DIRECTORY DragOpsCross USING [Word], Rope USING [ROPE]; SoftcardOps: CEDAR DEFINITIONS = BEGIN ROPE: TYPE = Rope.ROPE; Addr: TYPE = LONG CARDINAL; OneBit: TYPE = [0..1]; EUInternal: TYPE = [0..17B]; -- tbd EUPBusCmd: TYPE = MACHINE DEPENDENT RECORD[ -- tbd unused (0: 0..6): [0..177B] _ 0, userMode (0: 7..7): BOOL _ FALSE, unspecifiedAsYet (0: 8..15): [0..377B] _ 0 ]; IFUPBusCmd: TYPE = MACHINE DEPENDENT {noAccess (0), access (1)}; IFUInternalState: TYPE = MACHINE DEPENDENT RECORD[ -- tbd w0: WORD, w1: WORD, w2: WORD, w3: WORD ]; Error: SIGNAL[code: ATOM, explanation: ROPE _ NIL]; EstablishConnection: PROC[host: ROPE] RETURNS[ok: BOOL]; CloseConnection: PROC; SetEUBrkPtAddr: PROC[addr: Addr]; -- EU will brkpt when this address is accessed SetIFUBrkPtAddr: PROC[addr: Addr]; -- IfU will brkpt when this address is accessed ReadEUCmd: PROC RETURNS[euPBusCmd: EUPBusCmd]; ReadIFUCmd: PROC RETURNS[ifuPBusCmd: IFUPBusCmd]; ReadEUPBusData: PROC RETURNS[value: DragOpsCross.Word]; ReadIFUPBusData: PROC RETURNS[value: DragOpsCross.Word]; ReadClock: PROC RETURNS[value: LONG CARDINAL]; ReadEUInternalRegsiter: PROC[which: EUInternal] RETURNS[value, extra: DragOpsCross.Word]; WriteEUInternalRegsiter: PROC[which: EUInternal, value, extra: DragOpsCross.Word]; ReadIFUInternalState: PROC RETURNS[ifuState: IFUInternalState]; WriteIFUInternalState: PROC[ifuState: IFUInternalState]; ClockControl: TYPE = MACHINE DEPENDENT RECORD[ reserved (0: 0..7): [0..377B], freqSelect (0: 8..9): [0..3], -- choice of four frequencies for the Dragon clock phaseAdjust (0: 10..12): [0..7], -- adjust phase between Dragon and Softcard delay (0: 13..15): [0..7] -- adjust the delay between FA and FB ]; ReadClockControl: PROC RETURNS[clockControl: ClockControl]; WriteClockControl: PROC[clockControl: ClockControl]; ControlBit: TYPE = { interruptDragonToIOP, interruptDragonToMesa, writeParity, virtualMemAccessIOP, virtualMemAccessMesa, virtualMemAccessIFU, virtualMemAccessEU, ifuBreakpointEnabled, euBreakpointEnabled, IOPIntToDragon, mesaIntToDragon }; DragonPhase: TYPE = { phaseA, betweenAandB, phaseB, betweenBandA}; ReadControlBit: PROC[which: ControlBit] RETURNS[current: BOOL]; SetControlBit: PROC[which: ControlBit] RETURNS[previous: BOOL]; ResetControlBit: PROC[which: ControlBit] RETURNS[previous: BOOL]; ResetIFUCacheStateMachine: PROC; ResetEUCacheStateMachine: PROC; DisableIFUCache: PROC; DisableEUCache: PROC; FlushIFUCache: PROC; FlushEUCache: PROC; DragonHaltOrStep: PROC[phase: DragonPhase _ phaseA]; DragonRun: PROC; ResetCounter: PROC; StatusBit: TYPE = { periodicIntToDragon, -- 16HZ periodic interrupt memoryError, -- IOP access to Dragon memory caused a parity error euBkptReached, ifuBkptReached, mapError }; ReadStatusBit: PROC[which: StatusBit] RETURNS[current: BOOL]; ResetStatusBit: PROC[which: StatusBit] RETURNS[previous: BOOL]; MesaMapEntry: TYPE = MACHINE DEPENDENT RECORD[ unused (0: 0..11): [0..3777B] _ 0, dp (0: 12..15): [0..17B] _ 0 ]; MesaMapIndex: TYPE = [0..7]; ReadMesaMap: PROC[index: MesaMapIndex] RETURNS[value: MesaMapEntry]; WriteMesaMap: PROC[index: MesaMapIndex, value: MesaMapEntry]; DragonMapEntry: TYPE = MACHINE DEPENDENT RECORD[ fault (0: 0..0): BOOL _ TRUE, unused (0: 1..5): [0..37B] _ 0, rp (0: 6..15): [0..1777B] _ 0 ]; DragonMapIndex: TYPE = [0..37777B]; ReadDragonMap: PROC[index: DragonMapIndex] RETURNS[value: DragonMapEntry]; WriteDragonMap: PROC[index: DragonMapIndex, value: DragonMapEntry]; END. tSoftcardOps.mesa Copyright c 1986 by Xerox Corporation. All rights reserved. Willie-Sue, October 2, 1986 4:34:40 pm PDT ************************* -- EU internal registers tbd the IFU has only one internal state register the IFU has only one internal state register ************************* ************************* Control and status bits. NOTE: virtualMemAccessXX: if TRUE, the XX accesses to Dragon memory are using virtual addresses; if FALSE, physical addresses are being used allows selection of even or odd parity for subsequent writes; reads are always done with TDB parity; thus one can create a parity error Notation: Fx/Fy => between Fx and Fy enable by doing a FlushIFUCache enable by doing a FlushEUCache halt the dragon in the specified phase; if already halted, moves the Dragon to the specified phase (including a full step from Fx to Fx or from Fx/Fy to Fx/Fy no-op if Dragon is already running The following status bits can be read & reset ************************* Mapping between 2 megabytes of Daybreak physical address space and Dragon memory ************************* Access to the Dragon Map Κ ˜codešœ™Kšœ Οmœ1™