<> <> <> <> <> <<>> DIRECTORY SoftcardOps USING [ Addr, DragonMapEntry, DragonMapIndex, MesaMapEntry, MesaMapIndex]; SoftcardPrivate: CEDAR DEFINITIONS = BEGIN Addr: TYPE = SoftcardOps.Addr; OneBit: TYPE = [0..1]; SCBaseAddr: Addr = (LONG[28]*256*256); -- 3.5MB; <> <> <> <> <> <> <> <> <<>> <<(a) when bits indicated are fewer than 16, only those bits get used - others are ignored>> <<>> <<(b) The Softcard ignores the 8 most significant bits of the MS-part of a Dragon address>> <> <<>> <> <<>> <<>> <> <<>> BkptEUH: Addr = SCBaseAddr+0b800h; -- W [8..16); MS-part of brkp register for EU BkptEUL: Addr = SCBaseAddr+0b000h; -- W [16..32); LS-part of brkp register for EU BkptIFUH: Addr = SCBaseAddr+0a800h; -- W [8..16); MS-part of brkp register for IFU BkptIFUL: Addr = SCBaseAddr+0a000h; -- W[16..32); LS-part of brkp register for IFU SpyCmd1: Addr = SCBaseAddr+9800h; -- R [0..8); 8-bit PBus command of the EU SpyCmd2: Addr = SCBaseAddr+8800h; -- R [0..8); 2 bits used <> <> SpyEUDataH: Addr = SCBaseAddr+9000h; -- R [0..16); MS-part of PBus data of the EU SpyEUDataL: Addr = SCBaseAddr+9001h; -- R [16..32); LS-part of PBus data of the EU SpyIFUDataH: Addr = SCBaseAddr+8000h; -- R [0..16); MS-part of PBus data of the IFU SpyIFUDataL: Addr = SCBaseAddr+8001h; -- R [16..32); LS-part of PBus data of the IFU ClockH: Addr = SCBaseAddr+7800h; -- R [0..16); MS-part of Clock ClockL: Addr = SCBaseAddr+7801h; -- R [16..32); LS-part of Clock <> <<*************************>> <> <<>> <> <> <> <<>> <<>> <> < copy the specified internal state of the chip into the chip shift register>> < write the chip shift register into the internal state of the chip>> < shift one bit into or out of the chip shift register>> <<(depends on previous operation)>> <> <> DebugReadEU: Addr = SCBaseAddr+800h; -- Read EU internal register into shift register DebugWriteEU: Addr = SCBaseAddr+0h; -- Write shift register into EU internal DebugReadIFU: Addr = SCBaseAddr+1800h; -- Read IFU internal state into shift register DebugWriteIFU: Addr = SCBaseAddr+1000h; -- Write shift register into IFU DebugShiftA: Addr = SCBaseAddr+4000h; DebugShiftB: Addr = SCBaseAddr+4800h; DebugInfo: Addr = SCBaseAddr+2001h; -- RW [0..8); 8-bits of debugging info DebugInfoEntry: TYPE = MACHINE DEPENDENT RECORD[ debugInIFU (0: 0..0): OneBit _ 0, -- bit to shift into the IFU shift register debugInEU (0: 1..1): OneBit _ 0, -- bit to shift into the EU shift register unused (0: 2..3): [0..3B] _ 0, debugEUAddr (0: 4..7): [0..17B] _ 0, reserved (0: 8..15): [0..377B] _ 0 ]; <<>> <<*************************>> <<>> ClockControlAddr: Addr = SCBaseAddr+3001h; -- RW [8..16); 8-bits of clock control info <> <> <> <> <> <<];>> <<*************************>> <> < ConsultAndResetXXX>> <> <> Control1Bits: TYPE = MACHINE DEPENDENT RECORD [ resetDragon(0: 0..0): BOOL, notInterruptDragonToIOP(0: 1..1): BOOL, interruptDragonToMesa(0: 2..2): BOOL, dragonRun(0: 3..3): BOOL, dragonStep(0: 4..4): BOOL, writeParity(0: 5..5): BOOL, virtualMemAccessIOP(0: 6..6): BOOL, virtualMemAccessMesa(0: 7..7): BOOL, resetIFUCacheStateMachine(0: 8..8): BOOL, notResetIFUCache(0: 9..9): BOOL, enableIFUBkpt(0: 10..10): BOOL, virtualMemAccessIFU(0: 11..11): BOOL, resetEUCacheStateMachine(0: 12..12): BOOL, notResetEUCache(0: 13..13): BOOL, enableEUBkpt(0: 14..14): BOOL, virtualMemAccessEU(0: 15..15): BOOL ]; Control2Bits: TYPE = MACHINE DEPENDENT RECORD[ reserved (0: 0..7): [0..377B], iopIntToDragon (0: 8..8): BOOL, mesaIntToDragon (0: 9..9): BOOL, notResetCounter (0: 10..10): BOOL, unused (0: 11..15): [0..37B] _ 0 ]; ControlBits1Addr: Addr = SCBaseAddr+0c841h; -- read the control1 bits Consult1: Addr = ControlBits1Addr; ConsultAndChange1Base: Addr = SCBaseAddr+0c801h; CarDragon: Addr = ConsultAndChange1Base+0; CarNotInterruptDragonToIOP: Addr = ConsultAndChange1Base+4; <> CarInterruptDragonToMesa: Addr = ConsultAndChange1Base+8; CarDragonRun: Addr = ConsultAndChange1Base+12; <> <> CarDragonStep: Addr = ConsultAndChange1Base+16; <> CarWriteParity: Addr = ConsultAndChange1Base+20; <> CarVirtualMemAccessIOP: Addr = ConsultAndChange1Base+24; <> CarVirtualMemAccessMesa: Addr = ConsultAndChange1Base+28; <> CarIFUCacheStateMachine: Addr = ConsultAndChange1Base+32; CasIFUCacheStateMachine: Addr = CarIFUCacheStateMachine+2; CarNotResetIFUCache: Addr = ConsultAndChange1Base+36; CasNotResetIFUCache: Addr = CarNotResetIFUCache+2; <> CarEnableIFUBkpt: Addr = ConsultAndChange1Base+40; CarVirtualMemAccessIFU: Addr = ConsultAndChange1Base+44; <> CarEUCacheStateMachine: Addr = ConsultAndChange1Base+48; CasEUCacheStateMachine: Addr = CarEUCacheStateMachine+2; CarNotResetEUCache: Addr = ConsultAndChange1Base+52; CasNotResetEUCache: Addr = CarNotResetEUCache+2; <> CarEnableEUBkpt: Addr = ConsultAndChange1Base+56; CarVirtualMemAccessEU: Addr = ConsultAndChange1Base+60; <> ControlBits2Addr: Addr = SCBaseAddr+0c041h; -- read the control2 bits Consult2: Addr = ControlBits2Addr; ConsultAndChange2Base: Addr = SCBaseAddr+0c021h; CarIOPIntToDragon: Addr = ConsultAndChange2Base+0; CarMesaIntToDragon: Addr = ConsultAndChange2Base+4; CarNotResetCounter: Addr = ConsultAndChange2Base+8; <<>> <<*************************>> <> <<>> StatusBits: TYPE = MACHINE DEPENDENT RECORD[ dOutIFU (0: 0..0): OneBit, -- bit shifted out of the IFU shift register dOutEU (0: 1..1): OneBit, -- bit shifted out of the EU shift register phaseA (0: 2..2): BOOL, -- is the Dragon in periodicIntToDragon (0: 3..3): BOOL, -- 16HZ periodic interrupt notMemoryError (0: 4..4): BOOL, -- IOP access to Dragon memory saw a parity error euBkptReached (0: 5..5): BOOL, ifuBkptReached (0: 6..6): BOOL, mapError (0: 7..7): BOOL, reserved (0: 8..15): [0..377B] ]; ConsultStatusAddr: Addr = SCBaseAddr+0c041h; CarStatusBase: Addr = SCBaseAddr+0c001h; Car1PeriodicIntToDragon: Addr = CarStatusBase+0; Car1NotMemoryError: Addr = CarStatusBase+10h; Car1EUBrkptReached: Addr = CarStatusBase+14h; Car1IFUBrkptReached: Addr = CarStatusBase+18h; Car1MapError: Addr = CarStatusBase+1ch; <<>> <<*************************>> <> MesaMapEntry: TYPE = SoftcardOps.MesaMapEntry; MesaMapIndex: TYPE = SoftcardOps.MesaMapIndex; <> <> <> <> <<];>> <> MesaMapRec: TYPE = MACHINE DEPENDENT RECORD[ reserved0 (0: 0..15): [0..177777B] _ 0, mapEntry (1: 0..15): MesaMapEntry, reserved2 (2: 0..15): [0..177777B] _ 0, reserved3 (3: 0..15): [0..177777B] _ 0 ]; MesaMapAddr: Addr = SCBaseAddr + 0d000h; -- RW, 4 locations <> MesaMap: TYPE = ARRAY MesaMapIndex OF MesaMapRec; MesaMapBase: LONG POINTER TO MesaMap = LOOPHOLE[MesaMapAddr]; <<>> <<*************************>> <> <<>> DragonMapEntry: TYPE = SoftcardOps.DragonMapEntry; DragonMapIndex: TYPE = SoftcardOps.DragonMapIndex; <> <> <> <> <<];>> <> DragonMapRec: TYPE = MACHINE DEPENDENT RECORD[ reserved (0: 0..15): [0..177777B], mapEntry (1: 0..15): DragonMapEntry ]; DragonMapAddr: Addr = SCBaseAddr+LONG[256]*256*2; -- RW, 16K locations -- actually, 2*16K locations are allocated but only the odd locations are used DragonMap: TYPE = ARRAY DragonMapIndex OF DragonMapRec; DragonMapBase: LONG POINTER TO DragonMap = LOOPHOLE[DragonMapAddr]; <<>> END.