SoftcardOps.mesa
Copyright © 1986 by Xerox Corporation. All rights reserved.
Willie-Sue, February 9, 1987 5:39:05 pm PST
DIRECTORY
DragOpsCross USING [Word],
Rope USING [ROPE];
SoftcardOps: CEDAR DEFINITIONS = BEGIN
ROPE: TYPE = Rope.ROPE;
Addr: TYPE = LONG CARDINAL;
EUInternal: TYPE = MACHINE DEPENDENT {
left(0), right (1),  -- operands for ALU and field unit
st2A (2), st2B (3), st3A (4), -- pipeline for the data to be sent to Cache (store)
kReg (5),    -- a collection of control bits sent by the IFU
field (6),   -- the field descriptor
r2B (7), r3A (8), r3B (9),  -- pipeline for the output of the ALU
dataIn (15)   -- data back from the Cache
};
All registers are 32-bits; all except kReg & field are interpreted as 32-bit values
FieldDesc: TYPE = MACHINE DEPENDENT RECORD[
insert (0: 0..0): [0..1],
mask (0: 1..6): [0..37B],
shift (0: 7..12): [0..77B],
reserved (0: 13..15): [0..7B] ← 0,
reserved1 (1: 0..15): [0..177777B] ← 0
];
KReg: TYPE = MACHINE DEPENDENT RECORD[
aAddr (0: 0..7): [0..377B],  -- A address for the register file (left read port)
bAddr (0: 8..15): [0..377B], -- B address for the register file (right read port)
cAddr (1: 0..7): [0..377B],  -- C address for the register file (write port)
leftSrc (1: 8..9): [0..3B],  -- source for the `left' register (2 bits)
rightSrc (1: 10..12): [0..7B], -- source for the `right' register (3 bits)
st2ASrc (1: 13..14): [0..3B], -- source for the `st2A' register (2 bits)
st3ASrc (1: 15..15): [0..1]  -- source for the `st3A' register (1 bit)
];
EURegister: TYPE = RECORD[
val: SELECT tag: * FROM
regular => [rVal: DragOpsCross.Word],
kReg => [kVal: KReg],
field => [fVal: FieldDesc],
ENDCASE
];
EUPBusCmd: TYPE = MACHINE DEPENDENT RECORD[ -- tbd
unused (0: 0..6): [0..177B] ← 0,
userMode (0: 7..7): BOOL ← FALSE,
unspecifiedAsYet (0: 8..15): [0..377B] ← 0
];
IFUPBusCmd: TYPE = MACHINE DEPENDENT {noAccess (0), access (1)};
numIFUBits: CARDINAL = 30 * 16;  -- for debugging at the moment
IFUInternalState: TYPE = PACKED ARRAY [0..numIFUBits) OF [0..1];
Error: SIGNAL[code: ATOM, explanation: ROPE ← NIL];
EstablishConnection: PROC[host: ROPE] RETURNS[ok: BOOL];
CloseConnection: PROC;
SetEUBrkPtAddr: PROC[addr: Addr]; -- EU will brkpt when this address is accessed
SetIFUBrkPtAddr: PROC[addr: Addr]; -- IFU will brkpt when this address is accessed
ReadEUCmd: PROC RETURNS[euPBusCmd: EUPBusCmd];
ReadIFUCmd: PROC RETURNS[ifuPBusCmd: IFUPBusCmd];
ReadEUPBusData: PROC RETURNS[value: LONG CARDINAL];
ReadIFUPBusData: PROC RETURNS[value: LONG CARDINAL];
ReadClock: PROC RETURNS[value: LONG CARDINAL];
*************************
ReadEURegsiter: PROC[which: EUInternal] RETURNS[value: LONG CARDINAL];
WriteEURegsiter: PROC[which: EUInternal, value: LONG CARDINAL];
ReadIFUState: PROC RETURNS[ifuState: IFUInternalState];
the IFU has only one internal state register
WriteIFUState: PROC[ifuState: IFUInternalState];
the IFU has only one internal state register
*************************
ClockControl: TYPE = MACHINE DEPENDENT RECORD[
reserved (0: 0..7): [0..377B],
freqSelect (0: 8..9): [0..3],  -- choice of four frequencies for the Dragon clock
0 => not running
1 => 6.6 mhz
2 => 10 mhz
3 => 5 mhz
phaseAdjust (0: 10..12): [0..7], -- adjust phase between Dragon and Softcard
delay (0: 13..15): [0..7]  -- adjust the delay between FA and FB
];
ReadClockControl: PROC RETURNS[clockControl: ClockControl];
WriteClockControl: PROC[clockControl: ClockControl];
*************************
Control and status bits.
NOTE: virtualMemAccessXX:
if TRUE, the XX accesses to Dragon memory are using virtual addresses; if FALSE, physical addresses are being used
ControlBit: TYPE = {
resetDragon,
notInterruptDragonToIOP,
interruptDragonToMesa,
dragonRun,
dragonStep,
writeParity,
allows selection of even or odd parity for subsequent writes; reads are always done with TDB parity; thus one can create a parity error
virtualMemAccessIOP,
virtualMemAccessMesa,
virtualMemAccessIFU,
virtualMemAccessEU,
resetIFUCacheStateMachine,
notResetIFUCache,
ifuBreakpointEnabled,
resetEUCacheStateMachine,
notResetEUCache,
euBreakpointEnabled,
iopIntToDragon,
mesaIntToDragon,
notResetCounter
};
DragonPhase: TYPE = { phaseA, betweenAandB, phaseB, betweenBandA};
Notation: Fx/Fy => between Fx and Fy
ReadControlBit: PROC[which: ControlBit] RETURNS[current: BOOL];
SetControlBit: PROC[which: ControlBit] RETURNS[previous: BOOL];
ResetControlBit: PROC[which: ControlBit] RETURNS[previous: BOOL];
ResetIFUCacheStateMachine: PROC;
ResetEUCacheStateMachine: PROC;
DisableIFUCache: PROC;
enable by doing a FlushIFUCache
DisableEUCache: PROC;
enable by doing a FlushEUCache
FlushIFUCache: PROC;
FlushEUCache: PROC;
DragonHaltOrStep: PROC[phase: DragonPhase ← phaseA];
halt the dragon in the specified phase; if already halted, moves the Dragon to the specified phase (including a full step from Fx to Fx or from Fx/Fy to Fx/Fy)
DragonRun: PROC;
no-op if Dragon is already running
DragonStop: PROC;
no-op if Dragon is already stopped
ResetCounter: PROC;
StatusBit: TYPE = {
dOutIFU,
dOutEU,
phaseA,
The following status bits can be read & reset
periodicIntToDragon, -- 16HZ periodic interrupt
notMemoryError, -- IOP access to Dragon memory caused a parity error
euBkptReached,
ifuBkptReached,
mapError
};
ReadStatusBit: PROC[which: StatusBit] RETURNS[current: BOOL];
ResetStatusBit: PROC[which: StatusBit] RETURNS[previous: BOOL];
*************************
Mapping between 2 megabytes of Daybreak physical address space and Dragon memory
MesaMapEntry: TYPE = MACHINE DEPENDENT RECORD[
unused (0: 0..11): [0..3777B] ← 0,
dp (0: 12..14): [0..7B] ← 0,
ignored (0: 15..15): [0..1] ← 0
];
MesaMapIndex: TYPE = [0..3];
ReadMesaMap: PROC[index: MesaMapIndex] RETURNS[value: MesaMapEntry];
WriteMesaMap: PROC[index: MesaMapIndex, value: MesaMapEntry];
*************************
Access to the Dragon Map
DragonMapEntry: TYPE = MACHINE DEPENDENT RECORD[
fault (0: 0..0): BOOL ← TRUE,
unused (0: 1..5): [0..37B] ← 0,
rp (0: 6..15): [0..1777B] ← 0
];
DragonMapIndex: TYPE = [0..37777B];
ReadDragonMap: PROC[index: DragonMapIndex] RETURNS[value: DragonMapEntry];
WriteDragonMap: PROC[index: DragonMapIndex, value: DragonMapEntry];
END.