FieldUnit:
PROC [t,m: Word, q: FieldDescriptor, k: FieldDescriptor]
RETURNS [u: Word] = {
This procedure specifies the behavior of the Field Unit under control of a given FieldDescriptor, k. The Q register's low-order bits are also available as input as a FieldDescriptor. The inputs t & m are determined by the IFU.
op: ShiftOp ← k.op;
fd: FieldDescriptor ← IF k.pq THEN q ELSE k; -- may take specs from q register
maskSpec: FiveBits ← IF op = shift THEN fd.shift ELSE fd.mask;
shiftSpec: FiveBits ← fd.shift;
invertMask: BOOL ← FALSE;
su, mu, imu: Word;
SELECT op
FROM
extract => invertMask ← TRUE;
shift => invertMask ← fd.shiftSign;
insert => m ← t;
rCycle => invertMask ← TRUE;
ENDCASE => ERROR;
su ← ShiftUnit[t, m, shiftSpec, op = rCycle];
mu ← MaskUnit[maskSpec, op # shift];
imu ← WordNot[mu];
u ← WordAnd[su, IF invertMask THEN imu ELSE mu];
IF op = insert THEN u ← WordOr[WordAnd[imu, m], u];
};
ShiftUnit:
PROC [w0,w1: Word, shiftSpec: FiveBits, rcyc:
BOOL]
RETURNS [su: Word] = {
This procedure specifies the operation of the shift unit in the EU. The idea is to left shift the 64-bit quantity given by w0 & w1 by shiftSpec bits (unless rcyc, in which case we shift left by 32-shiftSpec bits). By convention, w0 is more left than w1.
dist: FiveBits ← shiftSpec;
IF rcyc
THEN
IF dist = 0
THEN RETURN [w1]
ELSE dist ← 32-shiftSpec;
su ← DoubleWordShiftLeft[w0, w1, dist];
};
MaskUnit:
PROC [maskSpec: FiveBits, ms0:
BOOL]
RETURNS [mu: Word] = {
This procedure specifies the operation of the mask unit in the EU. The idea is to generate a mask with maskSpec low-order bits of 0s, the remaining bits being 1s, unless maskSpec = 0 AND ms0, in which case, the mask is all 0s.
IF maskSpec = 0 AND ms0 THEN RETURN [ZerosWord];
mu ← DoubleWordShiftLeft[OnesWord, ZerosWord, maskSpec];
};