DIRECTORY RapunzelP2200V3 USING [SeqLong, SeqShort], Rope USING [ROPE]; SoftcardOps: CEDAR DEFINITIONS = BEGIN OPEN Rapunzel: RapunzelP2200V3; ROPE: TYPE = Rope.ROPE; Addr: TYPE = CARD32; SeqShort: TYPE = Rapunzel.SeqShort; SeqLong: TYPE = Rapunzel.SeqLong; EUInternal: TYPE = MACHINE DEPENDENT { left(0), right (1), -- operands for ALU and field unit st2A (2), st2B (3), st3A (4), -- pipeline for the data to be sent to Cache (store) kReg (5), -- a collection of control bits sent by the IFU field (6), -- the field descriptor r2B (7), r3A (8), r3B (9), -- pipeline for the output of the ALU dataIn (10) -- data back from the Cache }; FieldDesc: TYPE = MACHINE DEPENDENT RECORD[ insert (0: 0..0): [0..1], mask (0: 1..6): [0..37B], shift (0: 7..12): [0..77B], reserved (0: 13..15): [0..7B] _ 0, reserved1 (1: 0..15): [0..177777B] _ 0 ]; KReg: TYPE = MACHINE DEPENDENT RECORD[ aAddr (0: 0..7): [0..377B], -- A address for the register file (left read port) bAddr (0: 8..15): [0..377B], -- B address for the register file (right read port) cAddr (1: 0..7): [0..377B], -- C address for the register file (write port) leftSrc (1: 8..9): [0..3B], -- source for the `left' register (2 bits) rightSrc (1: 10..12): [0..7B], -- source for the `right' register (3 bits) st2ASrc (1: 13..14): [0..3B], -- source for the `st2A' register (2 bits) st3ASrc (1: 15..15): [0..1] -- source for the `st3A' register (1 bit) ]; EURegister: TYPE = RECORD[ val: SELECT tag: * FROM regular => [rVal: CARD32], kReg => [kVal: KReg], field => [fVal: FieldDesc], ENDCASE ]; EUPBusCmd: TYPE = MACHINE DEPENDENT RECORD[ -- tbd unused (0: 0..6): [0..177B] _ 0, userMode (0: 7..7): BOOL _ FALSE, unspecifiedAsYet (0: 8..15): [0..377B] _ 0 ]; IFUPBusCmd: TYPE = MACHINE DEPENDENT {noAccess (0), access (1)}; numIFUBits: CARD16 = 30 * 16; -- for debugging at the moment IFUInternalState: TYPE = PACKED ARRAY [0..numIFUBits) OF [0..1]; EstablishConnection: PROC[host: ROPE] RETURNS[ok: BOOL]; CloseConnection: PROC; SCError: SIGNAL[code: ATOM, explanation: ROPE _ NIL]; SetEUBrkPtAddr: PROC[addr: Addr]; -- EU will brkpt when this address is accessed SetIFUBrkPtAddr: PROC[addr: Addr]; -- IFU will brkpt when this address is accessed ReadEUCmd: PROC RETURNS[euPBusCmd: EUPBusCmd]; ReadIFUCmd: PROC RETURNS[ifuPBusCmd: IFUPBusCmd]; ReadEUPBusData: PROC RETURNS[value: CARD32]; ReadIFUPBusData: PROC RETURNS[value: CARD32]; ReadClock: PROC RETURNS[value: CARD32]; ReadEURegister: PROC[which: EUInternal] RETURNS[value: CARD32]; WriteEURegister: PROC[which: EUInternal, value: CARD32]; ReadIFUState: PROC RETURNS[ifuState: IFUInternalState]; WriteIFUState: PROC[ifuState: IFUInternalState]; ReadShort: PROC[addr: Addr] RETURNS[val: CARD16]; ReadForAffect: PROC[addr: Addr]; ReadLong: PROC[addr: Addr] RETURNS[value: CARD32]; WriteShort: PROC[addr: Addr, value: CARD16]; WriteLong: PROC[addr: Addr, value: CARD32]; WriteMultipleLong: PROC[num: CARD16, proc: PROC RETURNS[addr: Addr, value: CARD32]]; DumpShort: PROC[addr: Addr, num: CARD16] RETURNS[SeqShort]; DumpLong: PROC[addr: Addr, num: CARD16] RETURNS[SeqLong]; ClockControl: TYPE = MACHINE DEPENDENT RECORD[ reserved (0: 0..7): [0..377B], freqSelect (0: 8..9): [0..3], -- choice of four frequencies for the Dragon clock phaseAdjust (0: 10..12): [0..7], -- adjust phase between Dragon and Softcard delay (0: 13..15): [0..7] -- adjust the delay between FA and FB ]; ReadClockControl: PROC RETURNS[clockControl: ClockControl]; WriteClockControl: PROC[clockControl: ClockControl]; ControlBit: TYPE = { resetDragon, interruptDragonToIOP, interruptDragonToMesa, dragonRun, dragonStep, writeParity, virtualMemAccessIOP, virtualMemAccessMesa, virtualMemAccessIFU, virtualMemAccessEU, resetIFUCacheStateMachine, notResetIFUCache, ifuBreakpointEnabled, resetEUCacheStateMachine, notResetEUCache, euBreakpointEnabled, iopIntToDragon, mesaIntToDragon, notResetClock }; DragonPhase: TYPE = MACHINE DEPENDENT { phaseB(0), betweenBandA(1), phaseA(2), betweenAandB(3)}; DragonStepSize: TYPE = MACHINE DEPENDENT {quarter(1), half(2), full(4)}; ReadControlBit: PROC[which: ControlBit] RETURNS[current: BOOL]; SetControlBit: PROC[which: ControlBit] RETURNS[previous: BOOL]; ResetControlBit: PROC[which: ControlBit] RETURNS[previous: BOOL]; ResetIFUCacheStateMachine: PROC; ResetEUCacheStateMachine: PROC; DisableIFUCache: PROC; DisableEUCache: PROC; FlushIFUCache: PROC; FlushEUCache: PROC; DragonHaltInPhase: PROC[phase: DragonPhase _ phaseA]; DragonStep: PROC[size: DragonStepSize _ half] RETURNS[ok: BOOL]; DragonRun: PROC; DragonStop: PROC; ResetClock: PROC; ResetBoard: PROC; CurrentDragonPhase: PROC RETURNS[phase: DragonPhase, ok: BOOL]; StatusBit: TYPE = { dOutIFU, dOutEU, phaseA, periodicIntToDragon, -- 16HZ periodic interrupt notMemoryError, -- IOP access to Dragon memory caused a parity error euBkptReached, ifuBkptReached, mapError }; ReadStatusBit: PROC[which: StatusBit] RETURNS[current: BOOL]; ResetStatusBit: PROC[which: StatusBit] RETURNS[previous: BOOL]; MesaMapEntry: TYPE = MACHINE DEPENDENT RECORD[ unused (0: 0..11): [0..3777B] _ 0, dp (0: 12..14): [0..7B] _ 0, ignored (0: 15..15): [0..1] _ 0 ]; MesaMapIndex: TYPE = [0..3]; ReadMesaMap: PROC[index: MesaMapIndex] RETURNS[value: MesaMapEntry]; WriteMesaMap: PROC[index: MesaMapIndex, value: MesaMapEntry]; DragonMapEntry: TYPE = MACHINE DEPENDENT RECORD[ fault (0: 0..0): BOOL _ TRUE, unused (0: 1..5): [0..37B] _ 0, rp (0: 6..15): [0..1777B] _ 0 ]; DragonMapIndex: TYPE = [0..37777B]; ReadDragonMap: PROC[index: DragonMapIndex] RETURNS[value: DragonMapEntry]; WriteDragonMap: PROC[index: DragonMapIndex, value: DragonMapEntry]; END. îSoftcardOps.mesa Copyright c 1986 by Xerox Corporation. All rights reserved. Willie-Sue, March 13, 1987 4:58:01 pm PST All registers are 32-bits; all except kReg & field are interpreted as 32-bit values ************************* the IFU has only one internal state register the IFU has only one internal state register ************************* raises an error if addr is odd raises an error if addr is odd raises an error if addr is odd ************************* 0 => not running 1 => 6.6 mhz 2 => 10 mhz 3 => 5 mhz ************************* Control and status bits. NOTE: virtualMemAccessXX: if TRUE, the XX accesses to Dragon memory are using virtual addresses; if FALSE, physical addresses are being used allows selection of even or odd parity for subsequent writes; reads are always done with TDB parity; thus one can create a parity error Notation: Fx/Fy => between Fx and Fy enable by doing a FlushIFUCache enable by doing a FlushEUCache halt the dragon in the specified phase; if already halted, moves the Dragon to the specified phase returns FALSE if the dragon is running, mkaing a specified step difficult no-op if Dragon is already running no-op if Dragon is already stopped resets the entire dragon state on the softcard board returns ok = FALSE if dragon is running The following status bits can be read & reset ************************* Mapping between 2 megabytes of Daybreak physical address space and Dragon memory ************************* Access to the Dragon Map ÊÆ˜codešœ™Kšœ Ïmœ1™