Low Cost Test Systems
Richard Barth and James Gasbarro
Draft of March 7, 1989 12:20:59 pm PST
1.0 Introduction
The automatic test equipment industry had revenues of about $2.8 billion in 1988 [VLSI1]. This revenue was split evenly between integrated circuit testers and printed circuit board testers. Another market, which is just emerging, is the hardware modeling market [VLSI2]. General purpose digital test systems are currently available in two price ranges, $200K-$500K and $1M-$4M. Hardware modelers are in the $100K range. The technology described here is applicable to all of these markets and can deliver the same, or better, capability, with the exception of vector depth, as any existing product, but with a unit manufacturing cost of $1K-$3K.
1.1 Digital Electronic Test Systems
Every electronic system must be tested during the manufacturing cycle to ensure that it meets specifications. Digital electronic system specifications are comprised of power supply, temperature, timing and function specifications. Power supply and temperature specifications are limited to the specification of minimum and maximum values. Timing and function specifications are much more complex. Timing specifications define the relative placement in time of voltage transitions between the zero and one values. Function specifications define the output values over time given a set of input values at specified times. As a device operates, the timing specifications determine the details, while the function specifications determine the operation over longer periods of time.
General purpose digital test systems make use of this split between timing and function specification in their design. Their implementation is divided into the data generator section, which implements the function specification, and the pin electronics section, which implements the timing specification. A vector consists of the values to be forced on the inputs of the device under test, or DUT, and the values to be checked on the outputs. Time is divided into periods, called cycles. The test system stores one vector per cycle. During each cycle, the pin electronics section is responsible for combining the contents of the current vector with the timing information to produce the waveforms for stimulating the DUT and measuring the result.
Digital test systems have, in the past, been divided into two major categories: printed circuit board testers and integrated circuit testers. The reason for this dichotomy is the difference in scale between the two implementation techniques. Printed circuit boards are sufficiently large (physically) that it is possible to probe the board internally and ensure that it is constructed correctly by checking the individual traces. In contrast, integrated circuits are so small that it is not possible to probe them internally; only the pins can be accessed. All information must pass through these pins, both for test purposes, and in actual operation. Some modern printed circuit boards have become sufficiently dense that it is no longer possible to adequately test them via probes on their surface. Instead, test techniques previously reserved for integrated circuit testing must be applied to them.
1.2 Hardware Modeling
All complex electronic system design makes heavy use of simulation to ensure that a design is correct before the time consuming, expensive process of fabrication is begun. Hardware modeling uses a physical device, rather than a software program, to model a high complexity device in such a simulation. This has become important as the complexity of components has risen to such a level that writing complete, accurate models in a timely fashion, i.e. before the device is obsolete, has become impossible.
If we look at the basic functionality of a hardware modeller we see that it consists of the same data generator and pin electronics sections as a digital test system. The only difference is that a hardware modeller is interrogating the DUT for its response rather than checking that the response matches a predetermined value. It is assuming that the DUT is correct rather than checking it for correctness.
1.3 Mechanical Aspects
In addition to the electronic portion of a test system there must be a mechanical portion which holds the physical device. The type of testing being performed, either design verification or production, determines the mechanism.
1.3.1 Engineering Verification
The simplest arrangement consists of a zero insertion force socket into which the DUT is inserted by hand. This is effective for engineering verification and is one of the methods supported by all of the test equipment manufacturers. This method is typically used by ASIC design engineers.
Another mechanism is the manual probe station typically used by full custom integrated circuit designers. This station has a ring of needles mounted in it which allows the pins of the device to be connected to the test system. A microscope is placed over the device and a mechanical probe is used to access the internal nodes of the device.
Probing the internal nodes of a device with mechanical probes is becoming more and more difficult as the feature size of these devices shrinks. Below one micron it becomes extraordinarily difficult, if not impossible, to probe devices in this manner. This difficulty has led to the introduction of electron beam probers. These probers utilize scanning electron microscopy technology to replace the probe needle. Either packaged parts or undiced wafers can be placed in these probers.
1.3.2 Production Testing
Production testing is split into two types, wafer sort and final test. These correspond to the form of the device, either as a whole wafer, or as a packaged part.
Wafer sort mechanical systems consist of a mechanism for moving wafers from and to cassettes, placing them on, and removing them from, a precision x-y stage, and aligning the wafers to a set of probe needles. The x-y stage steps the needles across all the die on a wafer.
Packaged part mechanical systems take tubes of parts and automatically insert them into the equivalent of the zero insertion force socket used for engineering verification.
Both types of systems are mechanically complex, especially the wafer sort systems. The wafer sort systems cost about $100K.
1.4 Engineering Interface
The mechanical system is only one of the two interfaces which a test system must consider. The other is the interface to the design or test engineer. How does the engineer describe the correct operation of a device so that the tester can check it? How does the engineer relate failures discovered by the tester back to his original design description?
The engineer has already described the correct operation of the device once in order to simulate the design prior to fabrication. This same description forms the nucleus of the vectors and timing description which the tester requires.
Typically both the design description and the description of correct operation are available on an engineering workstation. The engineer would like to control the tester and interpret the tester results in the same fashion as the simulation was controlled.
2.0 Technology
An extended description of motivations, research, and development of this technology can be found in [Gasbarro2]. The existing artifacts consist of
a single chip implementation of the data generator and pin electronics functions,
a debugging fixture,
a Multibus-I interface board,
debugging and calibration software,
software which drives a DUT given ASCII files easily understood by a design engineer.
The major artifact is the data generator and pin electronics chip, or channel chip. It combines functions which require multiple boxes of hardware in existing products into a single chip. It has an interface easily driven by a host computer and 16 pins which can connect to a DUT. A 256 pin tester can be constructed from 16 of these chips and a small amount of interface and timing logic.
The major novelty of this chip is simply its size. It is the first integration of so many tester functions into a single chip. This integration is the source of the major cost reduction. The high level of integration is enabled by novel vector compression and timing generation techniques.
3.0 Property Rights
The development of this technology was mostly performed on Xerox time and with Xerox facilities as a part of the second author's Phd thesis work. Mark Horowitz, a Stanford University professor, is the thesis advisor. It is our understanding that neither he nor Stanford University will make any claim upon the patentable inventions contained in this work.
There were multiple fabrication runs during the development of the channel chip. Some of these runs were paid by Xerox. Others were fabricated through the MOSIS implementation service and were paid with funds controlled by Mark Horowitz.
An invention proposal was filed with Xerox at the beginning of February 1989. We are currently preparing succinct descriptions of the patentable ideas so that a preexamination patent search can be performed.
The timing techniques were described in a paper published in May 1988 [Gasbarro1].
The thesis defense occurred March 2, 1988. The compression ideas were made public at this point, but were not widely distributed.
The thesis will be made available through Stanford University prior to June 1989.
4.0 Market Definition
Two scenarios are sketched here. One follows the traditional method of delivering test systems to customers. In this scenario a company is formed which designs the integrated circuits and printed circuit boards, contracts for their fabrication, and packages them into a system along with the software and documentation required by design engineers to utilize the system. This scenario is intended to include any partnership arrangements which might be formed with existing companies that follow this model, such as verfication station manufacturers like IMS. This is the systems scenario.
The systems scenario starts with the introduction of packaged integrated circuit verification stations, later pushing into e-beam probers, automated handlers, and the board level and hardware modeling markets.
Another scenario recognizes the fundamental change in delivery strategy which the radical change in cost engenders. In this scenario a company is formed which designs the integrated circuits, one or two evaluation boards, and the low-level software which mates these circuits to existing test system engineering practices. The major business of such a company is the sale of integrated circuit components to system houses. This scenario is intended to include any partnership arrangements which might be formed with existing companies that follow this model, such as integrated circuit manufacturers like TI, or design houses such as Chips & Technologies. This is the components scenario.
Chips & Technologies is an excellent example of the components scenario played out in a different market. They recognized that there is a large market for the components which form the heart of IBM PC compatibles. Rather than entering the cut throat systems business, they were the first to introduce the components as commodity parts. The lead which they developed has been very difficult for any other design house to overcome.
The reduction in size and cost makes the test system electronics substantially cheaper than the mechanical portion of the test system, with the exception of engineering verification of packaged parts. However, since the engineer would like to use the same interface to control the tester as was used to run the simulations of the device, the test system electronics is still the cheap partner in this situation because an engineering workstation costs far more than a tester. Thus, in all situations, the tester is now a subsystem of some other system, be it mechanical or a computer. Buying decisions will be based on factors other than the capabilities of the tester.
The single inherent limitation of the new technology, compared to the old, is the limited vector depth. Production final test is the only application area which is likely to be sensitive to this limitation. Even this limitation is only serious for dynamic devices. Wafer sort is relatively insensitive to this limitation.
5.0 Product Development
Product development is split into three categories: productizing the current design, designing an advanced version, and system development. Productizing the current design can be eliminated if it is decided that its functionality is insufficient to support a product. Designing an advanced version is required for any scenario. System development can be downsized to producing a prototype if the components scenario is chosen. No time or cost estimates are given because they are so dependent on the group of people gathered to do this job.
5.1 Current Design Productization
This is defined as getting the current channel chip ready to put into a system, not to build a system. Proof of concept from a research point of view has been completed. A great deal of work remains to document the specifications of the channel chip and to ensure that it meets those specifications.
Some of the things which must be done include:
chip
Dynamic RAM bug removal
torture testing
designer hiring
fabrication process selection
tool selection, procurement, and training
design transliteration into new tool set
production test development
fabrication
documentation
printed circuit board
designer hiring
tool selection, procurement, and training
design
fabrication
test
software
engineer hiring
development environment selection, procurement, and training
existing software transliteration into new environment
diagnostic development
demonstration development
integration
chips on board, plugged into PC, running software, all debugged
application notes
The current design can be improved simply by shrinking it to a state of the art process. TI has already shown some interest in the channel chip as an interesting use for their 0.7 micron Bi-CMOS process. Since they are a large integrated circuit manufacturer they can easily see the impact of the technology and are likely to be interested in a business arrangement.
5.2 Advanced Design Development
The advantages of redesigning the channel chip are discussed in detail in [Gasbarro2]. Improvements can be made by increasing density or capability. Unless DUT pin counts exceed 256, increased density only results in a modest decrease in system price. Thus increased capability should be the target of a redesign.
Three areas of capability improvement are possible: more flexible channel electronics, increased vector RAM size, and higher performance DUT drive and sense circuits. High performance DUT drive and sense is substantially improved if an advanced technology such as Bi-CMOS is available. This would allow the channel chip to dominate the characteristics, except for vector depth, of every tester currently on the market, even those costing several million dollars.
The hardware modelling application requires sampling the response rather than comparing against a predicted result. One could just predict all zero and then use the error buffer for determining which values were actually ones but that limits the number of unknown cycles to the depth of the error buffer.
All of the chip development items mentioned in section 5.1 must be performed for the new device.
5.3 System Development
This section assumes that all of the work in section 5.1 has been completed and that the goal is to produce a system which can be placed directly into the hands of integrated circuit designers.
An interface must be built to transfer test data from any CAD environment into the test environment. The detailed work for the most popular CAD environments must be completed and the interface documented so that any weird systems can be interfaced by the customer. OEM agreements with the major CAD houses would ease this problem substantially and allow a much higher quality solution.
All of the standard test system software must be written. This includes shmoo plotting and other failure analysis software.
A salable implementation of the computer interface and timing generator must be included in the printed circuit board design effort. This may require the design of an ASIC.
Large quantities of high quality documentation must be written, marketing and sales support established, customer hot lines set up, etc, etc.
5.4 A Scenario
Suppose that the intention is to move into the market as soon as possible with a redesigned channel chip and its associated evaluation board.
Development assumptions:
A semiconductor house supplies a static RAM core for storing vectors. TI has expressed interest due to contacts through Mark Horowitz. We have had discussions with National about obtaining such a RAM core because of another project. Cypress has the technology, local location, and fast pace needed.
The selected semiconductor house supplies the engineering development environment for both the integrated circuit and the evaluation board.
It also supplies manpower in the form of integrated circuit, printed circuit board, test, and software engineers as well as layout designers.
The authors spend 6 months at the semiconductor house to transfer the design knowledge.
The engineering labor requires 6 engineers, a technical writer, and 2 layout designers for 1 year at a cost of $500K.
Two fabrication runs are required to produce samples and another run is required to produce the first fully qualified parts at a cost of $50K per run or $150K.
Other expenses, including printed circuit board fabrication, run about $100K
A contract that permits the engineering work to begin is signed by June 1989 and, therefore, the devices are available in sample quantities by third quarter 1990 and in volume the following quarter.
Market assumptions:
It is the semiconductor house's responsibility to market the devices and evaluation boards to engineering workstation, packaged part handler, and prober manufacturers.
Engineering workstation companies take one year from device availability to volume shipments of packaged part verification stations and two years to shipment of hardware modelers.
Half of the workstations already in the field will purchase this technology as a retrofit and half of all new workstations will be purchased with this technology as an add on.
The number of installed ASIC engineering workstations by third quarter 1991 is aaa.
ASIC engineering workstations are sold at the rate of bbb per year starting in third quarter 1991.
Automatic packaged part handler manufacturing companies take a year from device availability to product introduction.
Automatic packaged part handlers are sold at a rate of ccc per year starting in third quarter 1991.
Prober manufacturing companies, both electron beam analysis probers and wafer sort probers, take two years from device availability to product introduction.
Wafer sort probers are sold at a rate of ddd per year starting in third quarter 1992.
Electron beam probers are sold at a rate of eee per year starting in third quarter 1992.
These assumptions require an investment of about $750K through third quarter 1990 and start producing a return by third quarter 1991, with return ramping up quickly through third quarter 1993, followed by a slight drop as pent up demand is satisfied, and finally reaching a steady state sometime in 1994.
Ways to go about getting the numbers:
Call Dave Stamm and ask him what the relationship between cost and volume might be.
Call Valid people and ask the same questions.
Get IEEE membership survey and figure out how many are ASIC designers.
Dataquest? Go to library and ask:
How big is the engineering workstation market?
How many of these are sold by ASIC designers
Also need to talk to potential customers, i.e. ASIC designers, production test people. Get Xerox people in to look at the thing, or take it to them. Road trip to El Segundo, Bob St. John. Find out relative importance of features.
Electronics January 1989
Data
Integrated circuit testers, $1.45B, 1989, growing about 10% per year.
ASIC-prototype verification systems, 50% growth for 1989 to $75M, $35M 1987, $50M, 1988.
HP has $50K box, HP82000 model D50
Tek LV500, $55K-$172K
Design Work Stations
PC $31M 1989
32-bit $284M 1989
Interpretation
Assume average sales price of $1.5M for production general purpose IC tester and that 50% of the integrated circuit tester dollar volume is for such testers. Then unit volume of production general purpose IC testers is (($1.45B*0.50)/$1.5M), or 483.
Assume average sales price of $5K for PCs, and that 10% of the PCs will be used for ASIC prototype verification. Then unit volume of ASIC prototype verification PCs is ($31M/$5K)*0.10 or 620.
Assume average sales price of $50K for 32-bit work stations, and that 10% of the work stations will be used for ASIC prototype verification. Then unit volume of ASIC prototype verification work stations is ($284M/$50K)*0.10 or 568.
Assume that each system unit contains 16 channel chips. Assume market penetration of 50%. Then unit volume of channel chips is (483+620+568)*16*0.50, or 13368.
Coming at it from the established market for ASIC-prototype verification systems angle. Assume average sales price of $200K. Then unit volume of ASIC-prototype verification systems is ($75M/$200K), or 375. This says that there is an untapped market of (620+568)/375 or three times the existing market if the assumption of 10% of workstations which would like to have the capability, but do not because of cost reasons, is correct.
So how much are people willing to pay per unit? If a system sells for $50K and there is a three times markup that leaves $16K component purchase and manufacturing. Assume boards cost $1K to make that leaves $15K for the components or about $1K per piece.
Financials
So you have to dig a million dollar hole for development and marketing and sales for a couple years before any return comes in. Your UMC comes to about $150. Your volume is about 10K. So your ongoing cost is about $1.5M. Sales price of $1K per unit means $10M in sales. So you make about $8.5M gross profit per year minus retiring the $1M development cost. The item is probably only good for about 2 years of heavy volume so total gross profit is about $15M.
Of course since going from chips to boards is the easy part cutting out the middleman might be the best way to go. Then profits could rise to the $50M range, which starts to get interesting. The notion of a commodity item perhaps is not justified, there simply isn't enough volume to make a respectable business out of it.
6.0 Unit Manufacturing Costs
This section describes the manufacturing cost of a packaged part test board which plugs into any computer with a Centronic printer port (read IBM PC or compatible plus others).
Assume
masks amortized over sufficient runs to make no contribution,
a 1.6 micron DLM CMOS run costs $20K,
each run consists of 10 wafers,
each 5" wafer holds 70 die,
yield of 25%,
test and packaging cost of $20,
Then each packaged and tested channel chip costs about $150. This is a high estimate. If sufficient volume develops this price could drop to about $50.
Assume
board fabrication and test costs $500
timing generator gate array costs $50
channel chips cost 16*$150 or $2400
zero-insertion-force 256 pin socket costs $20
PGA socket to 48 and 40 pin DIP socket adaptors cost $20
power bypass capacitors cost $1
power programming pins cost $10
power supply posts (3 @ $1) cost $3
bag of blue push on doobies for programming supply cost $10
cable connector costs $5
Centronics port to board cable costs $10
floppy disk with software written on it costs $10
documentation reproduction costs $10
Then each system costs about $3K
As is obvious from the above cost estimate the major value added comes from producing the channel chips and the remainder comes from producing the printed circuit board which integrates these chips into a system. However, there is a large nonrecurring engineering cost to acquire the appropriate software to put on the floppy disk and there are ongoing costs to support the products in the field.
7.0 Competition
Existing testers fall into three fairly well defined price ranges. The very low-end testers are simply parallel word generators attached to PC-class computers. They provide only low-speed vector generation and capture under software control with no analog timing or voltage parameters. The mid-range machines provide much greater speed capability (up to 100MHz) as well as flexibility in timing and voltage characteristics. High-end testers mainly extend the performance capability of the mid-range testers, providing greater speed, timing accuracy and vector depth. The following list is a breakdown of manufacturers and the categories in which they offer products:
Low-End ($1K-10K)
MTS
Mid-Range ($200K-400K)
ASIX
Cadic
Hi-Level
HP
IMS (Valid)
Tektronix
High-End ($1M and up)
AdvanTest
Ando
GenRad
Mega-Test
Sentry
Teradyne
Trillium
Hardware modeling is still in its infancy. A survey of the market can be found in [VLSI3].
The major reduction in cost will completely change the structure of this industry. It will move from a low volume, labor intensive, high markup, expertise dominated industry into a medium volume, low labor, low markup, high technology industry. In the long run the large capitalization, low cost of sales, and technologically sophisticated sales force of HP or Tektronix will be necessary to play in this game.
8.0 Conclusion
Following the systems scenario assumes that the radical reduction in the cost of the test system does not require a change in marketing strategy. This seems very unlikely. The components scenario is the correct approach to bringing this technology to market. It lowers the initial investment substantially.
References
[Gasbarro1]
J. Gasbarro, Integrated Pin Electronics for VLSI Functional Testers, Proceedings of the Custom Integrated Circuits Conference, May, 1988.
[Gasbarro2]
J. Gasbarro, An Architecture For High-Performance Single-Chip VLSI Testers, Phd thesis to be submitted to Stanford University, <June, 1989.
[VLSI1]
R. Wittenberg, Has the ATE Industry Reached a Plateau?, editorial, VLSI Systems Design, September, 1988.
[VLSI2]
L. Widdoes and H. Stump, Hardware Modeling, VLSI Systems Design, July, 1988.
[VLSI3]
VLSI Systems Design Staff, Hardware Modelers, VLSI Systems Design, September, 1988.