<> <> <> <> <<>> DIRECTORY CoreClasses, CoreCreate, CoreFlat, CoreOps, Static, TerminalIO; TestStatic: CEDAR PROGRAM IMPORTS CoreClasses, CoreCreate, CoreFlat, CoreOps, Static, TerminalIO = BEGIN CreateInverter: PROC [] RETURNS [cellType: CoreCreate.CellType] = { In: CoreCreate.Wire _ CoreOps.CreateWire[name: "In"]; Out: CoreCreate.Wire _ CoreOps.CreateWire[name: "Out"]; Gnd: CoreCreate.Wire _ CoreOps.CreateWire[name: "Gnd"]; Vdd: CoreCreate.Wire _ CoreOps.CreateWire[name: "Vdd"]; ntrans: CoreClasses.CellInstance _ NEW [CoreClasses.CellInstanceRec _ [ actual: CoreOps.CreateWire[LIST [In, Out, Gnd]], type: CoreClasses.CreateTransistor[[nE]] ]]; ptrans: CoreClasses.CellInstance _ NEW [CoreClasses.CellInstanceRec _ [ actual: CoreOps.CreateWire[LIST [In, Out, Vdd, Vdd]], type: CoreClasses.CreateTransistor[[pE]] ]]; cellType _ CoreClasses.CreateRecordCell[ public: CoreOps.CreateWire[LIST [In, Out, Gnd, Vdd]], internal: CoreOps.CreateWire[LIST [In, Out, Gnd, Vdd]], instances: LIST [ntrans, ptrans], name: "Inverter" ]; }; Create2Inverter: PROC [] RETURNS [cellType: CoreCreate.CellType] = { In: CoreCreate.Wire _ CoreOps.CreateWire[name: "In"]; Out: CoreCreate.Wire _ CoreOps.CreateWire[name: "Out"]; Gnd: CoreCreate.Wire _ CoreOps.CreateWire[name: "Gnd"]; Vdd: CoreCreate.Wire _ CoreOps.CreateWire[name: "Vdd"]; Intern: CoreCreate.Wire _ CoreOps.CreateWire[name: "Intern"]; InInternOut: CoreCreate.Wire _ CoreCreate.WireList[LIST[In, Intern, Out], "InInternOut"]; inverter: CoreCreate.CellType _ CreateInverter[]; first: CoreClasses.CellInstance _ NEW [CoreClasses.CellInstanceRec _ [ actual: CoreOps.CreateWire[LIST [In, Intern, Gnd, Vdd]], type: inverter ]]; second: CoreClasses.CellInstance _ NEW [CoreClasses.CellInstanceRec _ [ actual: CoreOps.CreateWire[LIST [Intern, Out, Gnd, Vdd]], type: inverter ]]; cellType _ CoreClasses.CreateRecordCell[ public: CoreOps.CreateWire[LIST [In, Out, Gnd, Vdd]], internal: CoreOps.CreateWire[LIST [In, Out, Gnd, Vdd, Intern, InInternOut]], instances: LIST [first, second], name: "Inverter2" ]; }; <<>> CreateBrokeInverter2: PROC [] RETURNS [cellType: CoreCreate.CellType] = { In: CoreCreate.Wire _ CoreOps.CreateWire[name: "In"]; Out: CoreCreate.Wire _ CoreOps.CreateWire[name: "Out"]; Gnd: CoreCreate.Wire _ CoreOps.CreateWire[name: "Gnd"]; Vdd: CoreCreate.Wire _ CoreOps.CreateWire[name: "Vdd"]; InternA: CoreCreate.Wire _ CoreOps.CreateWire[name: "InternA"]; InternB: CoreCreate.Wire _ Static.UnconnectedOK[CoreOps.CreateWire[name: "InternB"]]; inverter: CoreCreate.CellType _ CreateInverter[]; first: CoreClasses.CellInstance _ NEW [CoreClasses.CellInstanceRec _ [ actual: CoreOps.CreateWire[LIST [In, InternA, Gnd, Vdd]], type: inverter ]]; second: CoreClasses.CellInstance _ NEW [CoreClasses.CellInstanceRec _ [ actual: CoreOps.CreateWire[LIST [InternB, Out, Gnd, Vdd]], type: inverter ]]; cellType _ CoreClasses.CreateRecordCell[ public: CoreOps.CreateWire[LIST [In, Out, Gnd, Vdd]], internal: CoreOps.CreateWire[LIST [In, Out, Gnd, Vdd, InternA, InternB]], instances: LIST [first, second], name: "BrokeInverter2" ]; }; <<>> Test: PROC = { Check: Static.ConnectionCountProc = { TerminalIO.PutRope[CoreOps.GetFullWireName[wireRoot, wire]]; TerminalIO.PutRope[IF public THEN " of cell " ELSE " in cell "]; TerminalIO.PutRope[CoreOps.GetCellTypeName[cellType]]; TerminalIO.PutF[" has %g connections\n", [integer[count]]]; }; cellType: CoreCreate.CellType _ Create2Inverter[]; cutSet: CoreFlat.CutSet _ CoreFlat.CreateCutSet[cellTypes: LIST["Inverter"]]; TerminalIO.PutRope["\n"]; <> Static.CountLeafConnections[cellType, Static.CheckCount, cutSet]; TerminalIO.PutRope["\n"]; <> Static.CountLeafConnections[cellType, Static.CheckCount]; TerminalIO.PutRope["\n"]; cellType _ CreateBrokeInverter2[]; Static.CountDirectConnections[cellType, Static.CheckCount]; TerminalIO.PutRope["\n"]; Static.CountDirectConnections[cellType, Static.CheckCount, cutSet]; }; END.