This section describes the low level abstraction used to program the devices.
2.1 Basic Programming
Figure 1 shows the low-level wires from which all larger structures are built.
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Figure 1. Basic Interconnect
Output is the wire which carries the output of a basic gate. Input carries the input of a basic gate. RightDown is a short length of uncommitted wire whose direction is fixed to right or down. LeftUp is similiar but its direction is fixed to left or up. The dots on RightDown and LeftUp indicate that the value is inverted when making the transition across the wire segment. Long is a wire which extends across the width of a chip to enhance interconnect density and performance. Its direction is not fixed.
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Figure 2. Minor Array
Figure 2 shows an array of basic interconnects organized as a repetition in the horizontal and vertical directions. The basic interconnects are numbered, increasing from left to right, and top to bottom.
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Figure 3. Programming Primitives
Figure 3 portrays the graphical symbols used to program the array. Program indicates that an input wire is connected to an output wire through a gate. Inverter indicates that a signal is inverted. FlipFlop indicates that a signal flows through an edge-triggered flip-flop. The allowable placement locations for these tiles are described later in this document.
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Figure 4. Basic Logic Function Classification
Figure 4 classifies the 16 functions of 2 variables. A single output wire can perform the nand function of 5 variables. Through the use of De Morgan's theorems, the programmable number of inputs, and the propagation of inversions, this basic capability can perform any of the function classes except xor, which requires three output wires for implementation.
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Figure 5. Example Function
Figure 5 shows the programming of the function horizontal0 ← not (vertical0 * vertical2 * vertical3), in the top row of a minor array. The remaining 3 rows are elided for clarity. In this same manner all horizontal outputs can be functions of all the vertical inputs (not the RightDown, LeftUp, or Long lines), and all vertical outputs can be functions of all horizontal inputs. In addition, the input parallel to an output and of the same index can participate in the formation of the output as illustrated in figure 6, which computes horizontal0 ← not (horizontal0 * vertical0 * vertical2 * vertical3).
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Figure 6. Another Example Function
The input wire can be delayed by a flip-flop and/or inverted. Figure 7 shows the same function as figure 6 except that the horizontal input has been delayed and inverted.
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Figure 7. Example Function with Inversion and Delay
The interior of a chip is formed by tiling the plane with minor arrays. Figure 8 illustrates a 4 by 4 array. A realistic chip using 2 micron DLM CMOS has an array which is 16 by 16.
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Figure 8. Sample Chip Interior Tiling
In this array logical networks are constructed by connecting physical wires in straight lengths, either horizontally or vertically, and then connecting the vertical and horizontal segments together with corners formed from 1 input gates.
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Figure 9. Connection Tiles
Figure 9 displays the tiles used to connect segments of wire together. At each intersection of basic interconnects any combination of these tiles may be used except that no wire may be driven more than once. The titles indicate function as follows:
ORDToI - Output Right Down To Input
LUToLU - Left Up To Left Up
OLUToI - Output Left Up To Input
ORDToL - Output Right Down To Long
RDToRD - Right Down To Right Down
ORDToLU - Output Right Down to Left Up
LUToI - Left Up To Input
OLUToRD - Output Left Up To Right Down
LToI - Long To Input
RDToI - Right Down To Input
The tiles are shown here in the orientation used for horizontal interconnects. Each tile must be rotated 90 degrees, mirrored, and flipped before use in vertical interconnects. This cumbersome mechanism of tiles is used to simplify printing and parsing of assembly language programs. It also succinctly expresses the permissible interconnections amoung the 9 wires which participate at each junction. Only 10 connections are legal out of the 81 possible.
Figure 10 is an example of routing a logical net through several wires, utilizing 2 corners. The net begins in the top horizontal output of the left minor array, runs to the top horizontal input wire of the right minor array, goes through a corner onto the leftmost vertical output of the right minor array, is fed back to the left vertical input wire, through a corner, onto the second from top horizontal output, and finishes as the second from top horizontal LeftUp wire in the left minor array.
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Figure 10. Logical Net Example
Whenever a function requires the inverted form of an input, an Inverter symbol must be placed on the corresponding input. Figure 11 computes the OR of two variables by inverting the inputs.
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Figure 11. OR gate implementation
Some functions require an inverted output, e.g. the AND gate. This is achieved by inverting the destination inputs. Since each corner also introduces an inversion, the input inversion is actually controlled by the parity function of the input inversion requirement, the source output inversion requirement, and all of the corners between the source output and the input.
2.2 Pin Programming
Eventually the abstraction of an infinite plane of silicon must break down. At this point we introduce the traces of the printed circuit board, to which the pins of the integrated circuit are attached, into the abstraction. In this section we describe the details of connecting the inner array to the pcb traces.
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Figure 12. Minor Array with Pins
In figure 12 only one minor array is shown. In a real array, which is 16x16, there would be 64 pins on each edge instead of the 4 pins shown.
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Figure 13. Pin Connection Tiles
Figure 13 shows the tiles available to connect the pins to the array. The upper row is the set of tiles available for the left and top (when rotated 90 degrees, mirrored, and flipped) edges. The lower row is the set of tiles available for the right and bottom (when rotated 90 degrees, mirrored, and flipped) edges. When a tile appears in both rows this indicates that the tile may be used for any of the four edges. The titles indicate function as follows:
OToP - Output To Pin
RDToP - Right Down To Pin
LUToP - Left Up To Pin
LToP - Long To Pin
PToI - Pin To Input
PToRD - Pin To Right Down
PToLU - Pin To Left Up
PToL - Pin To Long