PipalWireIconsImpl.mesa
Copyright Ó 1986, 1987, 1988 by Xerox Corporation. All rights reversed.
Bertrand Serlet March 5, 1988 6:45:48 pm PST
Don Curry September 17, 1987 4:49:53 pm PDT
DIRECTORY
CD, CDCells, CDDirectory, CDEvents, CDInstances, CDLayers, CDProperties, CDRects, CDTexts, CDViewer, Core, CoreOps, CoreProperties, IO,
PipalCore, PipalSinix, PipalSisyph,
PW, TerminalIO, ViewerOps, WireIcons;
PipalWireIconsImpl: CEDAR PROGRAM
IMPORTS CD, CDCells, CDDirectory, CDEvents, CDInstances, CDLayers, CDProperties, CDRects, CDTexts, CDViewer, CoreOps, CoreProperties, IO, PipalCore, PipalSinix, PipalSisyph, PW, TerminalIO, ViewerOps
EXPORTS WireIcons
SHARES PipalSisyph = BEGIN OPEN WireIcons;
Utilities
font: CDTexts.CDFont ← CDTexts.MakeFont["Xerox/TiogaFonts/Helvetica8", 4];
AddRect: PROC [size, pos: CD.Position, il: CD.InstanceList] RETURNS [newIl: CD.InstanceList] = {
newIl ← CONS [CDInstances.NewInst[CDRects.CreateRect[size, CD.commentLayer], [pos]], il];
};
AddText: PROC [rope: ROPE, pos: CD.Position, il: CD.InstanceList] RETURNS [newIl: CD.InstanceList] = {
newIl ← CONS [CDInstances.NewInst[CDTexts.Create[rope, font], [pos]], il];
};
PutPin: PROC [wire: Wire, size, pos: CD.Position, il: CD.InstanceList] RETURNS [newIl: CD.InstanceList] = {
newIl ← AddRect[size, pos, il];
PipalCore.PutPins[PipalSisyph.mode.decoration, wire, LIST [[newIl.first.ob, newIl.first.trans]]];
};
EvalNat: PROC [cx: PipalSisyph.Context, expr: ROPE] RETURNS [nat: NAT] = {
WITH PipalSisyph.EvalToRef[cx, expr] SELECT FROM
refInt: REF INT => RETURN [NAT[refInt^]];
refNat: REF NAT => RETURN [refNat^];
ENDCASE => ERROR; -- Wrong type
};
Composer icon
MakeComposer: PUBLIC PROC [design: CD.Design, size: NAT] RETURNS [wire: Wire, obj: CD.Object] = {
l: INT = design.technology.lambda;
il: CD.InstanceList ← NIL;
increment: INT ← SELECT TRUE FROM
size<4 => 8, size<6 => 6, size<8 => 4, size<16 => 2, size<32 => 2, ENDCASE => 1;
wire ← CoreOps.CreateWires[size: size];
The big rectangle
il ← AddRect[[increment*(size-1)*l+7*l/2, 7*l/2], [0, l/2], il];
The structured wire
il ← PutPin[wire, [l/2, l/2], [increment*(size-1)*l/2+2*l, 4*l], il];
The composed wires
FOR i: NAT IN [0 .. size) DO
wire[i] ← CoreOps.CreateWire[];
il ← PutPin[wire[i], [l/2, l/2], [increment*i*l+2*l, 0], il];
ENDLOOP;
The first composed wire
il ← AddRect[[l, l/2], [3*l/2, 0], il];
obj ← PW.CreateCell[instances: il, props: LIST [[$ComposerSize, NEW [INT ← size]], [PipalSisyph.mode.extractProcProp, $WireIconsExtractComposer]]];
CDCells.SetSimplificationTreshhold[obj, 10.0];
};
Composer: PW.GeneratorProc = {
name: ROPE;
int: INT ← TerminalIO.RequestInt["Size of the composer? "];
IF int<1 THEN {TerminalIO.PutF["*** Incorrect parameter.\n"]; RETURN};
name ← IO.PutFR["::Composer[%g].icon", IO.int[int]];
ob ← CDDirectory.Fetch[design, name].object;
IF ob=NIL THEN {
ob ← MakeComposer[design, NAT [int]].obj;
[] ← CDDirectory.Include[design, ob, name];
};
};
ExtractComposer: PipalSinix.ExtractProc = {
cx: PipalSisyph.Context = NARROW [userData];
refNat: REF INT ← NARROW [CDProperties.GetObjectProp[obj, $ComposerSize]];
size: NAT ← NAT [refNat^];
result ← MakeComposer[PipalSisyph.GetDesign[cx], size].wire;
};
Composer icon - Adjustable grid and line width
AdjGridWidthComposer: PW.GeneratorProc = {
name: ROPE;
grid: INT ← Grid[design];
n:  INT ← TerminalIO.RequestInt["Size of the composer? "];
w:  INT ← CDLayers.LayerWidth[design, CD.commentLayer];
IF n<1 THEN {TerminalIO.PutF["*** Invalid parameter.\n"]; RETURN};
name ← IO.PutFR["ComposerP%gW%g[%g].icon", IO.int[grid], IO.int[w], IO.int[n]];
ob ← CDDirectory.Fetch[design, name].object;
IF ob=NIL THEN {
ob ← AdjGridWidthComposerObj[design, grid, n].obj;
[] ← CDDirectory.Include[design, ob, name]}};
AdjGridWidthComposerObj: PROC [design: CD.Design, grid, n: INT]
RETURNS [obj: CD.Object] = {
Add: PROC[name: ROPE ← NIL, size, pos: CD.Position] = {
list ← CONS[CDInstances.NewInst[CDRects.CreateRect[size, CD.commentLayer], [pos]], list];
IF name#NIL THEN {
names: LIST OF ROPE ← LIST[name];
CDProperties.PutInstanceProp[list.first, PipalSisyph.expressionsProp, names]}};
list: CD.InstanceList ← NIL;
w:  INT ← CDLayers.LayerWidth[design, CD.commentLayer];
l:  INT ← MAX[w, grid/4];
wireNm: IO.ROPE ← "w";
wire:  Core.Wire ← IndexedWire[wireNm, n];
Add[size:[2*l, grid*2*n+w], pos:[l, 0]];
CDProperties.PutInstanceProp[list.first, PipalSisyph.mode.extractProcProp, $ExtractNull];
Add[name: wireNm, size:[l, w], pos:[0, grid]];
FOR ii: INT IN [0..n) DO
name: IO.ROPE ← CoreOps.GetShortWireName[wire[ii]];
Add[name: name, size:[l, w], pos:[3*l, (2*ii+1)*grid]] ENDLOOP;
obj ← PW.CreateCell[instances: list];
CDProperties.PutObjectProp
[obj, $CodeFor, IO.PutFR["WireIcons.IndexedWire[\"%g\",%g]", IO.rope[wireNm], IO.int[n]]];
CDProperties.PutObjectProp[obj, PipalSisyph.mode.extractProcProp, $SisyphExtractUnNamedWireIcon];
CDCells.SetSimplificationTreshhold[obj, 20]};
IndexedWire: PUBLIC PROC[name: ROPE, n: NAT] RETURNS [wire: Wire] ~ {
wire ← CoreOps.CreateWires[n, name];
FOR ii: INT IN [0..n) DO
wire[ii] ← CoreOps.CreateWires[0, IO.PutFR["%g%g", IO.rope[name], IO.int[ii]]] ENDLOOP};
Explicity names the kids since the extractor gets upset if you try using their full wire name.
Grid: PROC[design: CD.Design] RETURNS[grid: NAT ← 0] = {
viewers: CDViewer.ViewerList ← CDViewer.ViewersOf[design];
IF viewers#NIL THEN
WITH ViewerOps.GetViewer[viewers.first, $Grid] SELECT FROM
rgrid: REF CD.Number => grid ← rgrid^; ENDCASE;
IF grid=0 THEN grid ← design.technology.lambda*2};
Bus icon
MakeSlash: PROC [design: CD.Design] RETURNS [obj: CD.Object] = {
l: INT = design.technology.lambda;
il: CD.InstanceList ← NIL;
FOR i: INT IN [0 .. 2*l+l/4) DO il ← AddRect[[l/4, l/4], [i, 2*i], il] ENDLOOP;
obj ← PW.CreateCell[il];
CDCells.SetSimplificationTreshhold[obj, 10.0];
};
MakeBus: PUBLIC PROC [design: CD.Design, size: NAT, slash: CD.Object ← NIL] RETURNS [wire: Wire, obj: CD.Object] = {
l: INT = design.technology.lambda;
il: CD.InstanceList ← NIL;
wire ← CoreOps.CreateWires[size: size];
The slash (if not present, the resulting obj should NOT be used)
IF slash#NIL THEN il ← CONS [CDInstances.NewInst[slash, [[l-l/4, 0]]], il];
The structured wire
il ← PutPin[wire, [9*l/2, l/2], [0, 2*l], il];
The composed wires
FOR i: NAT IN [0 .. size) DO wire[i] ← CoreOps.CreateWire[] ENDLOOP;
The text
il ← AddText[IO.PutR1[IO.int[size]], [6*l/4, -7*l/4], il];
obj ← PW.CreateCell[instances: il, ir: [0, 0, 9*l/2, 9*l/2], props: LIST [[$BusSize, NEW [INT ← size]], [PipalSisyph.mode.extractProcProp, $WireIconsExtractBus]]];
CDCells.SetSimplificationTreshhold[obj, 10.0];
};
Bus: PW.GeneratorProc = {
slash: CD.Object;
int: INT ← TerminalIO.RequestInt["Size of the bus? "];
IF int<1 THEN {TerminalIO.PutF["*** Incorrect parameter.\n"]; RETURN};
slash ← CDDirectory.Fetch[design, "::SlashForBusIcon"].object;
IF slash=NIL THEN {
slash ← MakeSlash[design];
[] ← CDDirectory.Include[design, slash, "::SlashForBusIcon"];
};
ob ← MakeBus[design, NAT [int], slash].obj;
};
ExtractBus: PipalSinix.ExtractProc = {
cx: PipalSisyph.Context = NARROW [userData];
refNat: REF INT ← NARROW [CDProperties.GetObjectProp[obj, $BusSize]];
size: NAT ← NAT [refNat^];
result ← MakeBus[PipalSisyph.GetDesign[cx], size].wire;
};
Extractor icon
MakeExtractor: PUBLIC PROC [design: CD.Design, index, size: NAT] RETURNS [wire: Wire, obj: CD.Object] = {
l: INT = design.technology.lambda;
il: CD.InstanceList ← NIL;
wire ← CoreOps.CreateWires[size: size];
The composed wires
FOR i: NAT IN [0 .. size) DO wire[i] ← CoreOps.CreateWire[] ENDLOOP;
The structured wire
il ← PutPin[wire, [9*l/2, l/2], [0, 2*l], il];
The extracted wire
il ← PutPin[wire[index], [l/2, 3*l/2], [2*l, 0], il];
The square
il ← AddRect[[3*l/2, l/8], [l, 3*l/2], il];
il ← AddRect[[3*l/2, l/8], [l, 3*l], il];
il ← AddRect[[l/8, 3*l/2], [l, 3*l/2], il];
il ← AddRect[[l/8, 3*l/2], [19*l/8, 13*l/8], il];
The texts
il ← AddText[IO.PutR1[IO.int[index]], [9*l/4, -7*l/4], il];
il ← AddText[IO.PutR1[IO.int[size]], [9*l/4, 11*l/4], il];
obj ← PW.CreateCell[instances: il, ir: [0, 0, 9*l/2, 7*l/2], props: LIST [[$ExtractorIndex, NEW [INT ← index]], [$ExtractorSize, NEW [INT ← size]], [ PipalSisyph.mode.extractProcProp, $WireIconsExtractExtractor]]];
CDCells.SetSimplificationTreshhold[obj, 10.0];
};
Extractor: PW.GeneratorProc = {
int: INT ← TerminalIO.RequestInt["Index of the extracted wire? "];
int2: INT ← TerminalIO.RequestInt["Size of the structured wire? "];
IF int<0 OR int2<1 OR int>=int2 THEN {TerminalIO.PutF["*** Incorrect parameters.\n"]; RETURN};
ob ← MakeExtractor[design, NAT [int], NAT [int2]].obj;
};
ExtractExtractor: PipalSinix.ExtractProc = {
cx: PipalSisyph.Context = NARROW [userData];
refNat: REF INT ← NARROW [CDProperties.GetObjectProp[obj, $ExtractorIndex]];
refNat2: REF INT ← NARROW [CDProperties.GetObjectProp[obj, $ExtractorSize]];
index: NAT ← NAT [refNat^];
size: NAT ← NAT [refNat2^];
result ← MakeExtractor[PipalSisyph.GetDesign[cx], index, size].wire;
};
Range Extractor icon
MakeRangeExtractor: PUBLIC PROC [design: CD.Design, index, subSize, size: NAT] RETURNS [wires: Wires, obj: CD.Object] = {
l: INT = design.technology.lambda;
il: CD.InstanceList ← NIL;
We create an extra level of hierarchy in the wires to extract things properly
structWire: Wire ← CoreOps.CreateWires[size: size];
subWire: Wire ← CoreOps.CreateWires[size: subSize];
wires ← LIST [subWire, structWire];
The composed wires
FOR i: NAT IN [0 .. size) DO structWire[i] ← CoreOps.CreateWire[] ENDLOOP;
FOR i: NAT IN [0 .. subSize) DO subWire[i] ← structWire[i+index] ENDLOOP;
The structured wire
il ← PutPin[structWire, [19*l/2, l/2], [0, 2*l], il];
The extracted wire
il ← AddRect[[l/2, 3*l/2], [5*l/2, 0], il];
il ← PutPin[subWire, [l/2, 3*l/2], [3*l, 0], il];
The rectangle
il ← AddRect[[5*l/2, l/8], [l, 3*l/2], il];
il ← AddRect[[5*l/2, l/8], [l, 3*l], il];
il ← AddRect[[l/8, 3*l/2], [l, 3*l/2], il];
il ← AddRect[[l/8, 3*l/2], [27*l/8, 13*l/8], il];
The texts
il ← AddText[IO.PutFR["%g/%g", IO.int[index], IO.int[subSize]], [13*l/4, -7*l/4], il];
il ← AddText[IO.PutR1[IO.int[size]], [13*l/4, 11*l/4], il];
obj ← PW.CreateCell[instances: il, ir: [0, 0, 19*l/2, 7*l/2], props: LIST [[$ExtractorIndex, NEW [INT ← index]], [$ExtractorSubSize, NEW [INT ← subSize]], [$ExtractorSize, NEW [INT ← size]], [PipalSisyph.mode.extractProcProp, $WireIconsExtractRangeExtractor]]];
CDCells.SetSimplificationTreshhold[obj, 10.0];
};
RangeExtractor: PW.GeneratorProc = {
int: INT ← TerminalIO.RequestInt["Index of the extracted wire? "];
int2: INT ← TerminalIO.RequestInt["Size of the extracted wire? "];
int3: INT ← TerminalIO.RequestInt["Size of the structured wire? "];
IF int<0 OR int2<1 OR int3<1 OR int>=int3 OR int+int2>int3 THEN {TerminalIO.PutF["*** Incorrect parameters.\n"]; RETURN};
ob ← MakeRangeExtractor[design, NAT [int], NAT [int2], NAT [int3]].obj;
};
ExtractRangeExtractor: PipalSinix.ExtractProc = {
cx: PipalSisyph.Context = NARROW [userData];
refNat: REF INT ← NARROW [CDProperties.GetObjectProp[obj, $ExtractorIndex]];
refNat2: REF INT ← NARROW [CDProperties.GetObjectProp[obj, $ExtractorSubSize]];
refNat3: REF INT ← NARROW [CDProperties.GetObjectProp[obj, $ExtractorSize]];
index: NAT ← NAT [refNat^];
subSize: NAT ← NAT [refNat2^];
size: NAT ← NAT [refNat3^];
result ← MakeRangeExtractor[PipalSisyph.GetDesign[cx], index, subSize, size].wires;
};
Parametrized Bus icon
ParametrizedBus: PW.GeneratorProc = {
l: INT = design.technology.lambda;
il: CD.InstanceList ← NIL;
slash: CD.Object ← CDDirectory.Fetch[design, "::SlashForBusIcon"].object;
sizeRope: ROPE ← TerminalIO.RequestRope["Size of the parametrized bus? "];
IF slash=NIL THEN {
slash ← MakeSlash[design];
[] ← CDDirectory.Include[design, slash, "::SlashForBusIcon"];
};
il ← CONS [CDInstances.NewInst[slash, [[l-l/4, 0]]], il];
il ← AddRect[[9*l/2, l/2], [0, 2*l], il];
The text
il ← AddText[sizeRope, [6*l/4, -6*l/4], il];
ob ← PW.CreateCell[instances: il, ir: [0, 0, 9*l/2, 9*l/2], props: LIST [[$BusSize, sizeRope], [PipalSisyph.mode.extractProcProp, $WireIconsExtractParametrizedBus]]];
CDCells.SetSimplificationTreshhold[ob, 10.0];
};
ExtractParametrizedBus: PipalSinix.ExtractProc = {
cx: PipalSisyph.Context ← PipalSisyph.EvaluateParameters[userData, obj, properties];
design: CD.Design ← PipalSisyph.GetDesign[cx];
l: INT = design.technology.lambda;
sizeRope: ROPE ← NARROW [CDProperties.GetObjectProp[obj, $BusSize]];
size: NAT ← EvalNat[cx, sizeRope];
wire: Wire;
IF size<1 THEN ERROR;
wire ← CoreOps.CreateWires[size: size];
The structured wire
[] ← PutPin[wire, [9*l/2, l/2], [0, 2*l], NIL]; -- new object thrown away!
The composed wires
FOR i: NAT IN [0 .. size) DO wire[i] ← CoreOps.CreateWire[] ENDLOOP;
result ← wire;
};
Parametrized Extractor icon
ParametrizedExtractor: PW.GeneratorProc = {
l: INT = design.technology.lambda;
il: CD.InstanceList ← NIL;
indexRope: ROPE ← TerminalIO.RequestRope["Parametrized index of the extracted wire? "];
sizeRope: ROPE ← TerminalIO.RequestRope["Size of the parametrized bus? "];
The structured wire
il ← AddRect[[9*l/2, l/2], [0, 2*l], il];
The extracted wire
il ← AddRect[[l/2, 3*l/2], [2*l, 0], il];
The square
il ← AddRect[[3*l/2, l/8], [l, 3*l/2], il];
il ← AddRect[[3*l/2, l/8], [l, 3*l], il];
il ← AddRect[[l/8, 3*l/2], [l, 3*l/2], il];
il ← AddRect[[l/8, 3*l/2], [19*l/8, 13*l/8], il];
The texts
il ← AddText[indexRope, [9*l/4, -6*l/4], il];
il ← AddText[sizeRope, [9*l/4, 11*l/4], il];
ob ← PW.CreateCell[instances: il, ir: [0, 0, 9*l/2, 7*l/2], props: LIST [[$ExtractorIndex, indexRope], [$ExtractorSize, sizeRope], [PipalSisyph.mode.extractProcProp, $WireIconsExtractParametrizedExtractor]]];
CDCells.SetSimplificationTreshhold[ob, 10.0];
};
ExtractParametrizedExtractor: PipalSinix.ExtractProc = {
cx: PipalSisyph.Context ← PipalSisyph.EvaluateParameters[userData, obj, properties];
design: CD.Design ← PipalSisyph.GetDesign[cx];
l: INT = design.technology.lambda;
indexRope: ROPE ← NARROW [CDProperties.GetObjectProp[obj, $ExtractorIndex]];
sizeRope: ROPE ← NARROW [CDProperties.GetObjectProp[obj, $ExtractorSize]];
index: NAT ← EvalNat[cx, indexRope];
size: NAT ← EvalNat[cx, sizeRope];
wire: Wire;
IF index<0 OR size<1 OR index>=size THEN ERROR;
wire ← CoreOps.CreateWires[size: size];
FOR i: NAT IN [0 .. size) DO wire[i] ← CoreOps.CreateWire[] ENDLOOP;
The structured wire
[] ← PutPin[wire, [9*l/2, l/2], [0, 2*l], NIL];
The extracted wire
[] ← PutPin[wire[index], [l/2, 3*l/2], [2*l, 0], NIL];
result ← wire;
};
Parametrized Range Extractor icon
ParametrizedRangeExtractor: PW.GeneratorProc = {
l: INT = design.technology.lambda;
il: CD.InstanceList ← NIL;
indexRope: ROPE ← TerminalIO.RequestRope["Parametrized index of the extracted wire? "];
subSizeRope: ROPE ← TerminalIO.RequestRope["Size of the parametrized sub wire? "];
sizeRope: ROPE ← TerminalIO.RequestRope["Size of the parametrized bus? "];
The structured wire
il ← AddRect[[19*l/2, l/2], [0, 2*l], il];
The extracted wire
il ← AddRect[[l/2, 3*l/2], [5*l/2, 0], il];
il ← AddRect[[l/2, 3*l/2], [3*l, 0], il];
The rectangle
il ← AddRect[[5*l/2, l/8], [l, 3*l/2], il];
il ← AddRect[[5*l/2, l/8], [l, 3*l], il];
il ← AddRect[[l/8, 3*l/2], [l, 3*l/2], il];
il ← AddRect[[l/8, 3*l/2], [27*l/8, 13*l/8], il];
The texts
il ← AddText[IO.PutFR["%g/%g", IO.rope[indexRope], IO.rope[subSizeRope]], [13*l/4, -7*l/4], il];
il ← AddText[sizeRope, [13*l/4, 11*l/4], il];
ob ← PW.CreateCell[instances: il, ir: [0, 0, 19*l/2, 7*l/2], props: LIST [[$ExtractorIndex, indexRope], [$ExtractorSubSize, subSizeRope], [$ExtractorSize, sizeRope], [PipalSisyph.mode.extractProcProp, $WireIconsExtractParametrizedRangeExtractor]]];
CDCells.SetSimplificationTreshhold[ob, 10.0];
};
ExtractParametrizedRangeExtractor: PipalSinix.ExtractProc = {
cx: PipalSisyph.Context ← PipalSisyph.EvaluateParameters[userData, obj, properties];
design: CD.Design ← PipalSisyph.GetDesign[cx];
l: INT = design.technology.lambda;
indexRope: ROPE ← NARROW [CDProperties.GetObjectProp[obj, $ExtractorIndex]];
subSizeRope: ROPE ← NARROW [CDProperties.GetObjectProp[obj, $ExtractorSubSize]];
sizeRope: ROPE ← NARROW [CDProperties.GetObjectProp[obj, $ExtractorSize]];
index: NAT ← EvalNat[cx, indexRope];
subSize: NAT ← EvalNat[cx, subSizeRope];
size: NAT ← EvalNat[cx, sizeRope];
wire, subWire: Wire;
wires: Wires;
IF index<0 OR subSize<1 OR size<1 OR index>=size OR index+subSize>size THEN RETURN;
wire ← CoreOps.CreateWires[size: size];
subWire ← CoreOps.CreateWires[size: subSize];
FOR i: NAT IN [0 .. size) DO wire[i] ← CoreOps.CreateWire[] ENDLOOP;
FOR i: NAT IN [0 .. subSize) DO subWire[i] ← wire[i+index] ENDLOOP;
The structured wire
[] ← PutPin[wire, [19*l/2, l/2], [0, 2*l], NIL];
The extracted wire
[] ← PutPin[subWire, [l/2, 3*l/2], [3*l, 0], NIL];
wires ← LIST [subWire, wire];
result ← wires;
};
Sequencing Slash
SequencingSlash: PW.GeneratorProc = {
l: INT = design.technology.lambda;
il: CD.InstanceList ← NIL;
il ← AddRect[[5*l/2, l/2], [0, 2*l], il];
FOR i: INT IN [0 .. 2*l+l/4) DO il ← AddRect[[l/4, l/4], [i, 2*i], il] ENDLOOP;
ob ← PW.CreateCell[instances: il, name: "/", props: LIST [[PipalSisyph.mode.extractProcProp, $WireIconsExtractSequencingSlash]]];
CDCells.SetSimplificationTreshhold[ob, 10.0];
};
ExtractSequencingSlash: PipalSinix.ExtractProc = {
cx: PipalSisyph.Context ← PipalSisyph.EvaluateParameters[userData, obj, properties];
design: CD.Design ← PipalSisyph.GetDesign[cx];
l: INT = design.technology.lambda;
wire: Wire ← CoreOps.CreateWire[props: CoreProperties.Props[[$Sequence, $Sequence]]];
The structured wire
[] ← PutPin[wire, [5*l/2, l/2], [0, 2*l], NIL];
result ← wire;
};
Compatibility Code
Convert: PROC [design: CD.Design] = {
EachObj: CDDirectory.EachEntryAction = {
SELECT TRUE FROM
Rope.Match[":Composer[*].icon", name] => {
refNat: REF INT ← NARROW [CDProperties.GetObjectProp[ob, $ComposerSize]];
size: NAT ← NAT [refNat^];
new: CD.Object = MakeComposer[design, size].obj;
off: CD.Position = CDBasics.SubPoints[CDBasics.BaseOfRect[CD.InterestRect[ob]], CDBasics.BaseOfRect[CD.InterestRect[new]]];
CDDirectory.ReplaceObject[design, ob, new, off];
};
Rope.Match[":Bus[*].icon", name] => {
refNat: REF INT ← NARROW [CDProperties.GetObjectProp[ob, $BusSize]];
size: NAT ← NAT [refNat^];
new: CD.Object = MakeBus[design, size].obj;
off: CD.Position = CDBasics.SubPoints[CDBasics.BaseOfRect[CD.InterestRect[ob]], CDBasics.BaseOfRect[CD.InterestRect[new]]];
CDDirectory.ReplaceObject[design, ob, new, off];
};
Rope.Match[":Extractor[*, *].icon", name] => {
refNat: REF INT ← NARROW [CDProperties.GetObjectProp[ob, $ExtractorIndex]];
refNat2: REF INT ← NARROW [CDProperties.GetObjectProp[ob, $ExtractorSize]];
index: NAT ← NAT [refNat^];
size: NAT ← NAT [refNat2^];
new: CD.Object = MakeExtractor[design, index, size].obj;
off: CD.Position = CDBasics.SubPoints[CDBasics.BaseOfRect[CD.InterestRect[ob]], CDBasics.BaseOfRect[CD.InterestRect[new]]];
CDDirectory.ReplaceObject[design, ob, new, off];
};
Rope.Match[":RangeExtractor[*/*, *].icon", name] => {
refNat: REF INT ← NARROW [CDProperties.GetObjectProp[ob, $ExtractorIndex]];
refNat2: REF INT ← NARROW [CDProperties.GetObjectProp[ob, $ExtractorSubSize]];
refNat3: REF INT ← NARROW [CDProperties.GetObjectProp[ob, $ExtractorSize]];
index: NAT ← NAT [refNat^];
subSize: NAT ← NAT [refNat2^];
size: NAT ← NAT [refNat3^];
new: CD.Object = MakeRangeExtractor[design, index, subSize, size].obj;
off: CD.Position = CDBasics.SubPoints[CDBasics.BaseOfRect[CD.InterestRect[ob]], CDBasics.BaseOfRect[CD.InterestRect[new]]];
CDDirectory.ReplaceObject[design, ob, new, off];
};
ENDCASE => {};
};
[] ← CDDirectory.Enumerate[design, EachObj];
};
The purpose of this function is to correct the decorations for WireIcons that were created before CD24 and which do not have the interestRect based on [0, 0]. The idea is that we just translate everything!
Convert: CDEvents.EventProc = {
replaceList: CDDirectory.ReplaceList ← NIL;
EachObj: CDDirectory.EachEntryAction = {
instances: CD.InstanceList ← NIL;
base: CD.Position = CD.InterestBase[ob];
size: CD.Position = CD.InterestSize[ob];
new: CD.Object;
EachInst: CDCells.InstEnumerator = {
instances ← CONS [CDInstances.DeComposed[inst, [base]], instances];
};
IF base=[0, 0] THEN RETURN;
IF CDProperties.GetObjectProp[ob, PipalSisyph.mode.extractProcProp]=NIL THEN RETURN;
SELECT CDProperties.GetObjectProp[ob, PipalSisyph.mode.extractProcProp] FROM
$WireIconsExtractComposer, $WireIconsExtractBus, $WireIconsExtractExtractor, $WireIconsExtractRangeExtractor, $WireIconsExtractParametrizedBus, $WireIconsExtractParametrizedExtractor, $WireIconsExtractParametrizedRangeExtractor => NULL;
ENDCASE => RETURN;
IF NOT CDCells.IsCell[ob] THEN RETURN;
[] ← CDCells.EnumerateInstances[ob, EachInst];
new ← PW.CreateCell[instances: instances, ir: [0, 0, size.x, size.y], props: ob.properties];
CDCells.SetSimplificationTreshhold[new, 10.0];
replaceList ← CONS [NEW [CDDirectory.ReplaceRec ← [old: ob, new: new, trans: [base]]], replaceList];
};
IF design=NIL THEN RETURN; -- design is sometimes NIL!!
IF CDProperties.GetProp[design, $WireIconsConvertedFrom23] = $TRUE THEN RETURN;
CDProperties.PutProp[design, $WireIconsConvertedFrom23, $TRUE];
[] ← CDDirectory.Enumerate[design, EachObj];
IF replaceList=NIL THEN RETURN;
TerminalIO.PutF["***WireIconsImpl: repositions for conversion to CD24.\n"];
FOR list: CDDirectory.ReplaceList ← replaceList, list.rest WHILE list#NIL DO
CDDirectory.ReplaceObject[design, list.first.old, list.first.new, list.first.trans];
TerminalIO.PutF["\t\t%g -> %g;", IO.rope[CDDirectory.Name[list.first.old, design]], IO.rope[CDDirectory.Name[list.first.new, design]]];
ENDLOOP;
TerminalIO.PutF["\n***WireIconsImpl made replacements. Save the design\n"];
};
Initialization
CDEvents.RegisterEventProc[$AfterInput, Convert];
PW.RegisterGenerator[AdjGridWidthComposer, "Composer - adjustable grid and width"];
PW.RegisterGenerator[Composer, "Composer"];
PipalSinix.RegisterExtractProc[$WireIconsExtractComposer, ExtractComposer];
PW.RegisterGenerator[Bus, "Bus"];
PipalSinix.RegisterExtractProc[$WireIconsExtractBus, ExtractBus];
PW.RegisterGenerator[Extractor, "Extractor"];
PipalSinix.RegisterExtractProc[$WireIconsExtractExtractor, ExtractExtractor];
PW.RegisterGenerator[RangeExtractor, "Range Extractor"];
PipalSinix.RegisterExtractProc[$WireIconsExtractRangeExtractor, ExtractRangeExtractor];
PW.RegisterGenerator[ParametrizedBus, "Parametrized Bus"];
PipalSinix.RegisterExtractProc[$WireIconsExtractParametrizedBus, ExtractParametrizedBus];
PW.RegisterGenerator[ParametrizedExtractor, "Parametrized Extractor"];
PipalSinix.RegisterExtractProc[$WireIconsExtractParametrizedExtractor, ExtractParametrizedExtractor];
PW.RegisterGenerator[ParametrizedRangeExtractor, "Parametrized Range Extractor"];
PipalSinix.RegisterExtractProc[$WireIconsExtractParametrizedRangeExtractor, ExtractParametrizedRangeExtractor];
PW.RegisterGenerator[SequencingSlash, "Sequencing Slash"];
PipalSinix.RegisterExtractProc[$WireIconsExtractSequencingSlash, ExtractSequencingSlash];
END.