DIRECTORY CD, Core, CoreCreate; CommonPadFrame: CEDAR DEFINITIONS = BEGIN ROPE: TYPE = Core.ROPE; Wire: TYPE = Core.Wire; WireSeq: TYPE = Core.WireSeq; CellType: TYPE = Core.CellType; CellInstance: TYPE = CoreCreate.CellInstance; PA: TYPE = CoreCreate.PA; WR: TYPE = CoreCreate.WR; Pads: TYPE = LIST OF Pad; Pad: TYPE = RECORD [public: WR, type: ATOM, pos: NAT, pas: LIST OF PA]; AddPad: PROC [pads: Pads, public: WR, type: ATOM, pos: NAT, pa1, pa2, pa3, pa4: PA _ []] RETURNS [Pads]; AddPadList: PROC [pads: Pads, public: WR, type: ATOM, pos: NAT, pas: LIST OF PA _ NIL] RETURNS [Pads]; AddPads: PROC [pads: Pads, public: Wire, type: ATOM, firstPos: NAT, reverse: BOOL _ FALSE, pa1, pa2, pa3, pa4: PA _ []] RETURNS [Pads]; CreatePadFrame: PROC [public: WireSeq, onlyInternal: WireSeq, innerInstance: CellInstance, pads: Pads, params: PadFrameParametersRec, name: ROPE _ NIL, props: Core.Properties _ NIL] RETURNS [fullChip: CellType]; PadFrameParameters: TYPE = REF PadFrameParametersRec; PadFrameParametersRec: TYPE = RECORD [ horizLayer: ROPE, -- "poly", "metal" or "metal2", runs length of area vertLayer: ROPE, -- branch goes across the area nbPadsX, nbPadsY: NAT, -- one pad is the corner in every side library: ROPE _ NIL, -- name of the library. Default means "Pads.dale" centerDisplacement: CD.Position _ [0, 0], -- quantity to be added to Cabbage.Center outerChanWidth: INT _ 28, -- width of channel at periphery in lambdas powerCellWidth : INT _ 152, -- width of power at periphery in lambdas padsData: REF PadsData _ NIL, -- used by implementation design: Design _ NIL -- used by implementation ]; padFrameParamsProp: PRIVATE ATOM; -- on cellType; type PadFrameParameters Design: PRIVATE TYPE = CD.Design; PadData: PRIVATE TYPE = RECORD [ instance: CellInstance _ NIL, trans: CD.Transformation _ [] -- [0, 0] is the lower-left of the cavity ]; PadsData: TYPE = RECORD [SEQUENCE nbOfPads: NAT OF PadData]; END. ΘCommonPadFrame.mesa Copyright c 1986 by Xerox Corporation. All rights reversed. Louis Monier April 23, 1986 11:32:05 am PST Bertrand Serlet April 29, 1987 5:20:24 pm PDT Last Edited by: Louis Monier March 27, 1987 11:50:23 am PST Last Edited by: Don Curry May 13, 1987 10:41:42 am PDT Theory Core level: the top level cellType describing a chip is a record cellType containing n+1 instances: n pads and the inner. Every pad instance (excluding the inner) carries the property packagePinProp which is used to derive its geometrical position in the pad frame. The only instance without this property is the inner. Every non trivial pad cellType must have a public wire named "Pad" (for Bonnie). In the current implementation (used primarily for the Dragon EU) pads are pulled out of Pads.dale and numbered 1 through 2*(nbPadsX+nbPadsY). The first pad is the top-left corner, and then walk counter-clockwise through the pad frame. Corners are specified when you do CreatePadFrame, so don't try to specify them again. Corners are counted, i.e. you should never specify a pad number 1, or number nbPadsY, .... Unspecified position are filled with "filler" pads. Common types Generation of the Core type is the name of a pad of the library. type is the name of a pad of the library. type is the name of a pad of the library. size of pad induces number of pad instanciated. Adds fillers and corners to pads, and makes several checks. Generation of the Layout The layout proc creates the four sides, inserts automatically extra power pads, places the inner and calls Cabbage to do the routing. The resulting cell is flattened so that the extra power pads and the routing are expanded. This style produces fixed-size PadFrames. ΚF˜– "Cedar" stylešœ™Jšœ Οmœ1™Kšœ žœžœ‘2˜HKšœžœ‘)˜SKšœžœ‘"Πbc ‘˜FKšœžœ‘ ’ ˜EKšœ žœ žœ‘˜7Kšœžœ‘˜0Kšœ˜K˜Kšœžœžœ‘'˜JKšœžœžœžœ˜!šœ ž œžœ˜ Kšœžœ˜Kšœžœ‘)˜HK˜—Kš œ žœžœžœ žœžœ ˜