MintDoc.tioga
Copyright Ó 1986, 1987 by Xerox Corporation. All rights reserved.
Written by: Christian LeCocq August 5, 1986 11:20:25 am PDT
MINT: MINIMUM TIME SIMULATOR
MINT: MINIMUM TIME SIMULATOR
MINT: MINIMUM TIME SIMULATOR
DATOOLS — FOR INTERNAL XEROX USE ONLY
DATOOLS — FOR INTERNAL XEROX USE ONLY
DATOOLS — FOR INTERNAL XEROX USE ONLY
Mint: MINimum Time simulator
Christian Le Cocq
User Manual
© Copyright 1986, 1987 Xerox Corporation. All rights reserved.
Abstract: Mint is a program that simulates a Core data structure extracted from a layout. It offers also a static electrical checker, and a timing analyzer.
Created by: Christian Le Cocq
Maintained by: Le Cocq <LeCocq.pa>
Keywords: Circuit Simulation, Graph Display
XEROX Xerox Corporation
Palo Alto Research Center
3333 Coyote Hill Road
Palo Alto, California 94304
For Internal Xerox Use Only
Introduction
The Purpose of Mint is to provide a fast verification of logic and timing features of a piece of layout or schematics. Mint is faster and less accurate than Thyme and can handle many more fets in a reasonable amount of time. Its time evaluations are more reliable than Crystal ones, as it propagates the clocks in a way more suitable to our needs.
Programming Interface
The simulation interface resides in Mint.mesa.
User Interface
The user interface for Mint consists of six commands in the <space>-P menu of ChipNDale. These commands take a selected ChipNDale cell as argument, extract the cell using Sinix or Sisyph, translates the resulting cellType into a Mint flat world, writes on the Terminal viewer the statistics of the creation of the Mint sets, then process the requested stuff.
Running Mint
1. BringDATools
2. Type Install Mint to the Commander.
3. If you work with Standard Cells, load them by the command LoadStdCellsCmosB.
The simulator
Mint is interfaced with the CoreThyme icons, and then a simulation is prepared for Mint the same way as for Thyme. It shows the results on a PlotGraph Viewer.
Mint is not very good with analogic designs, as it assumes that a fet is simply either open or close. Consequently, smart and tricky fet assembly will probaly result in oscillations, traducing the fact that neither the fets fully open nor fully closed reaches a equilibrium.
The checker
Mint will give you a diagnostic if:
a node has no electrical path to Vdd or no path to Gnd,
a node which is not public has no driving device on it,
a node is not connected to any fet.
The critical path finder
The path finder - CD interface assumes that you have a clock wire in your tested cell which name is "public.CK", if not you should specify:
CDMint.clkName ← "public.MyFunnyClockName"
Mint gives you (after a while) three informations:
it highlights the alleged longest path,
it shows a histogram of the delays through the paths of the cell, so that you can evaluate if you are right, a few steps from the victory, or a long way to tahiti (user feedback needed),
it prints a time, which is not guaranteed to be anything else than an indication, which hopefully will turn into something meaningfull after some real IC have been measured.
The property $MintIgnoreMe , if set to $TRUE stops the analysis of the critical path at this point. It can be put on a wire, or on a cell (type or instance). If on a cell, the property applies to the internals of this cell, and all the public and internals of included cells, that is all the strictly included electrical nodes.
The wires capacitances are computed from the geometry of the layout, if any. If the cell beeing analyzed is a schematics cell, then the wires of the cells from top level to those with PWCore.GetLayoutAtom[cell] =$Get or $GetAndFlatten excluded are supposed to have a parisitic capacitance of CDMint.defaultCapa (default 0.5 pF) and the wires of the cells from there to the leaves are supposed to have no parasitic capacitance.