DIRECTORY AbSets, BiRels, IntStuff, LichenArrayStuff, LichenDataOps, LichenDataStructure, LichenNavigation, Process, Rope, SetBasics, StructuredStreams, UnparserBuffer, ViewerIO; LichenData4Impl: CEDAR PROGRAM IMPORTS AbSets, BiRels, IntStuff, LichenArrayStuff, LichenDataOps, LichenDataStructure, LichenNavigation, Process, SetBasics = BEGIN OPEN LichenArrayStuff, LichenDataOps, LichenDataStructure, Sets:AbSets, Ints:IntStuff, SS:StructuredStreams, UB:UnparserBuffer; Set: TYPE ~ LichenDataStructure.Set; Function: TYPE ~ LichenDataStructure.Function; OneToOne: TYPE ~ LichenDataStructure.OneToOne; Seq: TYPE ~ LichenDataStructure.Seq; Thing: TYPE ~ REF ANY --actually UNION [Port, Wire]--; Wirism: TYPE ~ REF ANY --actually UNION [Vertex, DumbWire]--; refPerms: Sets.Space ~ BiRels.CreateBiRelSpace[ALL[SetBasics.ints]]; break1: SteppyName _ NIL; break2: SteppyName _ NIL; Break: SIGNAL ~ CODE; ReOrderDesign: PROC [d: Design] ~ { desiredPerm: BiRel--Wirism X REF Permutation-- ~ BiRels.CreateHashReln[[SetBasics.refs, refPerms]]; portDesires: Function--Port _ REF Permutation-- ~ BiRels.CreateHashFn[invable: FALSE]; delayedVerts: Set--of Vertex-- ~ Sets.CreateHashSet[]; delayedPorts: Set--of Port-- ~ Sets.CreateHashSet[]; arrayWireArray: Function--DumbWire _ Array-- ~ BiRels.CreateHashFn[invable: FALSE]; StartCellType: PROC [val: REF ANY] ~ { ct: CellType ~ NARROW[val]; WorkOnPort: PROC [port: Port] RETURNS [doKids, moreSibs: BOOL _ TRUE] ~ { IF port.FirstChildPort[]=NIL THEN RETURN; IF break1#NIL AND port.PortNames.HasMemA[break1] THEN Break; {desire: Permutation ~ DesiredPerm[port, LichenNavigation.portToChildren, LichenNavigation.bestPortShortName]; refDesire: REF ANY ~ desire.Refify; DelayInstance: PROC [ci: CellInstance] ~ { v: Vertex ~ FindCellConnection[ci, port]; [] _ delayedVerts.AddA[v]; [] _ desiredPerm.AddAA[v, refDesire]; RETURN}; DelayArray: PROC [act: CellType] ~ { a: Array ~ act.asArray; DelayArrayWire: PROC [dw: DumbWire] ~ { [] _ arrayWireArray.AddAA[dw, a]; [] _ desiredPerm.AddAA[dw, refDesire]; RETURN}; EnumerateDumbWiresForPort[a, port, DelayArrayWire]; RETURN}; ct.EnumerateInstances[DelayInstance, TRUE]; ct.EnumerateArrays[DelayArray]; IF NOT delayedPorts.AddA[port] THEN ERROR; portDesires.AddNewAA[port, refDesire]; RETURN}}; WorkOnWire: PROC [wire: Wire] RETURNS [doKids, moreSibs: BOOL _ TRUE] ~ { IF wire.FirstChildWire[]=NIL THEN RETURN; IF break1#NIL AND wire.VertexNames.HasMemA[break1] THEN Break; {desire: Permutation ~ DesiredPerm[wire, LichenNavigation.wireToChildren, LichenNavigation.bestVertexShortName]; refDesire: REF ANY ~ desire.Refify; [] _ delayedVerts.AddA[wire]; [] _ desiredPerm.AddAA[wire, refDesire]; RETURN}}; Process.CheckForAbort[]; [] _ EnumeratePort[ct.port, WorkOnPort]; IF ct.asUnorganized#NIL THEN [] _ ct.asUnorganized.internalWire.EnumerateWire[WorkOnWire]; RETURN}; DoDelayedPort: PROC [val: REF ANY] ~ { port: Port ~ NARROW[val]; ct: CellType ~ PortCCT[port]; allSame: BOOL _ TRUE; desire: Permutation ~ BiRels.DeRef[portDesires.ApplyA[port].MA]; CheckInstance: PROC [ci: CellInstance] ~ { v: Vertex ~ FindCellConnection[ci, port]; perms: Set ~ desiredPerm.MappingA[v]; size: INT ~ perms.Size[Ints.two].EN; IF size=0 THEN ERROR; IF size>1 THEN allSame _ FALSE; RETURN}; CheckArray: PROC [act: CellType] ~ { a: Array ~ act.asArray; CheckArrayWire: PROC [dw: DumbWire] ~ { perms: Set ~ desiredPerm.MappingA[dw]; size: INT ~ perms.Size[Ints.two].EN; IF size=0 THEN ERROR; IF size>1 THEN allSame _ FALSE; RETURN}; EnumerateDumbWiresForPort[a, port, CheckArrayWire]; RETURN}; Process.CheckForAbort[]; IF break1#NIL AND port.PortNames.HasMemA[break1] THEN Break; ct.EnumerateInstances[CheckInstance, TRUE]; ct.EnumerateArrays[CheckArray]; IF allSame THEN PermutePort[port, desire, FALSE] ELSE Log["Port %g not permuted\n", LIST[port]]; RETURN}; DoDelayedVertex: PROC [val: REF ANY] ~ { v: Vertex ~ NARROW[val]; ct: CellType ~ v.containingCT; perms: Set ~ desiredPerm.MappingA[v]; size: INT ~ perms.Size[Ints.two].EN; Process.CheckForAbort[]; IF break1#NIL AND v.VertexNames.HasMemA[break1] THEN Break; IF size=0 THEN ERROR; IF size>1 THEN { Log["%g perms desired for vertex %g\n", LIST[NEW [INT _ size], v]]; RETURN}; {desire: Permutation ~ BiRels.DeRef[perms.TheElt.VA]; PermuteVertex[v, desire]; RETURN}}; d.cellTypes.EnumA[StartCellType]; delayedPorts.EnumA[DoDelayedPort]; delayedVerts.EnumA[DoDelayedVertex]; RETURN}; < IF port#find AND port#ci.type.port THEN RETURN [FALSE]; im: Intermediary => IF port#find AND port#im.port THEN RETURN [FALSE]; w: Wire => IF w.containingWire#NIL THEN { goal: Port; IF port=find THEN goal _ find ELSE IF port=NIL THEN goal _ NIL ELSE WITH port.parent SELECT FROM ct: CellType => ERROR--shouldn't happen--; parent: Port => { wi: INT ~ w.containingWire.WireIndex[w]; pi: INT ~ port.PortIndex[]; IF wi=pi THEN goal _ parent ELSE goal _ NIL}; ENDCASE => ERROR; IF NOT AllForPort[w.containingWire, goal] THEN RETURN [FALSE]; }; ENDCASE => ERROR; RETURN};>> DesiredPerm: PROC [parent: Thing, ToChildren: OneToOne--Thing f Seq of children--, ToName: Function--Thing _ SteppyName--] RETURNS [perm: Permutation] ~ { children: Seq--of child Things-- ~ BiRels.DeRef[ToChildren.ApplyA[parent].MA].CreateVectorCopy; names: Seq--of SteppyName-- ~ children.Compose[right: ToName, restricts: [TRUE, FALSE]]; perm _ BiRels.GradeUp[names, alphaSteppyNameOrder]; RETURN}; alphaSteppyNameOrder: SetBasics.Order ~ SetBasics.CreateLORASpace[NIL, LIST[nameStepSpace]].SpaceOrder[]; PermutePort: PROC [port: Port, perm: Permutation, doConnections: BOOL] ~ { oldKids: Seq ~ BiRels.DeRef[LichenNavigation.portToChildren.ApplyA[port].MA] .CreateVectorCopy; n: INT ~ oldKids.Size.EN; prev: Port _ NIL; index: INT _ 0; FixElt: PROC [pair: BiRels.Pair] ~ { newIndex: INT ~ pair[left].VI; oldIndex: INT ~ pair[right].VI; kid: Port ~ NARROW[oldKids.ApplyI[oldIndex].MA]; IF index#newIndex THEN ERROR; kid.prev _ prev; IF prev#NIL THEN prev.next _ kid ELSE port.firstChild _ kid; prev _ kid; index _ index+1; RETURN}; FixInstance: PROC [ci: CellInstance] ~ { v: Vertex ~ FindCellConnection[ci, port]; PermuteVertex[v, perm]; }; IF break2#NIL AND port.PortNames.HasMemA[break2] THEN Break; perm.Enumerate[FixElt]; IF index#n THEN ERROR; prev.next _ NIL; port.lastChild _ prev; IF doConnections THEN port.PortCCT.EnumerateInstances[FixInstance, TRUE]; RETURN}; PermuteWire: PROC [wire: Wire, perm: Permutation] ~ { oldKids: Seq ~ BiRels.DeRef[LichenNavigation.wireToChildren.ApplyA[wire].MA] .CreateVectorCopy; n: INT ~ oldKids.Size.EN; prev: Wire _ NIL; index: INT _ 0; FixElt: PROC [pair: BiRels.Pair] ~ { newIndex: INT ~ pair[left].VI; oldIndex: INT ~ pair[right].VI; kid: Wire ~ NARROW[oldKids.ApplyI[oldIndex].MA]; IF index#newIndex THEN ERROR; kid.prev _ prev; IF prev#NIL THEN prev.next _ kid ELSE wire.firstChild _ kid; prev _ kid; index _ index+1; RETURN}; IF break2#NIL AND wire.VertexNames.HasMemA[break2] THEN Break; perm.Enumerate[FixElt]; IF index#n THEN ERROR; prev.next _ NIL; wire.lastChild _ prev; RETURN}; PermuteVertex: PROC [v: Vertex, perm: Permutation] ~ { WITH v SELECT FROM w: Wire => {PermuteWire[w, perm]; RETURN}; im: Intermediary => NULL; ci: CellInstance => NULL; ENDCASE => ERROR; {old: Seq--of old Edge-- ~ BiRels.CreateVector[oneToOne: TRUE, dense: TRUE]; NoteOldEdge: PROC [p: Port, w: Vertex, e: Edge] ~ { IF e.sides[cellward].v#v THEN ERROR; old.AppendA[e]; RETURN}; v.EnumerateImmediateEdges[NoteOldEdge, [cellward: FALSE, wireward: TRUE], forward]; {n: INT ~ old.Size.EN; oldFirstWireward: Edge ~ NARROW[old.First[].it[right].VA]; lastCellward: Edge ~ oldFirstWireward.sides[cellward].prev; prev: Edge _ lastCellward; prevSide: GraphDirection _ wireward; index: INT _ 0; FixElt: PROC [pair: BiRels.Pair] ~ { newIndex: INT ~ pair[left].VI; oldIndex: INT ~ pair[right].VI; e: Edge ~ NARROW[old.ApplyI[oldIndex].MA]; IF index#newIndex THEN ERROR; e.sides[cellward].prev _ prev; IF prev#NIL THEN prev.sides[prevSide].next _ e ELSE IF v.firstEdge.sides[cellward].v#v THEN ERROR ELSE v.firstEdge _ e; prev _ e; prevSide _ cellward; index _ index+1; RETURN}; IF lastCellward#NIL AND lastCellward.sides[wireward].v#v THEN ERROR; perm.Enumerate[FixElt]; IF index#n OR n=0 THEN ERROR; prev.sides[cellward].next _ NIL; v.lastEdge _ prev; RETURN}}}; END. ^LichenData4Impl.Mesa Last tweaked by Mike Spreitzer on January 20, 1988 10:55:40 pm PST ‌تLک™IcodeڑœB™B—JکKڑدk œ©ک²Kکڑرbnxœ‌œ‌کKڑ‌œuک|Kڑœک—KکKڑ‌œ‌œ7دnœںœ‌œ‌œک…KکKڑœ‌œک$Kڑœ ‌œ ک.Kڑœ ‌œ ک.Kڑœ‌œک$KکKڑ œ‌œ‌œ‌œدcœک6Kڑ œ‌œ‌œ‌œ %œک=KکKڑœ/‌œکDKکKڑœ‌œکKڑœ‌œکKڑںœ‌œ‌œکKکڑں œ‌œک#Kڑœ ذcm œ5کcKڑœ ، œ ‌œکVKڑœ œک6Kڑœ œک4Kڑœ ، œ ‌œکSڑں œ‌œ‌œ‌œک&Kڑœ‌œکڑ ں œ‌œ‌œ‌œ‌œکIKڑ‌œ‌œ‌œ‌œک)Kڑ‌œ‌œ‌œ ‌œکKڑœpکpKڑœ‌œ‌œک#KڑœکKڑœ(ک(Kڑ‌œک —KڑœکKڑœ(ک(Kڑ‌œ‌œ‌œ>کZKڑ‌œک—ڑں œ‌œ‌œ‌œک&Kڑœ ‌œکKکKڑœ ‌œ‌œکKڑœ<‌œک@ڑں œ‌œک*Kڑœ)ک)Kڑœ%ک%Kڑœ‌œ‌œک$Kڑ‌œ‌œ‌œکKڑ‌œ‌œ‌œکKڑ‌œک—ڑں œ‌œک$Kکڑںœ‌œک'Kڑœ&ک&Kڑœ‌œ‌œک$Kڑ‌œ‌œ‌œکKڑ‌œ‌œ‌œکKڑ‌œک—Kڑœ3ک3Kڑ‌œک—KڑœکKڑ‌œ‌œ‌œ ‌œکKک—Kڑ‌œ‌œک—Kڑ‌œک —Kکڑںœ‌œں œ ، œںœ ، œ‌œکڑKڑœ œ*‌œک_Kڑœ œ/‌œ‌œکXKڑœ3ک3Kڑ‌œکKڑœB‌œ‌œکi—Kکڑںœ‌œ0‌œکJKڑœI‌œک_Kڑœ‌œ‌œکKڑœ ‌œکKڑœ‌œکڑںœ‌œک$Kڑœ ‌œ‌œکKڑœ ‌œ‌œکKڑœ‌œ‌œک0Kڑ‌œ‌œ‌œکKکKڑ‌œ‌œ‌œ‌œکKکKڑ‌œ ‌œ‌œکKڑœ‌œکKکKڑ‌œک—Kکڑں œ‌œ#ک6ڑ‌œ‌œ‌کKڑœ"‌œک*Kڑœ‌œکKڑœ‌œکKڑ‌œ‌œک—Kڑœ œ!‌œ ‌œکLڑںœ‌œ"ک3Kڑ‌œ‌œ‌œک$KکKڑ‌œک—Kڑœ2‌œ‌œکSKڑœ‌œ‌œکKڑœ‌œ‌œک:Kڑœ;ک;KڑœکKک$Kڑœ‌œکڑںœ‌œک$Kڑœ ‌œ‌œکKڑœ ‌œ‌œکKڑœ ‌œ‌œک*Kڑ‌œ‌œ‌œکKڑœکKڑ‌œ‌œ‌œک.Kڑ‌œ‌œ!‌œ‌ک2Kڑ‌œکKک KکKکKڑ‌œک—Kڑ ‌œ‌œ‌œ"‌œ‌œکDKکKڑ‌œ ‌œ‌œ‌œکKڑœ‌œک KڑœکKڑ‌œک —KکKڑ‌œک—…—!ى-–