TestCableImpl.mesa
Copyright © 1986 by Xerox Corporation. All rights reserved.
Last Edited by: Gasbarro October 3, 1986 12:21:02 pm PDT
Last Edited by: Don Curry July 13, 1987 9:59:45 am PDT
Don Curry January 31, 1987 2:54:20 pm PST
DIRECTORY
Basics, Commander, Core, CoreOps, IO, ICTest, Ports, Rope, TerminalIO, TestCable;
TestCableImpl: CEDAR PROGRAM
IMPORTS Basics, IO, CoreOps, Ports, Rope, TerminalIO
EXPORTS TestCable
= BEGIN
groupList: ICTest.Groups;
assignmentList: ICTest.Assignments;
clockAName: Core.ROPE;
clockBName: Core.ROPE;
Init:
PUBLIC
PROC [groups: ICTest.Groups, assignments: ICTest.Assignments, clockA, clockB: ICTest.
ROPE ←
NIL] ~ {
groupList ← groups;
assignmentList ← assignments;
IF clockA=NIL AND clockB=NIL THEN ERROR; --at least one has to be non-NIL
clockAName ← clockA;
clockBName ← clockB;
};
TestCable:
PUBLIC ICTest.TestProc = {
InitDrive:
PROC [wire: Core.Wire, port: Ports.Port]
RETURNS [subElements:
BOOL ←
TRUE, quit:
BOOL ←
FALSE]
--Ports.EachPortPairProc-- = {
IF port#NIL THEN port.d ← force;
};
EachPair:
PROC [wire: Core.Wire, port: Ports.Port]
RETURNS [subElements:
BOOL ←
TRUE, quit:
BOOL ←
FALSE]
--Ports.EachPortPairProc-- = {
SetBS:
PROC[seq: Ports.BoolSequence, b:
BOOL] = {
FOR i: NAT IN [0..seq.size) DO seq[i] ← b; ENDLOOP;
};
Cycle:
PROC = {
Eval[];
};
IF CoreOps.IsFullWireName[cellType.public, wire, a.name]
AND a.group#0
THEN {
IF port=
NIL
THEN
SELECT rootPort.levelType
FROM
ls => {rootPort.ls[count] ← H; Cycle[]; rootPort.ls[count] ← L};
bs => {rootPort.bs[count] ← TRUE; Cycle[]; rootPort.bs[count] ← FALSE};
c => {rootPort.c ← Basics.
BITSHIFT[08000h, -rootPort.fieldStart-count]; Cycle[];
rootPort.c ← 0};
lc => {rootPort.lc ← Basics.DoubleShift[[lc[080000000h]], -rootPort.fieldStart-count].lc; Cycle[]; rootPort.lc ← 0};
ENDCASE => ERROR
ELSE
SELECT port.levelType
FROM
l => {port.l ← H; Cycle[]; port.l ← L};
b => {port.b ← TRUE; Cycle[]; port.b ← FALSE};
ENDCASE => ERROR;
}
ELSE
IF port#
NIL
THEN
SELECT port.levelType
FROM
l => port.l ← L;
ls => {Ports.SetLS[port.ls, L]};
b => port.b ← FALSE;
bs => {SetBS[port.bs, FALSE]};
c => port.c ← 0;
lc => port.lc ← 0;
ENDCASE;
-- set the clock TRUE or no vector will be generated
IF CoreOps.IsFullWireName[cellType.public, wire, clockAName]
OR CoreOps.IsFullWireName[cellType.public, wire, clockBName]
THEN
IF port=
NIL
THEN
SELECT rootPort.levelType
FROM
ls => rootPort.ls[count] ← H;
bs => rootPort.bs[count] ← TRUE;
c => rootPort.c ← Basics.BITSHIFT[08000h, -rootPort.fieldStart-count];
lc => rootPort.lc ← Basics.DoubleShift[[lc[080000000h]], -rootPort.fieldStart-count].lc;
ENDCASE => ERROR
ELSE
SELECT port.levelType
FROM
l => port.l ← H;
b => port.b ← TRUE;
ENDCASE => ERROR;
IF port#
NIL
AND port.levelType#composite
THEN {count ← 0; rootPort ← port}
ELSE count ← count+1;
};
directionality: ICTest.Directionality ← force;
probe: INT ← 1;
count: NAT ← 0;
lastPin: NAT ← 0;
a: ICTest.Assignment;
rootPort: Ports.Port;
help: ICTest.ROPE ← "
Commands:
CR: proceed
b: step backward
j: jump
r: repeat
q: quit\n";
IF clockAName=NIL AND clockBName=NIL THEN ERROR; --no clocks
[] ← Ports.VisitBinding[cellType.public, p, InitDrive]; --initialize the drives
a ← ["xxyyzz", 0, 0, L, AB, A, 0, 1, 1, 1];
[] ← Ports.VisitBinding[cellType.public, p, EachPair]; --bogus call to initialize the clocks
TerminalIO.PutF["\n\nProbe Card Tester%g", IO.rope[help]];
FOR l: ICTest.Assignments ← assignmentList, l.rest
WHILE l#
NIL
DO
lastPin ← MAX[l.first.probeCardPin, lastPin];
ENDLOOP;
WHILE probe <= lastPin
DO
FOR l: ICTest.Assignments ← assignmentList, l.rest
WHILE l#
NIL
DO
a ← l.first;
IF a.probeCardPin = probe
THEN {
FOR l: ICTest.Groups ← groupList, l.rest
WHILE l#
NIL
DO
IF l.first.number=a.group
THEN {
directionality ← l.first.directionality;
EXIT;
}
ENDLOOP;
SELECT
TRUE
FROM
a.group=0 => {
TerminalIO.PutRope[IO.PutFR["Pin %g is unused, %g\n", IO.int[probe], IO.rope[a.name]]];
probe ← probe+1;
};
directionality=acquire => {
TerminalIO.PutRope[IO.PutFR["Pin %g is acquire only\n", IO.int[probe]]];
probe ← probe+1;
directionality ← force;
};
ENDCASE => {
DO
response: ICTest.
ROPE ← TerminalIO.RequestRope
[IO.PutFR["Ready to test pin %g, %g ...", IO.int[probe], IO.rope[a.name]]];
IF response.Length[]=0
THEN probe ← probe+1
ELSE
SELECT Rope.Fetch[response]
FROM
'b, 'B => {
probe ← probe-1;
TerminalIO.PutRope["\n"];
};
'j, 'J => {
--jump
probe ← TerminalIO.RequestInt["\nJump to pin: "];
IF probe < 1 THEN probe ← 1;
IF probe >LAST[ICTest.ProbeCardPin] THEN probe ← LAST[ICTest.ProbeCardPin];
GOTO MainLoop;
};
'q, 'Q => GOTO quit;
'r, 'R => probe ← probe; --redo
ENDCASE => {TerminalIO.PutRope[help]; LOOP};
EXIT REPEAT MainLoop => LOOP ENDLOOP;
[] ← Ports.VisitBinding[cellType.public, p, EachPair];
TerminalIO.PutRope["done\n"];
};
EXIT;
};
REPEAT
FINISHED => {
TerminalIO.PutRope[IO.PutFR["Pin %g not found\n", IO.int[probe]]];
probe ← probe+1;
};
ENDLOOP;
ENDLOOP;
};
END.