DrcCmosb.Mesa
Copyright Ó 1987 by Xerox Corporation. All rights reserved.
Written by gbb, January 12, 1987 11:47:17 am PST
gbb January 18, 1988 3:59:49 pm PST
Genista is the Grandson of Spinifex. It is a hierarchical design rule checker that monkeys around in a Core design and tries to find all the ChipNDale geometry in order to check as many design rules as it possibly can.
Gli uomini vollero piuttosto le tenebre che la luce (Giovanni, III, 19.)
DIRECTORY
CD USING [Layer, Number],
DesignRules USING [Rules],
Drc USING [Tech],
Rope USING [ROPE];
DrcCmosb: CEDAR DEFINITIONS
SHARES Drc ~ BEGIN
cMosBsimpleKey, cMosBcompleteKey: READONLY ATOM;
cMosBsimple does the same thing SoS did; GenistaCMosBcomplete verifies all VTI rules eccept for wells and transistors, which are not in Core.
CMosbTable: TYPE ~ REF;
Rule: TYPE ~ RECORD [extent: CD.Number, msg: Rope.ROPE];
Layer: TYPE ~ CD.Layer;
CMosbTableRec: TYPE ~ RECORD [
minWidth, maxWidth: ARRAY Layer OF Rule,
separation: ARRAY Layer OF REF ARRAY Layer OF Rule,
Via flatness rules:
viaOnFieldOxideAvoidsDiff, viaOnFieldOxideAvoidsPoly, fieldOxideSurroundsViaOnFieldOxide, diffSurroundsViaOnDiff, polySurroundsViaOnPoly: Rule,
In the following rules the extent is used only to determine the overlap of the error rectangle:
viaOnPolyAndDiff, viaSeparation, viaOverGate, viaOverPoly: Rule,
WellsEtc:
nWellSurround, pWellSurround, nWellContact, pWellContact, wellContactSpacing: Rule,
In the following rules the extent is used only to determine the overlap of the error rectangle:
wellConflict, NinN, PinP, isolatedWell: Rule,
Exception to gate rules:
diffCutToGate, largeDiffCutToGate: Rule,
Miscellaneous rules
difCutViaSpace, minPadSize: Rule];
NewTechnology: PROC [key: ATOM, rules: DesignRules.Rules] RETURNS [tech: Drc.Tech]
Allocation of technology records. Fills the rule tables for a given set of design rules. Must be called before calling CheckDesignRules. The key must be one of those exported from a technology dependent part of Genista. Returns NIL if a key is invalid.
END.