FSMTest.mesa
Copyright © 1987 by Xerox Corporation. All rights reserved.
Barth, June 15, 1987 5:01:36 pm PDT
Last Edited by: Don Curry July 20, 1987 10:28:58 am PDT
DIRECTORY CDCommandOps, CDProperties, CDSequencer, Core, CoreCreate, CoreFlat, Ports, Rosemary, RosemaryUser, Sisyph;
FSMTest: CEDAR PROGRAM
IMPORTS CDCommandOps, CDProperties, CoreFlat, Ports, Rosemary, RosemaryUser, Sisyph
= BEGIN
Binding
Vdd, Gnd, Reset, Clock, CountRowAdr, DriveCharMatch, LoadMatchAddress, ForceMatchLoad, SetReady, WriteMatchEnable, WriteCharEnable, LoadRowAdr, ReadStateEnable, RowAdrEqual, MatchChar, ReadCharMatch, WriteChar, WriteCharMatch: NATLAST[NAT];
InitPortIndicies: PROC [p: Core.Wire] ~ {
[Vdd, Gnd, Reset, Clock, CountRowAdr, DriveCharMatch, LoadMatchAddress, ForceMatchLoad, SetReady] ← Ports.PortIndexes[p, "Vdd", "Gnd", "Reset", "Clock", "CountRowAdr", "DriveCharMatch", "LoadMatchAddress", "ForceMatchLoad", "SetReady"];
[WriteMatchEnable, WriteCharEnable, LoadRowAdr, ReadStateEnable, RowAdrEqual, MatchChar, ReadCharMatch, WriteChar, WriteCharMatch] ← Ports.PortIndexes[p, "WriteMatchEnable", "WriteCharEnable", "LoadRowAdr", "ReadStateEnable", "RowAdrEqual", "MatchChar", "ReadCharMatch", "WriteChar", "WriteCharMatch"];
};
Test
InitializeTest: PROC ~ {
CDCommandOps.RegisterWithMenu[menu: $ProgramMenu, entry: "Simulate FSM", key: $FSMExtractAndSimulate, proc: FSMExtractAndSimulate, queue: doQueue];
RosemaryUser.RegisterTestProc["FSMTest", FSMTestProc]; 
};
FSMExtractAndSimulate: PROC [comm: CDSequencer.Command] ~ {
cellType: Core.CellType ← Sisyph.ExtractSchematicByName["FSMExample.icon", Sisyph.Create[comm.design]];
public: Core.Wire ← cellType.public;
InitPortIndicies[public];
Ports.IPList[public, LIST[Vdd, Gnd, Reset, Clock, CountRowAdr, DriveCharMatch, LoadMatchAddress, ForceMatchLoad, SetReady, WriteMatchEnable, WriteCharEnable, LoadRowAdr, ReadStateEnable, RowAdrEqual, MatchChar, ReadCharMatch, WriteChar, WriteCharMatch], b];
CDProperties.PutDesignProp[comm.design, $DAUserRoseDisplay, FSMSimulate[cellType].display];
};
FSMSimulate: PROC [cellType: Core.CellType] RETURNS [tester: RosemaryUser.Tester] ~ {
public: Core.Wire ← cellType.public;
Ports.ITDList[public, LIST[Reset, Clock, RowAdrEqual, MatchChar, ReadCharMatch, WriteChar, WriteCharMatch], force];
Ports.ITDList[public, LIST[CountRowAdr, DriveCharMatch, LoadMatchAddress, ForceMatchLoad, SetReady, WriteMatchEnable, WriteCharEnable, LoadRowAdr, ReadStateEnable], expect];
[] ← Rosemary.SetFixedWire[cellType.public[Vdd], H];
[] ← Rosemary.SetFixedWire[cellType.public[Gnd], L];
tester ← RosemaryUser.TestProcedureViewer[
cellType: cellType,
testButtons: LIST["FSMTest"],
name: "FSM Test",
displayWires: RosemaryUser.DisplayPortLeafWires[cellType],
cutSet: CoreFlat.CreateCutSet[labels: LIST["FSM"]]];
};
FSMTestProc: RosemaryUser.TestProc ~ {
MyEval: RosemaryUser.TestEvalProc ~ {
Eval[memory: TRUE, clockEval: TRUE];
Eval[memory: TRUE, clockEval: FALSE];
};
Init: PROC = {
p[Reset].b ← TRUE;
p[Clock].b ← FALSE;
MyEval[];
p[SetReady].b ← TRUE;
p[Clock].b ← TRUE;
MyEval[];
};
InitPortIndicies[cellType.public];
Init[! Rosemary.Stop => IF reason = $BoolWireHasX THEN RESUME ELSE REJECT];
p[Reset].b ← FALSE;
p[Clock].b ← FALSE;
MyEval[];
p[SetReady].b ← FALSE;
p[LoadRowAdr].b ← TRUE;
p[Clock].b ← TRUE;
MyEval[];
p[Clock].b ← FALSE;
MyEval[];
p[Clock].b ← TRUE;
MyEval[];
p[MatchChar].b ← TRUE;
p[Clock].b ← FALSE;
MyEval[]; -- M1
p[LoadRowAdr].b ← FALSE;
p[CountRowAdr].b ← TRUE;
p[DriveCharMatch].b ← TRUE;
p[Clock].b ← TRUE;
MyEval[];
p[MatchChar].b ← FALSE;
p[Clock].b ← FALSE;
MyEval[]; -- M11
p[ForceMatchLoad].b ← TRUE;
p[LoadMatchAddress].b ← TRUE;
p[Clock].b ← TRUE;
MyEval[];
p[Clock].b ← FALSE;
MyEval[]; -- M2
p[ForceMatchLoad].b ← FALSE;
p[Clock].b ← TRUE;
MyEval[];
p[Clock].b ← FALSE;
MyEval[]; -- M2
p[Clock].b ← TRUE;
MyEval[];
p[RowAdrEqual].b ← TRUE;
p[Clock].b ← FALSE;
MyEval[]; -- M3
p[CountRowAdr].b ← FALSE;
p[Clock].b ← TRUE;
MyEval[];
p[RowAdrEqual].b ← FALSE;
p[Clock].b ← FALSE;
MyEval[]; -- M4
p[DriveCharMatch].b ← FALSE;
p[SetReady].b ← TRUE;
p[Clock].b ← TRUE;
MyEval[];
p[RowAdrEqual].b ← FALSE;
p[Clock].b ← FALSE;
MyEval[]; -- Idle
p[LoadMatchAddress].b ← FALSE;
p[SetReady].b ← FALSE;
p[LoadRowAdr].b ← TRUE;
p[Clock].b ← TRUE;
MyEval[];
};
Start Code
InitializeTest[];
END.