DAUserDrcCmd.mesa
Copyright Ó 1987 by Xerox Corporation. All rights reserved.
Last Edited by: Louis Monier January 7, 1987 8:15:20 pm PST
Last Edited by: Christian Jacobi, January 7, 1987 11:41:28 am PST
Jean-Marc Frailong December 8, 1987 9:55:49 pm PST
Barth, April 2, 1987 11:58:37 am PST
Bertrand Serlet September 15, 1987 8:12:20 pm PDT
DIRECTORY
CD, CDSequencer, CDSequencerExtras, Core, CoreCDUser, CoreOps, DesignRules, Drc, DrcCMOSB,
IO,
PW, PWCore, Rope, TerminalIO;
DAUserDrcCmd:
CEDAR
PROGRAM
IMPORTS CDSequencerExtras, CoreOps, CoreCDUser, DesignRules, Drc, DrcCMOSB, IO, PW, PWCore, TerminalIO
= BEGIN
GetRules:
PROC [design:
CD.Design]
RETURNS [drcAtom:
ATOM, techD: Drc.Tech] = {
rules: DesignRules.Rules;
drcAtom ← DesignRules.FetchRulesID[design];
IF drcAtom = NIL THEN drcAtom ← $VTI;
rules ← DesignRules.GetRuleSet[drcAtom ! DesignRules.DesignRuleError => CONTINUE];
IF rules =
NIL
THEN {
TerminalIO.PutF["Unknown design rule key: %g\n", IO.atom[drcAtom]];
drcAtom ← $VTI;
rules ← DesignRules.GetRuleSet[drcAtom];
};
techD ← DrcCMOSB.NewTechnology[DrcCMOSB.cMosBcompleteKey, rules];
};
ExtractAndDrc:
PROC [comm: CDSequencer.Command] = {
DoOne: CoreCDUser.EachRootCellTypeProc ~ {
quantity: INT ← 0;
name: IO.ROPE ← CoreOps.GetCellTypeName[root];
ect: Core.CellType;
obj: CD.Object;
TerminalIO.PutF["Generating and extracting layout for %g.\n", IO.rope[name]];
[layout: obj, extractedCT: ect] ← PWCore.LayoutInfo[root];
TerminalIO.PutF["Layout generation and extraction done for %g.\n", IO.rope[name]];
TerminalIO.PutF["DRC checking %g.\n", IO.rope[name]];
quantity ← Drc.CheckDesignRules[cell: ect, external: CoreOps.CopyWire [ect.public], tech: techD, viaFlatness: viaFlatness, stopFlag: NEW [BOOL ← FALSE], layout: PWCore.extractMode.decoration];
IF quantity>0 THEN {[] ← PW.Draw[obj]; TerminalIO.PutRope["*** "]};
TerminalIO.PutF["Finished %g Drc of %g: %g violation%g. %g\n",
IO.atom[drcAtom],
IO.rope[name],
IO.int[quantity],
IO.rope[IF quantity#1 THEN "s" ELSE ""],
IO.rope[IF viaFlatness THEN "Via flatness checked." ELSE ""]];
};
lastBadOb: CD.Object ← NIL;
viaFlatness:
BOOL ←
SELECT comm.key
FROM
$LayoutNDrcViasOn => TRUE,
$LayoutNDrcViasOff => FALSE,
$LayoutNDRC => (TerminalIO.RequestSelection[
header: "Check Via Flatness",
choice: LIST["Check via flatness", "Don't check via flatness"],
headerDoc: "Set up flat data structures to check via flatness",
choiceDoc: LIST["Not reasonable for large (>3 level) hierarchies", ""],
default: 1] # 2),
ENDCASE => ERROR;
drcAtom: ATOM; techD: Drc.Tech;
[drcAtom, techD] ← GetRules[comm.design];
TerminalIO.PutF["Using %g design rules.\n", IO.atom[drcAtom]];
[] ← CoreCDUser.EnumerateSelectedCellTypes[comm.design, DoOne];
};
CDSequencerExtras.RegisterCommand[key: $LayoutNDRC, proc: ExtractAndDrc, queue: doQueue];
CDSequencerExtras.RegisterCommand[key: $LayoutNDrcViasOn, proc: ExtractAndDrc, queue: doQueue];
CDSequencerExtras.RegisterCommand[key: $LayoutNDrcViasOff, proc: ExtractAndDrc, queue: doQueue];
END.