1. Louis, Rick, and Bertrand with hard hats in construction area.  Louis and Rick are unrolling a plot of the building electrical circuits on a table while Bertrand leans on it.  He looks up.
Bertrand  As you can see, we are building real circuits here.  
2. Cut to wiring diagram on table with three pairs of hands framed on the edges.  
3. Cut back to original camera angle.  Zoom in to Bertrand.  He takes off his hard hat.
Bertrand  The second part of this tape is devoted to several examples.  These examples illustrate in greater detail design capture, integration and layout.
--------
1. Logic slide: 
Libraries
Design Knowledge Capture
Rick  Over time, a number of common parameterized macros have been collected into a library of circuit generators.  
2. Cut to B&W screen: Logic2 library (not Logic!!!), zoom and tilt down 
Rick  The library includes the usual fixed size gates point, and their parameterized versions point.  The more complex macros include registers, adders, comparators, shift registers, memories, counters, and many varieties of multiplexors.
3. Zoom out to include the whole library
Rick  Providing this functionality while keeping the library small was a challenge.  This challenge was met by mixing programs and schematics appropriately.  An example will help explain this.
4. Cut to Color display with Logic2 on it: Shift Register icon (space-tab, one zoom out); attach satellite b_8; X-left
Rick  For a designer, this shift register is simply an icon whose width is the numerical parameter, b.  During the extraction, the current value of b, in this case 8, is passed along since it is needed to construct the netlist.
The netlist for this icon is generated by extracting its associated schematic.  We can access this schematic with a single click X-left.  
5. Cut to Color display: schematic for shift register
Rick  The schematic defines a shift register as composed of a register point, a multiplexor point, a NOR gate point, and small icons operating on the structured wires point.  Notice that all these elements are parameterized by expressions using the variable b.  
Let's follow the path of extraction into the register.  A hidden annotation specifies a function in the module defining the library.
6. Cut to B&W display: Code for register
Rick  This function takes as argument b, the number of bits, and returns the data structure that defines the register.  Apart from performing a check point and attaching a behavioral model point, the function requests the extraction of another schematic cell point.  

Register: PROCEDURE [b: INTEGER] RETURNS [cell: CellType] = {

IF b=0 THEN Error["Please specify a non-zero size for the register"];

cell _ Extract["register.sch", ["b", b]];  -- extract another schematic

AttachBehavioralModel[cell, RegisterSimulationProcs];

};

7. Cut to Color display: schematic for register
Rick  This closes the loop between the graphical and procedural domains, and demonstrates that schematics and code can be used interchangeably.  The choice of the most practical representation is always left to the designer.
The register is thus described as a sequence of D flip-flops, and a buffer for the control lines.  We already have encountered such sequences, so let's concentrate on the complementary buffer.  The load parameter specifies the number of unit gates that the buffer is to drive.  Once again, the icon specifies a function.
8. Cut to B&W display: Code for driver
Rick This time, the function chooses to extract a schematic according to the value of the load point.  This sort of case analysis and expression evaluation is best handled in a standard programming language.

SymDriver: PROCEDURE [load: INTEGER] RETURNS [cell: CellType] ~ {

SELECT load FROM  -- extract a schematic according to the range of load

<=0 => Error["Please specify a non-zero load for driver"];

<=3 => cell _ Extract["symDriver3.sch"];

<=6 => cell _ Extract["symDriver6.sch"];

ENDCASE => { -- use constant amplification in 3 stages

n2: NAT = (load+3)/4; -- last inverting stage

d1: NAT = load+n2;    -- logic drive of initial non-inverting driver

cell _ Extract["symDriver.sch", ["n2", n2], ["d1", d1]];

};

AttachBehavioralModel[cell, SymDriverSimulationProcs];

};

9. Cut to Color display: three different schematics for symmetric driver
Rick For small and medium loads, the function picks fixed-size buffers; for larger loads, the buffer is itself a schematic which accepts two parameters.
10. Cut to Rick in front of workstation
Rick  It is time to put a halt to this recursive walk through the shift register, but it is clear that after another couple of steps, the shift register would be completely described in term of basic gates and D flip-flops.
11. Cut to icons of shReg, multiplexer, register, symDriver (from previous shots)
Rick  During this exploration, we came across many parameterized macros: register, multiplexor, and several types of buffers.  This situation is very common and illustrates that such parameterized macros can be re-used very easily.  In fact, it is an excellent way to encapsulate knowledge about common circuits, and share it among designers.
12. Cut to Color screen:
drivers (top right of logic),
CounterUp.sch, 
decoded b-bit muxes definitions: 2,3,4, general case
Rick  In addition to complex circuit structures, other types of knowledge can be captured algorithmically: optimal sizing of buffers show a buffer, the proper carry-look-ahead structure for adders or counters show a counter, and special cases for common values of the parameters show small mux.
13. Cut to previous view of Logic library
Rick  This library is more than a collection of fixed common gates.  Each simple parameterized icon, such as the n-input AND gate, is equivalent to a family of circuits in a normal circuit library.  The more complex parameterized icons embody algorithms for assembling basic gates, such as carry-look-ahead networks.
14. Cut to Rick in front of workstation
Rick  In short we've emphasized two ideas:
code is an integral part of the source,
and code plus parameterized schematics form an extremely powerful circuit description language.
--------
1. FSM Slide. 
Finite State Machines
Source Level Debugging
2. Cut to Color Display: PopAndReply.fsm. 
Louis  Here is a finite state machine.  It consists of states and transitions. circle them  The states are named point to PopRp and have outputs associated with them.  point to PopFifo and LoadReply.  The transitions are conditioned by boolean expressions upon the inputs point to the expression Free*DataAvail.
3. Cut to fsm.sim + PopAndReply.fsm + PopAndReply.icon on color screen, then zoom on oracle. 
Louis  Now, this is a set up for simulating the previous finite state machine, abstracted here by this icon.  Clock generators circle and a tester emulation cell circle complete the set-up.  The tester emulator makes reference to a file circle that contains stimulus test vectors, as well as expected outputs.
4. Cut to B&W screen showing ThisFSM.oracle 
Louis Inputs are on the left, expected outputs are on the right.
5. Cut to color screen.  Invoke space F Rosemary Create Simulation.  
Louis That's all we need for simulating the FSM.  Let's initialize the simulation ...
6. Cut to left side of B&W screen showing Rosemary control panel (top), oracle file, and scope properly scaled with a few nodes displayed.  Start Test then interrupt. 
... and simulate for a while.  
7. Zoom on waveforms.
Louis We can see the state machine running. However, we have to infer the state of the machine from its outputs, which is a difficult task.  Our system provides a mechanism for displaying the state of an FSM, in much the same way we display node states.  Let's plot the state of this FSM.
8. Cut to Color Screen, Space F Rosemary Plot Cell State, cut back to waveforms 
Louis We can see that the state names are displayed.  These names were assigned by the designer during design capture.  This is far easier than inferring the state from the outputs.  This feature offers circuit designers the same advantages as source-level debuggers for software developers.
9. Cut back to oracle file (grow it on the screen).  Replace (4th row) an X by a 0.  Close viewer (bug appears).  
Louis Let's now modify the test vectors edit, and take the risk of introducing an error save and close.
10. Open rosemary panel and scope.  Push start test.  Zoom out.  The oracle file pops up.
Louis Now let's start the simulation again click.
Tough luck.  The simulator signals an error by opening the file and points to its location among the test vectors.  
Again, the interaction between the tool and the designer happens through the same medium used for design capture, in this case the test vectors.  It is another instance of source-level debugging.
11. Cut to face shot, some flash-backs of color screen, oracle file, and back to face.
Louis We've just seen an pristine example of tight integration.  The simulator communicates with the designer in terms of the original source, be it test vectors or schematics.
--------
1. Data Path Slide. 
Data Path
Rick A common companion to  finite state machine is a data path.  To us data path generation is primarily a layout optimization rather than a mechanism for logical specification.
2. Use dissolve to simulate animation.  Put down a sequence of blocks (with wire stubs on left and bottom) vertically labelled: Reg, Xor, And, Reg.  Put down sequence of horizontal wires connecting the blocks.  Put down sequence of vertical wires connecting the blocks, share some tracks.  Take whole thing and replicate it horizontally.
Rick With our data path generator the designer specifies the placement of the primitives vertically, the assignment of horizontal tracks, the assignment of vertical tracks, and the replication of the resulting bit slice horizontally.
3. Scroll through plot of testarossa schematic.
Rick This is the type of picture a designer draws to specify a data path.  The data path generator is implicitly controlled by the relative placement of the primitives and wires in the schematic.  Additional control such as the number of repetitions is provided textually.  This is an example of a more general feature of the system, which is the ability for any generator to access and interpret the source in its own manner.
4. Cut to plot of testarossa layout.
Rick The right half of this plot is a data path.  The random control for it is in the standard cells on the left.
5. Cut to Rick in chair.
Rick The data path is a good example of the extensibility of our system architecture.  It was added to the system by a designer because he needed it to optimize a portion of his chip.  It uses the standard editor and user interface.  
6. Cut to layout tree with datapath operator embedded in it, point to the datapath operator and then to the primitives.
Rick It also fits into the standard layout generation framework.  The layout primitives are computed using the same recursive tree walk as is used for any other piece of layout.  Some layout constraints must be met but the general mechanism is still used.  For example the width of each element must be identical but an element can be assembled from a series of abutments.  Similarly the result of data path generation may be used by higher level operators as a primitive.
7. Cut to data path library and pan through it.
Rick Data paths are similiar to standard cells in their use of predefined cell libraries.  Just as in our standard cell system it is easy for a designer to create a new cell, or even a whole new library, which is optimized for his needs.  Unlike standard cells the majority of the placement and routing is explicitly specified.  The tight control of the layout is a small burden for the designer since data paths are quite regular.
8. Cut to slide
Routing Channels
Dynamic Multiplexor Construction
Bit Interleaving
Snap Ons
Rick This data path generator has become a fundamental part of our layout generation tools.  Several important optimizations are required to cover the wide range of situations we have already encountered in our designs.  Let's briefly look at each of these.
9. Cut to testarossa schematic; focus on InhibitData.
Rick In some situations the routing is not uniform across the width of a data path.  To accomodate this the data path generator allows a routing area, instead of a functional block, to be defined as a row.
10. Cut to testarossa layout; focus on InhibitData; pan from right to left showing wires dropping off.
Rick Input buses, shifters, and carry-look-ahead adders are typical portions of data paths that require this type of routing.
11. Pan up to 3 input multiplexor.
Rick The cells which are constructed dynamically can be more sophisticated than just routing.  Highly design dependent cells such as multiplexors can also be synthesized on the fly.
12. Cut to slide 9.12 on color monitor
Rick An important optimization is bit level interleaving.  If multiple logically distinct datapaths have bit level communication it is important to interleave a bit from the first data path with a bit from the next and so on.  In this example the green data path supplies a value to a multiplexor in the red data path.  If the red and green data paths are interleaved the interconnect is small.  If they are not interleaved, all the red cells on the left and all the green on the right, then the routing area quickly dominates.
13. Animation.  Show RAM bit replicated vertically, then horizontally, finally add decoder snap on.
Rick Frequently highly regular decoders need to be attached to the side of a data path.
14. Cut to testarossa layout; focus on ram snap on.
Rick These attachments, or snap ons, are abutted to the replicated bit slice.  The routing below combines the wires from the replicated bit slice and the snap on.
15. Cut to Rick in chair.
Rick Our data path generator allows detailed control of placement and routing to exploit the regularity inherent in a data path.  Unlike other data path generator systems the clocking style, number of buses, types of register banks and so on are not constrained in any way.  Instead the designer can implement any net list he likes.  The purpose of the data path generator is to help him organize the tiling of the silicon plane.
--------
1. Slide
Fashion Show
2. Louis seating on the edge of a table, next to a screen, plot in the background.  We will insert a brief shot of Jim and Louis in the test lab. 
Louis Even though our system was developed in a research environment with limited manpower, it has produced many examples over the past three years. In fact, it has been stress tested with a variety of large circuits close to the state-of-the-art in complexity.
3. Show Photo of Crossram
Louis  This is the very first circuit.  It is full-custom and is assembled by program.
4. Show EU on wafer and highlight the blocks the areas as designer talk.
Louis  The earliest circuits form a 5-MIPS processor on two chips. The datapath chip has a datapath including a large register file, two PLAs, and a small block of standard cells.  
5. Same with IFU on wafer, highlight the datapath and both control blocks.
Louis The control section of the processor is made of a datapath in the center and a variety of PLAs on the sides.  Both circuits were designed while the system was still evolving, and make heavy use of the simpler layout operators.
6. Same with BIC on wafer: highlight the SC block, a slice, and then all slices.
Louis In addition to a strange aspect ratio, this interface circuit has a standard cell block and a full-custom part made of high-power cells, hand-placed, then routed and duplicated.
7. Same with Clock toy on wafer; highlight the circuit.
Louis This simple test circuit is generated in a similiar fashion.  Its complete design, through layout generation, was accomplished in a matter of hours.
8. Same with wafers of AFS; highlight the circuit.
Louis Several circuits only use one type of layout generator.  This frequency synthesizer is a large interleaved datapath.  
9. Same with wafers of Arbiter and Dynabus Exerciser.
Louis This cicuit is made solely from standard cells.  Generating its layout from its logical description requires very little manpower.  Here is another circuit of the same type.
10. Louis in front of a plot of the mapcache; he points as he talks.
Louis A remarkable aspect of the system is the size of the source for the circuits: here is a 170,000 transistors circuit, layed out with standard cells and standard memory blocks.  
11. Louis now points to a plot of the schematics; then camera zooms on interesting parts.
Louis The entire source description for this circuit fits here.  Because it uses standard components, its implementation took only one man-month.
12. Back to wafer shot of IO Bridge then plot of Display Controller
Louis Here is another example of designs using only library elements, such as standard cells, memories, and pads.
13. Wafer shot of Memory Controller; highlight the data path.
Louis When sufficient circuit density cannot be obtained with standard components, the designer can trade-off design time by using more precise layout generators.  
In this example, it is necessary to use a large datapath in order to reduce the area sufficiently.
14. Color Screen shots of DACTapeFullCustom.
Louis Finally, in order to benefit fully from a new technology, a few circuits will always need full-custom parts, such as this tester chip or this cache.
--------
1. Cut to Bertrand in chair.
Bertrand This completes the tour through our system.  In this tape we emphasized the explanation of a few basic principles rather than a complete review of all the tools available.  Timing analysis, design rule checking, layout vs. schematic comparison, and circuit simulation are examples of tools which we did not have time to present. 
2. Flash LatchIfValid.sch and code from 7.7
Bertrand The capture of a design as a program composed of both textual and graphical elements is simple and effective.  Both are needed because some parts of a design, generally the declarative parts, are most naturally described with pictures while others are most naturally described algorithmically (with code).
3. Cut to system architecture slide
Bertrand The common design data structure with links to the original source vastly simplifies the implementation of the system.  It leads to a consistent and convenient user interface.  It drastically reduces the number of lines of code in the design automation system.
4. Cut to Layout: Abut, DataPath, SC
Bertrand The architecture for layout generation utilizes the logical source in a natural manner thereby eliminating redundant design description.  Our experience has shown it is a good framework for integrating a large variety of layout generators, from finely controlled full custom operators to automatic operators.
5. Cut to Bertrand in chair.
Bertrand All of these features help people be more productive.  They reduce the time and the number of people required to design integrated circuits.  
--------
1. Slide Credits superimposed on fixed frame of group picture.
Rick Many people in the PARC Computer Science Laboratory contributed to the evolution of this set of tools over the past three years, especially the designers in the Dragon project.  Rapid software development was made possible by the Cedar programming environment.
2. Zoom on VLSI licence plate; car drives away.  
3. Switch to Xerox logo cut from some Xerox ad spinning up and filling frame.  
--------
7: Does this section explicitly state the principles of:
ubiquitous arbitrary properties
model of interpretation
9.3: polish
10: Use this section as an opportunity to enumerate features of the system as well as enumerate the chips which have been produced.
BS: which bugs do we use???
Screen and chair shots
2.1: Louis in chair
7, 8, 9: both screens; both Louis and Rick in chair
7.11 Collect these icons together in DACTape.dale
9.4: data path in IFUSch.dale PCFormBot PCAltPipe1A
10.1: Louis (replaces the tester room)
10.14: DACTapeFullCustom
11: Bertrand in chair (or outside? nice room with plants)
Animation from screen (Make sure to number the steps and alternate tapes)
9.2: B&W screen; animation by drawing and cutting later
9.12: B&W screen; more of the same
9.13: B&W screen; more of the same
Plots
9.6: layout tree with datapath operator embedded (**)
9.7: data path library
9.9: routing channel in the middle of a data path (screen? **)
9.10: shifter or carry-look-ahead routing channel (screen? **)
9.11: data path layout; routing channel plus first row of cells on either side (screen? **)
9.12: n squared to n reduction due to datapath interleaving (screen? **)
10.2: Photo of Crossram
10.10: Louis in front of a plot of the mapcache layout
10.11: Louis in front of a plot of the mapcache source
12.1: Credit pictures
Car chase
1: Bring both cars; fix licence plate.
Also shoot the car from the back as it leaves. (for the end of tape 2)
Construction site
6: Bring hard hats and plots.  Rick, Louis, Bertrand unrolling plots.
Test lab
10.1: Louis in front of tester
Slides
7, 8, 9, 10: Title
9.8: features of DP
Push Cue
5.X: Find a good sound to add to Push / Pop
Change voice over
4.4: Rick.  Current take is too sad.
5.9: Louis.  Sound is bad.


´DACTape2.tioga
Louis Monier April 26, 1988 9:13:30 am PDT
Bertrand Serlet April 18, 1988 1:10:59 am PDT
Barth, April 25, 1988 6:47:28 pm PDT
6. Introduction (0.5 minutes)
7. Logic (4.5 minutes)
8. FSM (2.5 minutes)
Install celllibraries fsm bugs
9. Data Path (3.5 minutes)
10. Examples of Circuits (3 min)
11. Review (2 minutes)
12. Credits (0.5 minutes)
Possible edits of the script
What has to be shot
To be ready by edit time
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