1. Cut to PARC sign from far away through a zoom, Pinto drives by it, followed by VLSI car

2. Cut to driveway, VLSI car drives towards camera and brakes hard, zoom on license plate

Some peppy music. **

3. Dissolve to layout plot on wall, then zoom back and center on Rick in a chair

Rick You are about to see a description of an environment for the design of integrated circuits. This design automation system was developed in the Computer Science Laboratory at the Xerox Palo Alto Research Center.

The system is fairly complete. It includes tools for design capture, analysis, layout generation, and layout verification.

4. Dissolve to slide showing system model, highlight each point.

Rick In our design system we capture the source description of a design as a mixture of text and pictures. This source is then executed, or interpreted, to create an annotated net list. This net list is the common data structure used by all of our tools as their design description.

5. Cut to Rick in chair

Rick We don't have time to cover the entire system in detail. Instead we will focus on three key points.

6. Dissolve to slide showing the three points; hightlight each point as speech goes

Rick We represent and manipulate designs as abstractions such as transistors or finite state machines. Parameterized schematics and a small amount of code capture the design.

All of the information in the source description is processed into a single extensible data structure. All of the tools operate directly on this representation.

Layout is generated by walking over this common data structure. All the generation parameters are specified with source annotations.

7. Cut back to Rick in chair; cut away with views of chips,

Rick The system includes the capability to design full-custom circuits, parameterized module generators, datapath generators, and standard cells. A single circuit can easily make use of all of these design styles.

1. Cut to Slide "Design Capture" (silent)

2. Dissolve to Rick sitting in front of a workstation

Rick We can capture designs at a high level of abstraction. Let's illustrate this with an example.

3. Zoom to Color screen; DACTape.dale, Ugly.sch

Louis This schematic represents an 8-bit wide register circle. The input is latched only when the four high-order bits satisfy some condition circle. Even though the sizes involved are fairly small, the circuit description is already cumbersome; it would quickly become unmanagable if the bus was wider.

4. Cut to Color screen; DACTape.dale, Better.sch

Louis This is an equivalent representation of the previous circuit.

The register circle is described as a sequence of flip-flops. The picture specifies the minimum amount of information needed to describe this sequence: the cell to be repeated circle, the repetition factor circle, the wires to be sequenced circle, and the ones to be shared by all cells circle, such as the clock.

Another improvement in the legibility of the schematic comes from the use of structured wires. This wire circle is now an 8-bit wide bus. This small symbol circle specifies the 4 high-order bits of this bus.

This AND gate circle deserves some explanation: it is a general parameterized gate which accepts the number of inputs as its parameter. A function defined in a library provides a decomposition into more basic gates.

5. Cut to Color screen; DACTape.dale, LatchIfValid.sch

Louis In this version of the schematic, we replace the numerical constants by symbolic values. Notice circle that the width of the wires and the size of the sequences now depend on two parameters. This parameterized schematic demonstrates the expressive power of the system. Let's outline how general this mechanism really is.

6. Cut to slide "Schematic Extraction". Highlight each point.

Rick There is a correspondence between the extraction of schematics and the execution of programs. The extractor itself is equivalent to an interpreter; an icon to a function header; a schematic to a function body; and, therefore, the process of extraction is the same as function execution. The result of executing the top level function is the common data structure.

7. Cut to Rick in chair.

This schematic extractor uses a general purpose interpreter to evaluate parameters, and to call arbitrary programs written in a standard programming language. New code defined by the designer can be executed this way. This makes the system extensible. General parameterization would not be possible without this general evaluation mechanism.

8. Cut to Color screen: DACTape.dale, LatchIfValid.sch and icon

Rick We can see now that our parameterized schematic is equivalent to a function definition.

The icon circle abstracts the circuit. It can be instantiated by providing values for the two parameters circle.

9. Cut to split screen of Plots of Ugly and LatchIfValid.sch with icon

Rick By comparing the flat representation against the parameterized schematic, the advantages become clear. This design representation is both concise and legible, making the source easier to comprehend and manipulate. It can be reused in many places, and shared among designers.

1. Louis walks to Plot of Memory Controller Source Plot (padframe cut on the side)

Louis Let's browse through different examples of schematics in order to illustrate other ways to capture abstractions.

2. Zoom on plot: FSM (voice over)

Louis This is a finite-state-machine represented by its state transition diagram.

The most notable thing about this picture is that it is a common way to represent a finite state machine. At the same time, the schematic extractor is able to interpret this picture and generate an internal representation for it. From there, it can derive a behavioral model, or a layout based on standard cells or PLAs.

3. Cut to plot: Pan on Data path (voice over)

Louis Each of these three columns represents a datapath. The abundance of information in the schematic is used to drive the layout generation very precisely.

4. Cut to plot: Pan over Pads (voice over)

Louis This description of the core of a circuit inside its padframe acts very much like a floorplan. It is used for layout generation. It is clear enough to be the only documentation of the physical circuit interface.

5. Cut to Plot: block of SC

Louis More generally, we capture not only the structure of the circuit, but also arbitrary annotations needed by other tools:

6. Cut to Rick on a chair

Rick We have seen several varieties of parameterized schematics. They can be mixed arbitrarily within a single design, because the same schematic extractor interprets them all.

This contrasts with typical net-list capture tools that expect schematics to have a fixed "look", and interpret them only in a fixed manner. Our system leaves the door open for the capture of circuits in almost any form which makes sense to the designer.

1. Cut to Slide "Integration"

Rick Another key feature of our system is integration. All of our tools are integrated into a coherent environment for designing circuits.

2. Cut to color screen. Pan across schematics, FSM, and layout; voice over

Rick Designers use the same general graphic editor for both schematics and layout.

3. Cut to B&W screen, schematics and layout in document AussiePWPaper.tioga 4.1

Rick A general text editor accomodates text and pictures in the same document. We use it for writing code that completes the source description of circuits, and for documentation.

4. Cut to system model slide with only one tool and bidirectional arrows

Rick Making the user interface uniform is important. In our system this is achieved by providing the tools with generic functions to map from the source to the common data structure and back. Let's see what this allows.

5. Cut to B&W screen; left: MapCache FifoCtrlTest+oscillo; right: panel

Louis What you see here is a circuit under test circle. The simulation is running. Let's interrupt it. do so And add node plots to the display by specifying them in the schematic. V left every wire, hit reset on plot viewer. Here they are. Let's continue the simulation. do so

This feature is very useful when debugging a simulation. It is only possible because of a tight coupling between the source representation and the simulator.

6. Cut to Color screen; ram2Cell.sch; poke a wire and the corresponding layout is highlighted; shoot cells separately; mix at editing.

Louis Source and layout are also tied together. We see here a cell circle schematic and its layout. I can select a wire, and highlight the corresponding wire in the layout. do so

7. SPACE-F menu

Louis Move the cursor through each of the tools, pausing long enough at each one to allow documentation to be read Graphical interactions with the source allows a designer to specify a net or a device for any of the available tools. Conversely, tools can provide visual feedback, such as highlight or selection.

8. Cut to DACTape.LatchIfValid both icon and schematic. Edit out the pause while the command runs and the rescaling.

Louis Select the LatchIfValid icon and invoke the static hierarchical check Let's demonstrate highlighting on one of our previous examples. One check we can perform statically is ensuring that each node is connected to at least two devices. Cut to highlighted error. In this cell the q bar output fails this check. Performing this highlight looks simple but let's recall that this rectangle is part of a function definition, not part of the netlist itself. The highlighting mechanism uses links from the net list back to the source which generated it in order to find the rectangle you see highlighted.

9. Push into flipflop, browse through disambiguation viewer, post inverted clock.

Louis Since rectangles are pieces of function definitions which generate net lists it is possible for a single rectangle to correspond to many nodes in the net list. For example if we look in the schematic of the flipflop and try to post the inverted enable we don't know which of the eight enables is specified using only the information from the graphical source. We need some additional information to choose one of the eight. This is the purpose of the disambiguation viewer. In this case it displays the name of the ambiguous sequence of flip flops followed by buttons to pick one of them.

10. Cut to Rick in chair.

Rick Another aspect of integration is the transmission of data between tools.

11. Dissolve to system model slide with path from tool A to data structure to tool B highlighted.

Rick Tools in our system transmit data by adding annotations to the common data structure. Communication is then a matter of convention between the tool generating the data and the tools which use it. In a system with N tools this reduces the number of communication paths from N2 to N. Finally since we communicate through main memory there are no print or parse routines and communications never slow down computations.

12. Dissolve back to original system model slide.

Rick This system structure has several advantages: it is extensible, enhances code sharing, and is efficient. For implementors, it reduces the amount of manpower required to build a complete DA system. For designers, the tool model is simple, a rich set of highly interactive tools is provided, and they all have a consistent user interface.

1. Slide "Layout Generation"

Rick The last portion of our system we will cover in detail is layout generation.

2. Cut to slide DACTape.dale LayoutTree

Rick Layout is generated by a recursive process of bottom up construction. Here is an abstraction of the common data structure with the layout operators shown for each cell. Additional parameters required by an individual layout operator, such as the number of rows in a standard cell placement, can also be placed upon a cell by annotating the original source description.

Let's work through an example using a real circuit.

3. Cut to plot of MapCache (MapCacheTop.icon) Push cue.

Louis This is the top level of a circuit. Let's probe its structure. (Introduce visual clue for push in sch).

4. Cut to plot of MapCache (MapCacheTop.sch)

Louis The circuit is composed of four rows of pads and a core.

5. Zoom on MapCache (Inner.sch)

Louis The core is made of three RAMs on the left and a control block on the right. Let's concentrate on the top-left RAM. It is an instantiation of a library element. Notice the parameters specifying that there are 16 lines of 78 bits.

(push, push, push) The RAM is described in the same manner. Eventually we reach the description of a line of the RAM array. All the parameters have known values. The line is described as a sequence of memory elements. Now let's probe the memory element itself.

6. Push cue into LogicRam2 (ram2Cell.sch, layout atom on yellow); move to layout cell

Louis (push) It is described as a transistor netlist. The text in the yellow background is the layout annotation. It specifies that the layout operator to be applied to this cell is the Get operator. This operator simply retrieves the hand-drawn layout.

7. Select each of the public wires and use highlight layout to show the correspondence of the interfaces. Mix the layout and schematics on the screen during postproduction.

It also checks that the layout and source description have compatible interfaces.

Let's follow the thread of control as the layout assembly proceeds.

8. Cut back to sequence (pop cue),

Louis (pop) Now that the layout for the memory cell has been produced, the layout of the line can be assembled. At this point we know that there are 78 memory cells in a line. The layout annotation specifies that the layout of the basic cells must be abutted horizontally. As with any layout operator, an interface check is performed on the resulting layout.

The 16 lines are then abutted vertically, and the ram is completed with I/O interfaces and address decoders.

9. Back to Inner.sch

Louis (pop, pop, pop) The layout of the other rams is obtained similarly.

10. Cut to layout of fifo

Louis The control block is implemented as a block of standard cells. The layout generation is again a recursive process. The structure is simply flattened until leaves carrying a layout annotation are reached: the general layout procedure is called to return the layout of the leaf.

These four blocks are then placed and routed. We now have the layout for the entire core of the circuit.

11. Back to MapCacheTop.sch

Louis The four sides composing the padframe are assembled by abutment. The last step is the assembly of the core with the pads.

12. zoom on Layout: PadFrame

Louis The layout operator invoked here is fairly complex. It is controlled by several explicit parameters such as the width of power buses. It is also controlled implicitly by the geometry of the schematics. For example it uses the relative position of the four sides in the schematic to place the sides similarly in the layout.

13. Cut to layout of inner

Louis Et voila!

14. Flip through

Rick You have seen how layout is specified by adding annotations to the source schematic. Since the source schematic can be parameterized, this is a graphical description for layout generators.

All layout operators have access to the graphical description of the source. The designer exerts control by drawing his source in a stylized manner specific to the layout operator.

Generating the layout of a circuit is a batch operation, in the sense that the final layout is produced by running a program on the source. This layout is never edited by hand. If the result is unsatisfactory, the source is updated, and the generation started all over.

15. Flip through

Rick Great confidence in the final mask results from

16. Flip through

Rick The strength of our framework is in its ability to mix a large number of layout styles together freely. Low-level assembly operators, such as abutment, provide the fine control necessary for full custom parts. At the other end of the spectrum, fully automatic operators, such as standard cells, reduce the amount of labor required for non-critical parts.