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CoreRouteDoc.tioga

Bertrand Serlet, September 21, 1987 5:34:23 pm PDT

Don Curry July 4, 1988 10:16:17 am PDT

Louis Monier September 6, 1987 8:51:21 pm PDT

CoreRoute

Integrated Routing

Bertrand Serlet

Abstract: CoreRoute allows interfacing purely geometric routers to the world of structure. CoreRoute does not route in itself but calls routers within the framework define by PWCore.

Created by: Bertrand Serlet, Louis Monier, Bryan Preas, Don Curry

Maintained by: Bertrand Serlet <Serlet.pa>, Louis Monier <Monier.pa>, Don Curry <Curry.pa>

Keywords: Router, PatchWork, PWCore, Tools Integration

XEROX Xerox Corporation
Palo Alto Research Center
3333 Coyote Hill Road
Palo Alto, California 94304

For Internal Xerox Use Only

0. Extensions, layer changes, power bussing : $Extend

Extend expects a RecordCell with one instance. The cellType properties $Bottom, $Right, $Top, $Left, specify the amount of extension, in l. If a property is absent, 0 is assumed.

Setting the cellType property ChangeLayers to a non-NIL value causes layer switching between Metal and Metal2 to occur.

Primarily in order to insure high quality power connections when doing ChangeLayers, Extend will do simple routing on all sides. The schematic pins are examined to determine whether bussed signals exist on a particular side and whether they exit at the high and/or low end of that side. This is indicated by the presence of pins on an adjacent side which are outside the projection of the sides of the subcell onto the parent (ie. in the corner).

The layout object returned is made up of the layout of the subcell surrounded by routing cells.

For $Extend, six properties may be placed on the schematic:

$Bottom: extension in lambda. defaults to 0.

$Right: extension in lambda. defaults to 0.

$Top: extension in lambda. defaults to 0.

$Left: extension in lambda. defaults to 0.

$VerticalMetal: ATOM or ROPE denoting a layer. If ambiguous, defaults to Metal2.

$ChangeLayers: ATOM or ROPE. Non NIL => TRUE. defaults to FALSE.

One property may be placed on the bussed schematic wires.

$w: a REF INT, specifies a larger than default trunk width.

Possible ERROR: Only one bused signal per side is possible when doing ChangeLayers.

1. Stack: $Stack and RawStack - One dimensional assembly.

Two layout atoms are registered for specifying a Stack:

$Stack derives layout information from schematic geometry with its attribute proc.

$RawStack assumes a record of type StackForm under the cellType property $StackForm.

The cellType must be either a stack in X or Y. This is determined by looking at the schematic geometry and checking that all cells overlap in X and not Y (by more than one line width) or vice versa.

The record cellType instances are reordered to reflect their order in the stack.

The layout geometry of schematic abutting subcells is examined to determine if the pins on their adjoining sides match exactly (wire, layer, size and spacings). An exact match means that the subcells may be abutted. The size the subcells' interest rectangle (either schematic or layout) at the abutting edge need not be the same.

A routing channel is included in the stack between each pair of non-abutting subcells as well as those subcell pairs which although schematically abutting, do not have matching layout interfaces. A routing channel will be put at the end of the stack if end wires are drawn such that they exit the side of the stack.

The layout size of the subcells is examined to determine what extensions, if any, are required to justify the sides.

Justify: $BestFit tries to position the cells on either side of a channel to (approximately) minimize the size of the channel. Use this mode with cells which could almost be abutted if it were not for some rogue signals requiring a channel.

If a subcell needs a side extension or makes up one side of a channel, the signals which get extended or routed are controlled by the schematic except that implicit globals (parent and subcell publics which do not appear is the schematic) are automatically included.

For $Stack, several properties may be placed on the schematic:

$VerticalMetal: ATOM or ROPE denoting a layer. ($Metal1 or $Metal2).

$FastRoute: when non-NIL implies a faster (possibly less compact) route.

$Justify: ATOM specifies $TopRight, $BottomLeft, $BestFit

$TotalLength: INT specifies overall desired length of stack (last channel is widened as rqd.)

$HorizontalStack, REF specifies when non-NIL a horizontal stack. This is used only in the degenerate case of a stack containing just one subcell. It essentially determines which ends of the subcell can have channel routes.

And one property may be placed on the schematic wires:

$w: a REF INT, specifies a larger than default channel trunk wire width.

2. Mosaic: $Mosaic - Two dimensional assembly.

Mosaic puts together two dimentional areas of abutting cells and can fill in notches and holes with switchboxes.

One layout atom is registered for specifying a Mosaic cell:

$Mosaic derives layout information from schematic geometry with its attribute proc.

Mosaic expects a record cell with two or more abutting instances. The layout object returned is made up of the layout of the subcells along with any switchboxes which are necessary to fill out the bounding rectangle. The abutted schematic subcells must loosely model the desired layout. Specifically, for each X or Y axis, monotonically increasing locations in the schmatic must correspond to monotonically increasing locations in the layout and the same schematic location (rounded down to 1 lambda grid) must correspond to the same layout location. Mosaic can not deal with channels so the size of all routing areas must be fixed by neighboring cells.

For $Mosaic, one property may be placed on the schematic:

$VerticalMetal: ATOM or ROPE denoting a layer. If ambiguous, defaults to Metal2.

One property may be placed on the bussed schematic wires.

$w: a REF INT, specifies a larger than default bus width.

3. Channel Routing: $ChannelRoute and $RawChannelRoute

OLD: Use Layout: $Stack instead

Uses as the engine Route.mesa.

Two layout atoms are registered for specifying Channels:

$RawChannelRoute: Assumes a record of type ChannelData under the $ChannelData property on the cellType;

$ChannelRoute: Calls an attribute proc that computes ChannelData from schematics decorations. Details of the parameter specification follows.

For $ChannelRoute, several properties can be found on the schematic, in order to specify parameters of the channel:

$Trunk: ATOM or ROPE denoting a layer. Defaults to Metal.

$Branch: ATOM or ROPE denoting a layer. Defaults to Metal2.

$Justify: ATOM specifies $TopRight, $BottomLeft

$DesignRules: ATOM specifies the design rules to use. Defaults to $cmosB.

$TotalWidth: REF INT specifies the total width of the channel, in lambdas. Defaults means minimum size channel.

And one property may be placed on the schematic wires:

$w: a REF INT, specifies a larger than default channel trunk wire width.

The schematic is also parsed to determine whether the channel should be horizontal or vertical, and the wires which have pins at the edge (perpendicular to the channel) and between the projections of the 2 instances will be routed out of the channel. Thoses wires can be structured, but then only atomic wires are taken into account.

4. ChangeLayers: $ChangeLayers and RawChangeLayers

OLD: Use Layout: $Extend with ChangeLayers: $yes instead

Current routers require that subcells have consistent vertical and horizontal layers. ChangeLayers can be used to provide this compatibility when rotation is not desired. The layout procedure includes the capability of generating a high quality power connections by bussing together power pins prior to the layer change.

Two layout atoms are registered for specifying a layer reversal cell:

$ChangeLayers derives layout information from schematic geometry with its attribute proc.

$RawChangeLayers assumes a record of type ChangeLayersForm under the cellType property $ChangeLayersForm.

ChangeLayers expects a record cell with one instance. The layout object returned is made up of the layout of the subcell surrounded by routing cells which change the routing layer between Metal and Metal2 and bus one signal per side (typically Vdd or Gnd) into one or two external pin(s) per side.

The schematic geometry of the cell is examined to determine which signals get translated on each side. Global signals (public signals not shown in the schematic) are translated wherever possible. The schematic geometry is also used to determine whether a bussed signal exists on a particular side and whether it exits at the high and/or low end of that side. This is indicated by the presence of a pin on the side of the parent which is outside the projection of that side of the subcell onto the parent.

For $ChangeLayers, one property may be placed on the schematic:

$VerticalMetal: ATOM or ROPE denoting a layer. If ambiguous, defaults to Metal2.

One property may be placed on the bussed schematic wires.

$w: a REF INT, specifies a larger than default bus width.

Possible ERROR: Large buses on adjacent sides which exit on adjacent ends (the same corner) may not be routable. Success depends on how much space is available beyond the last signal pin on the adjacent sides. In the current implementation, failure can occur even if the two busses are the same wire.

5. Model: $Model

Uses schematic as a model of a routing cell.

Uses a fixed channel format.

Expects schematic to be drawn in schematic mode (grid set at 2 lambda).

Expects cell size to be an even number of grid points in each dimention.

Expects channels positioned on odd grid points (spaced 2 grid points).

Layout wires are 4 lambda wide spaced 8 lambda center to center.

One property may be placed on the schematic:

$VerticalMetal: ATOM or ROPE denoting a layer. If ambiguous, defaults to Metal2.