DIRECTORY Core, RefTab;CoreOps: CEDAR DEFINITIONS = BEGIN OPEN Core;nameProp: ATOM;SetClassPrintProc: PROC [class: CellClass, proc: PrintClassProc] RETURNS [sameClass: CellClass];PrintClassProc: TYPE = PROC [data: REF ANY, out: STREAM, indent: NAT _ 0, level: NAT _ 2];CreateCellType: PROC [class: CellClass, public: WireSeq, data: REF ANY _ NIL, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [cellType: CellType];SetCellTypeName: PROC [cellType: CellType, name: ROPE] RETURNS [sameCellType: CellType];GetCellTypeName: PROC [cellType: CellType] RETURNS [name: ROPE];InheritCellTypeName: PROC [cellType: CellType] RETURNS [name: ROPE];Recast: PROC [me: CellType, fillCacheIfEmpty: BOOL _ TRUE] RETURNS [new: CellType];RecastBindingTable: PROC [cellType: CellType] RETURNS [table: RefTab.Ref];ToBasic: PROC [cellType: Core.CellType] RETURNS [basic: Core.CellType];PrintCellType: PROC [cellType: CellType, out: STREAM _ NIL, indent: NAT _ 0, level: NAT _ 2];PrintIndent: PROC [indent: NAT, out: STREAM, cr: BOOL _ TRUE];CreateWire: PROC [elements: Wires _ NIL, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [wire: Wire];CreateWires: PROC [size: NAT, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [wire: Wire];SubrangeWire: PROC [wire: Wire, start, size: NAT, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [sub: Wire];CopyWire: PROC [wire: Wire] RETURNS [new: Wire]; CopyWireUsingTable: PROC [old: Wire, oldToNew: RefTab.Ref, copyName: BOOL _ TRUE] RETURNS [new: Wire]; UnionWire: PROC [wire1, wire2: Wire, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [union: Wire];EachWireProc: TYPE = PROC [wire: Wire] RETURNS [subWires: BOOL _ TRUE, quit: BOOL _ FALSE];EachWirePairProc: TYPE = PROC [actualWire, publicWire: Wire] RETURNS [subWires: BOOL _ TRUE, quit: BOOL _ FALSE];VisitWire: PROC [wire: Wire, eachWire: EachWireProc] RETURNS [quit: BOOL];VisitWireSeq: PROC [seq: WireSeq, eachWire: EachWireProc] RETURNS [quit: BOOL];VisitRootAtomics: PROC [root: WireSeq, eachWire: PROC [Wire]];VisitBinding: PROC [actual, public: Wire, eachWirePair: EachWirePairProc] RETURNS [quit: BOOL]; VisitBindingSeq: PROC [actual, public: WireSeq, eachWirePair: EachWirePairProc] RETURNS [quit: BOOL];Conform: PROC [actual, public: Wire] RETURNS [BOOL];CorrectConform: PROC [actual, public: WireSeq] RETURNS [BOOL];WireBits: PROC [wire: Wire] RETURNS [bits: NAT];WireSeqBits: PROC [seq: WireSeq] RETURNS [bits: NAT];CreateBindingTable: PROC [wire1, wire2: Wire] RETURNS [table: RefTab.Ref];SetShortWireName: PROC [wire: Wire, name: ROPE] RETURNS [sameWire: Wire];GetShortWireName: PROC [wire: Wire] RETURNS [name: ROPE];GetWireIndex: PROC [wire: Wire, name: ROPE] RETURNS [n: INT _ -1];GetFullWireNames: PROC [root: WireSeq, wire: Wire] RETURNS [names: LIST OF ROPE];GetFullWireName: PROC [root: WireSeq, wire: Wire] RETURNS [name: ROPE];IsFullWireName: PROC [root: WireSeq, wire: Wire, name: ROPE] RETURNS [BOOL];FindWire: PROC [root: WireSeq, name: ROPE] RETURNS [wire: Wire _ NIL];ParseWireName: PROC [name: ROPE] RETURNS [base: ROPE, components: LIST OF ROPE _ NIL];PrintWire: PROC [wire: Wire, out: STREAM _ NIL, indent: NAT _ 0, level: NAT _ 2];FlushNameCaches: PROC [root: WireSeq];Reverse: PROC [wires: Wires] RETURNS [revWires: Wires _ NIL];Delete: PROC [wires: Wires, wire: Wire] RETURNS [newWires: Wires _ NIL];Member: PROC [wires: Wires, wire: Wire] RETURNS [BOOL];ParentWires: PROC [root, candidate: Wire] RETURNS [parents: LIST OF Wire _ NIL];RecursiveMember: PROC [wire, candidate: Wire] RETURNS [BOOL];Index: PROC [rope: ROPE, index: NAT] RETURNS [indexed: ROPE];FixStupidRef: PROC [ref: REF ANY] RETURNS [rope: ROPE];RopeDammit: PROC [ref: ROPE] RETURNS [rope: ROPE]= INLINE {rope _ ref};Print: PROC [ref: REF, out: STREAM _ NIL, indent: NAT _ 0, level: NAT _ 2];END.   Д  CoreOps.mesa	Copyright ╙ 1985, 1986, 1987 by Xerox Corporation.  All rights reserved.Barth, October 31, 1986 9:44:19 am PSTBertrand Serlet, June 4, 1987 1:23:12 pm PDTSpreitzer, April 8, 1986 4:29:54 pm PSTLouis Monier, May 1, 1986 4:43:54 pm PDTPradeep Sindhu, February 7, 1986 3:20:36 pm PSTMike Spreitzer February 27, 1987 2:35:34 pm PSTLast tweaked by Mike Spreitzer on November 2, 1987 3:39:45 pm PSTTheoryThis interface defines interesting utilities for the data structure defined in Core.PropertyThis atom is used by various types (wires, cellTypes, ...) to define a name (of type ROPE).Cell ClassesCell Typesname, if non NIL, has precedence over props.Convenience for CoreProperties.PutCellTypeProp[cellType, nameProp, name].Convenience for CoreProperties.GetCellTypeProp[cellType, nameProp].Looks for name on cellType. If not found and cellType.class.layersProps=TRUE then recasts and tries again.  Keeps trying until found or cellType.class.layersProps=FALSE.Returns the same pointer given the same cell type if fillCacheIfEmpty=TRUE.  See the theory in Core.Mesa.  IF fillCacheIfEmpty=FALSE then the recast cache is unchanged.Assumes it can call Recast[cellType]. table contains publics of cellType as keys and corresponding publics of Recast[cellType] as values.Recasts as much as possible.Wire Creationname, if non NIL, has precedence over props.name, if non NIL, has precedence over props.name, if non NIL, has precedence over props.Simple copy of a wire.  Respects DAGness.Only the name property is copied.Fancy copy of a wire.  Respects DAGness.Table oldToNew maps old wires to new wires.  As old DAG is visited, pairs are added into oldToNew.If copyName, the name property is the only property copied, otherwise no property is copied.Creates a new structured wire of size wire1.size+wire2.size, with corresponding name and properties.name, if non NIL, has precedence over props.Wire EnumerationReturns quit iff eachWire did.Visits the wire as a tree: each subwire reachable n ways is reached each of those n ways.  Calls VisitWire on each element of the seq.Short for previous function, when only atomic wires should be enumerated, and when the quit argument is not needed.Visits the wire as a tree: each subwire reachable n ways is reached each of those n ways.  Visits two wires as trees in parallel.  Aborts visit and returns quit=TRUE iff eachWirePair returns quit=TRUE or differing structure (viewed as trees) found.Calls VisitBinding on each element of the two sequences.Works only for trees, not DAGs; checks that they have the same structure.Works for DAGs, not just trees.Computes the number of atomic wires reachable from wire.Guess what this does!Assumes that wire1 and wire2 conform.table contains parts of wire1 as keys and corresponding parts of wire2 as values.Wire NamingWires have attached 2 kinds of names: short names (at most one per wire) and full names, which are relative to a root wire (such as public or internal), and which are a list of ROPE since we have DAGs.If wire is not atomic, and wire[i] has short name "name" , then returns "i"; -1 if not found.Appends .name if a short name is on the wire otherwise appends [index].  Should only be called with root DAGs, e.g. a public wire.  Full path names relative to the root DAG are cached (property on the root).  A NIL list of names means that wire is not part of root or that wire is root and has no short name. Will return a random name amongst all the possible names obtained with GetFullWireNames, but consistently always the same one.Will return NIL when called with a wire that has no full name.Should only be called with root DAGs, e.g. a public wire.  Fetches a wire part of root with full name name.  NIL is returned if no wire is found.Breaks apart a wire name into its components.  Eg., given the name "foo.mumble[3].bar", base is "foo", and components is LIST["mumble", "3", "bar"]. Various caches are stored on roots, and this function gets rid of them.Wires OperationsSearches for wire in the list wires.Searches for the direct parents of candidate starting at root.Implementation is slow, but allows easier interactive debugging.Searches for candidate in the structured wire wire.MiscellaneousCreates a name of the form rope[index], with some degree of efficiency.Converts a rope or ref text into a rope.Stupid compiler.Works on NIL, Wire, Wires and CellType.  User convenience only.Э╩╕  Ш Ц"Cedar" styleЪЬЩJЪЬHЩHJЩ&IcodeЩ,KЩ'KЩ(KЩ/KЩ/KЩAЧJШ Ъ╧k	ЬШJШ ЧJЪ
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