DIRECTORY Core, CoreClasses; CoreCreate: CEDAR DEFINITIONS = BEGIN CellType: TYPE = Core.CellType; Properties: TYPE = Core.Properties; ROPE: TYPE = Core.ROPE; Wire: TYPE = Core.Wire; WireSeq: TYPE = Core.WireSeq; CellInstances: TYPE = CoreClasses.CellInstances; CellInstance: TYPE = CoreClasses.CellInstance; TransistorType: TYPE = CoreClasses.TransistorType; WR: TYPE = REF _ NIL; WireList: PROC [wrs: LIST OF WR _ NIL, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [Wire]; Wires: PROC [wr1, wr2, wr3, wr4, wr5, wr6, wr7, wr8, wr9, wr10, wr11, wr12, wr13: WR _ NIL, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [Wire]; Seq: PROC [name: ROPE _ NIL, size: NAT, protoChild: Wire _ NIL] RETURNS [Wire]; Index: PROC [wr: WR, index: NAT] RETURNS [WR]; Range: PROC [wire: Wire, start, size: NAT, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [Wire]; Union: PROC [wr1, wr2, wr3, wr4, wr5, wr6, wr7, wr8, wr9, wr10, wr11, wr12, wr13: Wire _ NIL, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [Wire]; FindWire: PROC [root: WireSeq, wr: WR] RETURNS [Wire]; PA: TYPE = RECORD [public, actual: WR]; Instance: PROC [type: CellType, pa1, pa2, pa3, pa4, pa5, pa6, pa7, pa8, pa9, pa10, pa11, pa12, pa13: PA _ [], name: ROPE _ NIL, props: Properties _ NIL] RETURNS [CellInstance]; InstanceList: PROC [type: CellType, pas: LIST OF PA _ NIL, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [CellInstance]; Cell: PROC [public: WireSeq, onlyInternal, internal: WireSeq _ NIL, instances: CellInstances, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [CellType]; Transistor: PROC [type: TransistorType _ nE, length: NAT _ 2, width: NAT _ 4, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [CellType]; SequenceCell: PROC [baseCell: CellType, count: NAT, sequencePorts: WireSeq _ NIL, flatSequencePorts: WireSeq _ NIL, stitchPorts: LIST OF PA _ NIL, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [CellType]; END. XCoreCreate.mesa Copyright س 1985, 1986, 1987 by Xerox Corporation. All rights reserved. Bertrand Serlet, March 28, 1987 11:10:06 pm PST Barth, February 17, 1987 5:41:04 pm PST Louis Monier March 12, 1986 9:59:34 am PST Mike Spreitzer November 18, 1986 2:39:16 pm PST Theory This interface provides syntactic sugar to help create Core data structures while retaining the ability to have handles on the real Core objects. Types Wires WR is the union of the types Wire and ROPE, for user convenience. Basic constructor for creating a structured wire. Each element of wrs must be of type Wire or ROPE. Same as WireList but with more sugar. Each wr must be of type Wire or ROPE. Creates a wire with size children. protoChild#NIL => CoreOps.CopyWire is used to make children. Extractor for extracting a wire from a sequence. If the argument is a Wire then the element is extracted. If the argument is a ROPE, the suffix "[index]" is added to it. wr must be of type Wire or ROPE. Extractor for extracting a group of wires from a sequence. Elements are extracted and grouped together. The argument must be of type Wire only. Creates flat union of arguments. Looks into root to find wr. Root should usually be a public or an internal. Cells Records a binding. Creates a CoreClasses.RecordCell. If internal=NIL then internal _ Union[public, onlyInternal]. If internal#NIL then onlyInternal is discarded. Creates a CoreClasses.Transistor. Creates a CoreClasses.SequenceCellType. stitchPorts are not (public, actual) pairs but rather pairs of publics which should be bound together upon sequencing. ‌ت‌کcodeڑœ™KڑœH™HKڑœ/™/Kڑœ$دk™'Kڑœ'‌™*Kڑœ,‌™/—K™ڑ‌ œکKک—Kڑدn œ‌œ‌œ‌ک%head™Ibodyڑœ‘™‘—™Kڑœ ‌œکKڑœ‌œک#Kڑ‌œ‌œ‌œکKڑœ‌œ کKڑœ ‌œکKڑœ‌œک0Kڑœ‌œک.Kڑœ‌œک2—™ڑ‌œ‌œ‌œ‌œکKڑ‌œ$‌œ™CK™—ڑ‍œ‌œ‌œ‌œ‌œ‌œ‌œ‌œ‌œ‌œکaKڑœ_‌œ™dK™—ڑ‍œ‌œG‌œ‌œ‌œ‌œ‌œ‌œک–KڑœG‌œ™LK™—ڑ‍œ‌œ‌œ‌œ‌œ‌œ‌œکOKڑœ/‌œ/™aK™—ڑ‍œ‌œ‌œ ‌œ‌œ‌œک.Kڑœپ‌œC‌œ™حK™—ڑ‍œ‌œ‌œ‌œ‌œ‌œ‌œکeKڑœ‘™‘K™—ڑ‍œ‌œN‌œ‌œ‌œ‌œ‌œککK™ K™—ڑ‍œ‌œ‌œ‌œک6KڑœL™LK™——™ڑ‌œ‌œ‌œ‌œک'K™K™—ڑ‍œ‌œW‌œ ‌œ‌œ‌œ‌œک°K™—ڑ‍œ‌œ‌œ‌œ‌œ‌œ‌œ‌œ‌œ‌œک}K™—ڑ‍œ‌œ5‌œ"‌œ‌œ‌œ‌œکœKڑœ"™"Kڑœ‌œ-™<ڑœ‌œ ™/K™——ڑ‍ œ‌œ%‌œ ‌œ‌œ‌œ‌œ‌œکŒKڑœ!™!K™—ڑ‍œ‌œ‌œ‌œ‌œ‌œ‌œ‌œ‌œ‌œ‌œ‌œ‌œکرKڑœ ™ K™——Kڑ‌œک—…—†{