<> <> <> <> <> <> <<>> DIRECTORY Core, CoreClasses; CoreCreate: CEDAR DEFINITIONS = BEGIN <> <> <> CellType: TYPE = Core.CellType; Properties: TYPE = Core.Properties; ROPE: TYPE = Core.ROPE; Wire: TYPE = Core.Wire; WireSeq: TYPE = Core.WireSeq; CellInstances: TYPE = CoreClasses.CellInstances; CellInstance: TYPE = CoreClasses.CellInstance; TransistorType: TYPE = CoreClasses.TransistorType; <> WR: TYPE = REF _ NIL; <> <<>> WireList: PROC [wrs: LIST OF WR _ NIL, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [Wire]; <> <<>> Wires: PROC [wr1, wr2, wr3, wr4, wr5, wr6, wr7, wr8, wr9, wr10, wr11, wr12, wr13: WR _ NIL, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [Wire]; <> <<>> Seq: PROC [name: ROPE _ NIL, size: NAT, protoChild: Wire _ NIL] RETURNS [Wire]; < CoreOps.CopyWire is used to make children. >> <<>> Index: PROC [wr: WR, index: NAT] RETURNS [WR]; <> <<>> Range: PROC [wire: Wire, start, size: NAT, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [Wire]; <> <<>> Union: PROC [wr1, wr2, wr3, wr4, wr5, wr6, wr7, wr8, wr9, wr10, wr11, wr12, wr13: Wire _ NIL, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [Wire]; <> <<>> FindWire: PROC [root: WireSeq, wr: WR] RETURNS [Wire]; <> <<>> <> PA: TYPE = RECORD [public, actual: WR]; <> <<>> Instance: PROC [type: CellType, pa1, pa2, pa3, pa4, pa5, pa6, pa7, pa8, pa9, pa10, pa11, pa12, pa13: PA _ [], name: ROPE _ NIL, props: Properties _ NIL] RETURNS [CellInstance]; <<>> InstanceList: PROC [type: CellType, pas: LIST OF PA _ NIL, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [CellInstance]; <<>> Cell: PROC [public: WireSeq, onlyInternal, internal: WireSeq _ NIL, instances: CellInstances, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [CellType]; <> <> <> <<>> Transistor: PROC [type: TransistorType _ nE, length: NAT _ 2, width: NAT _ 4, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [CellType]; <> <<>> SequenceCell: PROC [baseCell: CellType, count: NAT, sequencePorts: WireSeq _ NIL, flatSequencePorts: WireSeq _ NIL, stitchPorts: LIST OF PA _ NIL, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [CellType]; <> <<>> END.