CoreCreate.mesa
Copyright Ó 1985, 1986, 1987 by Xerox Corporation. All rights reserved.
Bertrand Serlet, March 28, 1987 11:10:06 pm PST
Barth, February 17, 1987 5:41:04 pm PST
Louis Monier March 12, 1986 9:59:34 am PST
Mike Spreitzer November 18, 1986 2:39:16 pm PST
DIRECTORY Core, CoreClasses;
CoreCreate: CEDAR DEFINITIONS = BEGIN
Theory
This interface provides syntactic sugar to help create Core data structures while retaining the ability to have handles on the real Core objects.
Types
CellType: TYPE = Core.CellType;
Properties: TYPE = Core.Properties;
ROPE: TYPE = Core.ROPE;
Wire: TYPE = Core.Wire;
WireSeq: TYPE = Core.WireSeq;
CellInstances: TYPE = CoreClasses.CellInstances;
CellInstance: TYPE = CoreClasses.CellInstance;
TransistorType: TYPE = CoreClasses.TransistorType;
Wires
WR: TYPE = REFNIL;
WR is the union of the types Wire and ROPE, for user convenience.
WireList: PROC [wrs: LIST OF WRNIL, name: ROPENIL, props: Properties ← NIL] RETURNS [Wire];
Basic constructor for creating a structured wire. Each element of wrs must be of type Wire or ROPE.
Wires: PROC [wr1, wr2, wr3, wr4, wr5, wr6, wr7, wr8, wr9, wr10, wr11, wr12, wr13: WRNIL, name: ROPENIL, props: Properties ← NIL] RETURNS [Wire];
Same as WireList but with more sugar. Each wr must be of type Wire or ROPE.
Seq: PROC [name: ROPENIL, size: NAT, protoChild: Wire ← NIL] RETURNS [Wire];
Creates a wire with size children. protoChild#NIL => CoreOps.CopyWire is used to make children.
Index: PROC [wr: WR, index: NAT] RETURNS [WR];
Extractor for extracting a wire from a sequence. If the argument is a Wire then the element is extracted. If the argument is a ROPE, the suffix "[index]" is added to it. wr must be of type Wire or ROPE.
Range: PROC [wire: Wire, start, size: NAT, name: ROPENIL, props: Properties ← NIL] RETURNS [Wire];
Extractor for extracting a group of wires from a sequence. Elements are extracted and grouped together. The argument must be of type Wire only.
Union: PROC [wr1, wr2, wr3, wr4, wr5, wr6, wr7, wr8, wr9, wr10, wr11, wr12, wr13: Wire ← NIL, name: ROPENIL, props: Properties ← NIL] RETURNS [Wire];
Creates flat union of arguments.
FindWire: PROC [root: WireSeq, wr: WR] RETURNS [Wire];
Looks into root to find wr. Root should usually be a public or an internal.
Cells
PA: TYPE = RECORD [public, actual: WR];
Records a binding.
Instance: PROC [type: CellType, pa1, pa2, pa3, pa4, pa5, pa6, pa7, pa8, pa9, pa10, pa11, pa12, pa13: PA ← [], name: ROPENIL, props: Properties ← NIL] RETURNS [CellInstance];
InstanceList: PROC [type: CellType, pas: LIST OF PANIL, name: ROPENIL, props: Properties ← NIL] RETURNS [CellInstance];
Cell: PROC [public: WireSeq, onlyInternal, internal: WireSeq ← NIL, instances: CellInstances, name: ROPENIL, props: Properties ← NIL] RETURNS [CellType];
Creates a CoreClasses.RecordCell.
If internal=NIL then internal ← Union[public, onlyInternal].
If internal#NIL then onlyInternal is discarded.
Transistor: PROC [type: TransistorType ← nE, length: NAT ← 2, width: NAT ← 4, name: ROPENIL, props: Properties ← NIL] RETURNS [CellType];
Creates a CoreClasses.Transistor.
SequenceCell: PROC [baseCell: CellType, count: NAT, sequencePorts: WireSeq ← NIL, flatSequencePorts: WireSeq ← NIL, stitchPorts: LIST OF PANIL, name: ROPENIL, props: Properties ← NIL] RETURNS [CellType];
Creates a CoreClasses.SequenceCellType. stitchPorts are not (public, actual) pairs but rather pairs of publics which should be bound together upon sequencing.
END.