<> <> <> <> <> <> <> DIRECTORY Core, RefTab; CoreClasses: CEDAR DEFINITIONS = BEGIN OPEN Core; <> <> <> <> <> <<1) The actual wire sequence of an instance must conform to the public wire sequence of the cell type which is being instantiated. An actual wire may converge more than a public wire and still be considered to conform. This allows more than one wire of a public to be attached to the same actual.>> <<2) The actual wire sequence record may not be shared with anything else. Every actual wire must reachable from the containing cell type's internal wire sequence.>> <<3) The public wire sequence record may not be shared with anything else. Every public wire must be reachable from the cell type's internal wire sequence.>> <<4) The internal wire sequence record may not be shared with anything else. An internal wire must be treated as immutable once it is part of a record cell because of the CoreOps naming strategy. So must the internal wire sequence.>> <<5) Cell types may not share any part of any internal wire. >> recordCellClass: CellClass; RecordCellType: TYPE = REF RecordCellTypeRec; RecordCellTypeRec: TYPE = RECORD [ internal: WireSeq, instances: SEQUENCE size: NAT OF CellInstance]; < empty internal>> <> CellInstance: TYPE = REF CellInstanceRec; CellInstanceRec: TYPE = RECORD [ actual: WireSeq, type: CellType, properties: Properties _ NIL]; < empty actual>> CellInstances: TYPE = LIST OF CellInstance; CreateRecordCell: PROC [public: WireSeq, internal: WireSeq, instances: LIST OF CellInstance, name: ROPE _ NIL, props: Properties _ NIL, giveNames: BOOL _ FALSE] RETURNS [recordCell: CellType]; <> <> <> CreateInstance: PROC [actual: WireSeq, type: CellType, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [instance: CellInstance]; <> SetCellInstanceName: PROC [instance: CellInstance, name: ROPE] RETURNS [sameInstance: CellInstance]; GetCellInstanceName: PROC [instance: CellInstance] RETURNS [name: ROPE]; CorrespondingActual: PROC [instance: CellInstance, public: Wire] RETURNS [actual: Wire _ NIL]; <> CreatePermutedRecordCell: PROC [iconPublic: WireSeq, schCell: CellType, table: RefTab.Ref, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [recordCell: CellType]; <> <> <> <> ReverseCellInstances: PROC [instances: CellInstances] RETURNS [rev: CellInstances _ NIL]; <> <<>> InstanceIndex: PROC [recordCell: CellType, instance: CellInstance] RETURNS [index: INT _ -1]; <> <<-1 is returned if no such instance is found.>> <> transistorCellClass: CellClass; Transistor: TYPE = REF TransistorRec; TransistorRec: TYPE = RECORD [ type: TransistorType _ nE, length: NAT _ 2, width: NAT _ 4]; -- these units are in lambda but new code should not depend on these values since this is all obviously bullshit. TransistorType: TYPE = {nE, pE, nD}; TransistorPort: TYPE = MACHINE DEPENDENT {gate(0), ch1(1), ch2(2), Vdd(3)}; transistorTypeNames: ARRAY TransistorType OF ROPE; transistorPortNames: ARRAY TransistorPort OF ROPE; CreateTransistor: PROC [args: TransistorRec, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [transistor: CellType]; <> <> <> <> <> unspecifiedCellClass: CellClass; CreateUnspecified: PROC [public: WireSeq, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [cellType: CellType]; <> <> <> sequenceCellClass: CellClass; SequenceCellType: TYPE = REF SequenceCellTypeRec; SequenceCellTypeRec: TYPE = RECORD [ base: CellType, count: NAT, sequence: SequenceSet _ NIL, flatSequence: SequenceSet _ NIL, stitch: StitchSet _ NIL]; SequenceSet: TYPE = REF SequenceSetRec; SequenceSetRec: TYPE = RECORD [set: SEQUENCE length: NAT OF NAT]; StitchSet: TYPE = REF StitchSetRec; StitchSetRec: TYPE = RECORD [set: SEQUENCE length: NAT OF Stitch]; Stitch: TYPE = RECORD [this, that: NAT]; <> CreateSequence: PROC [args: SequenceCellType, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [cellType: CellType]; <> <<>> END.