The pad library is DynaBusPads.dale from CellLibraries.df. Its documentation, the document you are reading, is also included in CellLibraries.df.

You will also find in DynabusExampleCircuit.dale, from /Indigo/Dragon7.0/Top/DynaBus.df, an example of pad frame construction for a typical "Dynabus circuit". It shows four standard sides and a fake inner cell. All standard pads are already specified: Dynabus, DBus, clocks. Please preserve the public names and the location of these pads, even if you don't use them. You should import the large schematics, expand it (the cell will explode, but all pads will remain imports), and use it to build your top level schematics: substitute your inner cell and customize the remining pads. The names of the wires inside the pad frame are only here for convenience, you may modify them if you want to match names in your inner cell.

Pads should be imported and should not be edited. This is a clear case were standardization is a plus and unnecessary customization a nuisance.

A standard probe card will (hopefully) be designed that will probe the 268 possible pad positions. For that reason, all the pad locations must contain a pad, even if unused in that particular chip. All issues concerning the test of these circuits have not been resolved yet, so just stay tuned.

The PGA has an inside ring of signal tabs and an outside ring of large power tabs. There are 67 signal tabs on a 250m pitch per side (total 268). Each side has 8 power tabs, alternating between power and ground. The corners power tabs are truncated. The cavity is 17.75mm, or large enough to accomodate any circuit we can currently dream of. For too small a chip, long bonding wires might actually be a problem. The pad frame tries to mirror the arrangment of power and signal pads to simplify bonding.

The pad opening is 100m (4 mils). The pad pitch is 180m (7 mils) per pad. This creates a cavity of 12.060mm for the inner. Adding twice the pad height (~700m per pad) leads to a square chip of ~13.46mm on a side. The pad width is now fixed, but the height may still vary slightly.

Pentronix and most bonding houses in the Valley (but not VTI) can accomodate 7 mils pitch and 4 mils opening. Probes are also no problem with these dimensions (BIC used the same numbers).

The pad is the combination of a tristate driver in output and a TTL-level buffer in input. The input buffer is TTL compatible (think about tester, TTL chips). The pins are:

The last stage of drivers can deliver about 50mA under 5V. It drives a 40pF load in a couple of ns. The drains of the n transistor (w=500m) and of the p transistor (w=1100m) are protected by guard rings and act as clamping diodes. In an experiment on a similar actual circuit, spikes of up to 1000V (from a 100pF capacitor through 2kW) did not disturb the circuit. Each pad receives power from the outside power bus (the double decker) and passes some of it to the inside of the circuit.

By tying the various enables to Vdd or Gnd, the pad can be used as I/O, output only, input only, input tristate, ....

The following other pads are provided for user convenience. They are derived trivially from the I/O pad by omitting or fixing some of the public wires.

Power pads are located on the periphery of the die, and match the power fingers on the package. Notice that a wire goes through them: think of it as the projection of the bonding wire coming from the corresponding signal pad. This wire is here to keep the DA system sane, and will not appear on the masks.

There is a Vdd pad, a Gnd pad, and an empty pad needed to space areas of Vdd and Gnd. The pattern for the top row is: 3 Vdd, 1 Empty, (9 Gnd, 1 Empty, 9 Vdd, 1 Empty)3, 3 Gnd.

Sides are obtained through rotation, not symetry. If you copy the standard pad frame, you don't have to manipulate explicitely these pads.

Let's picture a worst case chip by making the following hypothesis:

Justifications: (1) the IOBridge is the largest SC block we have placed, and combinatorial logic switches in successive waves, producing smaller spikes; (2) and (3) result from elementary remarks about cell sizes and die size. So, we can reduce the problem to half a row, holding 15 flops, powered through a 5mm long by 10m wide metal1 line. Since metal has a resistivity of 30mW/¡, its resistance is 15W.

Voltage drop: A SPICE simulation has shown that a switching flop produces a spike of 2.2mA and we can suppose that at worst, all flops switch simultaneously. The resulting spike of 33mA will produce a voltage drop of 495mV. This is a worst case, ignoring any inductance or capacitance of wire, which will no doubt round those spikes.

Current density: Assuming a 20MHz clock rate, the average current through one flop is about 0.088mA; the half-row will thus need 1.32mA of current. The 10m line could handle up to 5mA DC.

Dynamic power: Measuring the total capacitance of all nodes in a circuit (IOB) leads to a value of 5.5nF; assuming a 20MHz clock and an equal distribution between up and down-going nodes, the average intensity comes up to 1/2 * 5.5nF * 5V / 50ns = 275mA and the power dissipation to 1.4W. This figures lead to 275mA average current for the inner of the chip: it takes 100m of metal2 or 200m of metal1 to provide this current. Divided among 268 pads, this leads to a current of 1mA per pad.

We build a model of a typical load on the wire wrapped machine. In the region we plan to use the circuits (2ns rise time), the load is equivalent to a 0.123mH inductor followed by a 40pF capacitor to ground. Spice simulations show a peak current of 50mA lasting 6ns; at 40MHz, that is 6mA average current.

By design, the power bus might have to provide power to as much as 5 pads, (plus a fraction of the inner power, negligible in practice). that is 250mA peak, 30mA average.

Unless absolutely necessary, please keep the position of pads specified in the example. Even if you don't know why now, one day this standardization will buy you something.

All input signals must go from the input buffer of the pad to a flop: no logic in between. Similarly, all output signals must go directly from a flop to the output driver of the pad. Notice that the following signals are enabled by grant: DataOut, SpareOut, ParityOut, HeaderOut. Other output signals are always driven.

The clock is input through a regular input pad (using the pad pin, not the buffered version), and amplified through two buffers distributed throughout the standard cell blocks. This ensures that the clock is generated where it is needed, and the size of the buffers is tailored for each chip. The amplified clock is then output through a simple metal wire to be sampled inside the BIC. Actual zapping tests showed that ESD-induced latchup was not an issue. No extra buffer can be inserted in this path, or the skew control mechanism will fail.

Assuming a 40pF load on the clock, the buffers have standard cell drives of 14 and 56. Mint can be used to estimate the load on the clock line. For memory, the load on a SC flop is 58fF.

Grant is input through a regular input pad and latched. The nQ output of the flop goes through 3 buffers (drive=2, 8, 32) and is distributed to the pads. The delay from rising edge of clock to data valid on bus was found to be about 8ns.

If it becomes necessary to save probes, one can use the output side of an input-only pad (say X) for testing an output only signal (say Y). Y is connected to the dataOut pin of X and a global "test" signal to the enableOut, so the X pad is used as a bidirectional pad, and the Y pad is not probed. This saves probes, but not tester resources, at least on the present tester. Let's hope that we wan't have to go to such extremities to test!