<> <> <> <> <> DIRECTORY DABasics, CD, Connections, RefTab, Rope, Route; Cabbage: CEDAR DEFINITIONS = BEGIN <> <> <> <> <> <> <> <<1. Currently, it is a client requirement to place the interior object so that projections of its edges do not intersect pins on the bonding pad sides. This will be relaxed in future versions.>> <<2. Currently wire widths specifications from Connections are transformed to net names. This means that there can be only one wire width per net name. This will be relaxed when Connections is moved into Route.>> <<3. Incomplete routing may occur if the switchbox areas (the corners) are too small or too congested in a part of the switchbox. Automatic recovery is planned but not implemented.>> <<4. The portions of the left and right bonding pad sides that are routed with switchboxes can have only one net per portion. Also, these portions must have "sparse" connections: spacing should be much greater than the minimum pin-to-pin spacing .>> <> Error: ERROR [errorType: ErrorType _ callingError, explanation: Rope.ROPE _ NIL]; Signal: SIGNAL [errorType: ErrorType _ callingError, explanation: Rope.ROPE _ NIL]; ErrorType: TYPE = {programmingError, callingError, noResource, designRuleViolation, other}; <> <<-- All the parameters for the channel and switchbox router>> PadRingParams: TYPE = REF PadRingParamsRec; PadRingParamsRec: TYPE = RECORD [ horizLayer: Rope.ROPE, -- "poly", "metal" or "metal2" vertLayer: Rope.ROPE, -- "poly", "metal" or "metal2" technologyKey: ATOM _ $cmosB, -- $cmosA or $cmosB wireWidthProc: Cabbage.WireWidthProc _ NIL, -- to control the width of a trunk wire outerBTChanWidth, outerLRChanWidth: INT _ 32, -- width of channel at periphery in lambdas powerBTCellWidth, powerLRCellWidth: INT _ 200, -- width of power at periphery in lambdas opt: Route.Optimization _ full, -- controls runtime vs quality signalSinglePinNets: BOOLEAN _ TRUE -- SIGNAL if there are any single pin nets ]; <> defaultPadRingParams: PadRingParams; WireWidthProc: TYPE = PROC[netName: Rope.ROPE, context: REF ANY _ NIL] RETURNS [wireWidth: INT]; <> <> <> Center: PROC [inner, bottomLeft, bottom, bottomRight, right, topRight, top, topLeft, left: CD.Object, parms: Cabbage.PadRingParams] RETURNS [innerPos: CD.Position]; <> MakeInner: PROC [oldInner: CD.Object, connections: Connections.Table, parms: PadRingParams] RETURNS [inner: CD.Object]; <<>> <> MakeOuter: PROC [oldOuter: CD.Object, side: DABasics.Side, connections: Connections.Table, parms: PadRingParams] RETURNS [outer: CD.Object]; <> <> <<>> <> <> <> <> <> <> <<>> <> <<>> PadRoute: PROC [inner, bottomLeft, bottom, bottomRight, right, topRight, top, topLeft, left: CD.Object, innerPos: CD.Position, connections: Connections.Table, parms: PadRingParams _ defaultPadRingParams, name: Rope.ROPE _ NIL] RETURNS [chip: CD.Object]; PadLimitedRoute: PROC [inner, bottomLeft, bottom, bottomRight, right, topRight, top, topLeft, left: CD.Object, innerPos: CD.Position, connections: Connections.Table, parms: PadRingParams _ defaultPadRingParams, name: Rope.ROPE _ NIL] RETURNS [chip: CD.Object]; END.