Create:
PROC
RETURNS [cellType: Core.CellType] = {
inputs: BooleCore.Inputs ← NIL;
outputs: BooleCore.Outputs ← NIL;
wa: Core.Wire = CoreOps.CreateWire[name: "A"];
wb: Core.Wire = CoreOps.CreateWire[name: "B"];
wc: Core.Wire = CoreOps.CreateWire[name: "C"];
inv: Core.CellType ← BooleCore.GetCellLibraryCell["InputDriver"];
out: Core.CellType ← BooleCore.GetCellLibraryCell["OutputDriver"];
pas: LIST OF CoreCreate.PA ← LIST[["VRef", "VRef"]];
inputs ← CONS [[input: "A", driver: inv], inputs];
inputs ← CONS [[input: "B", driver: inv], inputs];
inputs ← CONS [[input: "C", driver: inv], inputs];
outputs ← CONS [[output: "Z1", driver: out, expr: wa, pas: pas], outputs];
outputs ← CONS [[output: "Z2", driver: out, expr: Or[wa, And[Not[wa], Not[wb], wc]], pas: pas], outputs];
outputs ← CONS [[output: "Z3", driver: out, expr: And[Not[wb], Not[wc]], pas: pas], outputs];
outputs ← CONS [[output: "Z4", driver: out, expr: Or[And[Not[wa], Not[wb], wc], And[Not[wa], wb, Not[wc]]], pas: pas], outputs];
-- Generate the block Alps
cellType ← BooleCore.AlpsCell[
name: "MeadConwayPLA",
public: CoreCreate.Wires[wa, wb, wc, "Z1", "Z2", "Z3", "Z4", "Vdd", "Gnd", "VRef"],
inputs: inputs, outputs: outputs
];
};