BooleDoc.tioga
Bertrand Serlet, July 21, 1986 3:56:58 pm PDT
BOOLE
CEDAR 6.1 — FOR INTERNAL XEROX USE ONLY
Boole
Bertrand Serlet
© Copyright 1986 Xerox Corporation. All rights reserved.
Abstract: Boole (also called Alps) is a layout generator which accepts a set of boolean equations, much like PLA generators do. It makes use of an original tree-structured representation of arbitrary boolean expressions. This representation is usually more compact than the classic disjunctive form, is suitable for fast symbolic manipulation, and maps naturally into silicon. Boole produces static CMOS layout using the cascode switch style.
Created by: Bertrand Serlet
Maintained by: Bertrand Serlet <Serlet.pa>
Keywords: Boolean Algebra, Boolean expressions, Disjunctive Normal Form, PLA, DCVS, Cascode, Static
XEROX Xerox Corporation
Palo Alto Research Center
3333 Coyote Hill Road
Palo Alto, California 94304
For Internal Xerox Use Only
Pointer to documentation
A paper (ALPS: A Generator of Static CMOS Layout from Boolean expressions, Advanced research in VLSI, proceeding of the fourth MIT conference, edited by Charles E. Leiserson, MIT Press, Cambridge, Massachusetts 02142) presents the technical details of Boole. Also a CSL notebook: [Indigo]<CSL-Notebook>Entries>85CSLN-0008.tioga. Boole follows very closely what is described in the paper.