Over the past two years, a new system for describing circuits and generating layout has been developed in the Computer Science Laboratory at Xerox PARC. For the most part, it is a complete system, in the sense that it includes tools for design capture, layout generation, analysis and simulation, timing verification, layout versus schematic comparison, design rules checking, plotting and documentation. Despite this impressive variety of tools, the most original aspects of the system reside in the use of a single data structure, the design capture, and the generation of layout.

The system is described thoroughly, albeit without any in-depth examples, in three companion papers: the data structure which is the foundation of our synthesis and analysis tools is described in [1], the details of capturing designs as a mixture of annotated schematics and code are shown in [2], and the general mechanism for generating layout is explained in [3].

This paper describes this DA system through actual examples that illustrate the major underlying principles. Section 2 gives a brief overview of the system. The following section takes a thorough look at the structure of a parameterized shift register; this shows the expressive power of schematics and code. Section 4 covers the assembly of a RAM array to exemplify how the mechanism of schematics annotations can be used to generate layout. This section insists on low-level details, only necessary to optimize layout, which are by no means representative of the feel that a user would get from the system. Circuits described with high-level generators, such as standard cells, data path, and routers, usually carry very few extra annotations.

In the last section, we give an idea of how far some of the concepts are carried by describing a finite-state-machine by its transition diagram.

The design system is based on a unique data structure which captures all aspects of a VLSI circuit in the form of a hierarchical structural description that we simply call a net-list. The data structure can be created directly by executing a program, by extracting and evaluating schematics, or more commonly, by a combination of both. It can then be processed by a variety of processors, such as simulators, analysis and verification tools, and layout generators.

The data structure is extensible in the sense that it may carry arbitrary annotations. New classes of objects and processors can be defined dynamically, without having to modify the existing system or source.

As an illustration of the expressive power of mixing parameterized schematics and code, we will walk through the description of a simple library element: a shift register.

The following example is taken from the register file of an experimental processor. The description illustrates the construction of a typical module generator using parameterized schematics. As expected in dense full-custom areas, the main layout operators are the low-level assembly functions of abutment, rotations and symmetries.

Only two leaf cells are needed to describe the memory array, one of which is a very simple stitch cell, needed only to distribute power. The main cell is a triple-port RAM cell, shown in Figure 4.1.1. as a schematic at transistor-level with several annotations. The width of transistors is a typical annotation and is used by the schematics versus layout comparator, the static checker, and various simulators. An interesting annotation is Layout, whose value Get means that the layout is available as a user-defined cell. Computing the layout simply returns that cell, after checking that the schematics and layout cells have compatible interfaces.

The next level of assembly describes a quad-word: the RAM cell, shown in Figure 4.2.1. in iconic form, is sequenced graphically and the resulting cell is composed with a RamStitch, forming a complete RamQuad cell. The graphical sequence is similar to the one of Section 3.2., except that the keyword SeqX specifies that the layout must proceed by abutting cells in the horizontal direction.

Let's slow down here to examine closely the layout generation. When the layout generator processes the annotated net-list, it first encounters the AbutX annotation; this indicates that cells are to be abutted in the horizontal direction to compose the layout. Notice that the order of cells is derived from the schematic and does not have to be repeated explicitly. This is an extremely simple illustration of the use of schematics as a graphical language: since the layout generator has access to the graphical representation of the circuit in addition to its net-list, it can infer a lot of hints: these hints are exactly the ones a designer would use, which minimizes the redundancy and improves the legibility of the design. This graphical language is put to full use by high-level layout generators, such as data path or pad frame generators: the relative positions of cells and wires are used as floorplanning information to drive the layout generation.

Back to layout generation. The Abut layout generator asks for the layout of its two components, the sequence and the stitch. The RamStitch cell carries a Get annotation and its layout is readily available; the sequence recursively calls the Array generator, which finally fetches the layout of the RAM cell. The layout of these two pieces are abutted, and an interface check is performed before returning the final layout for RamQuad. This RamQuad is then sequenced to form RamRow. Notice that the repetition factor is a parameter, making this a module generator rather than a fixed cell.

The layout of adjacent rows in the array must alternate in order to share power rails and wells. The schematic of Figure 4.3.1. shows a symmetric version of the row produced with the FlipY annotation; the row and its symmetric version are abutted, then sequenced vertically to form the entire array. The icon on the right side of Figure 4.3.1. simply abstracts this whole array. Since it is parameterized by the number of quads per words and the number of words, one must bind specific values to these parameters, as shown.

The array can at this point be enhanced with I/O logic, and address decoders which are more naturally described by a page of code. The whole description for this parameterized RAM fits comfortably on two graphic pages (the schematics and layout of leaf-cells) and on one page of code. The design can easily be put together in a matter of hours, particularly if part of it can be borrowed from another design, like the code for making a decoder, or the schematic of a memory cell.

Space is lacking here to illustrate how far we carried some of the concepts, so we will skim briefly over an additional example. Figure 5.1. shows on its left half an example of a finite-state-machine, described graphically with named states, outputs, and boolean equations conditioning the transitions. To the designer, it is simply a very readable picture which can be inserted into the circuit documentation; to the DA system, it is a portion of a schematic which can be extracted, just like a stack of gates would be.

The schematic is extracted by an extractor specific to the FSM cell class. Depending on the option used, the result of the extraction can be an empty cell with a behavioral model generated directly from the boolean equations, or a complete net-list representing the FSM as standard cells or a PLA. An icon can be generated automatically from the schematic: it is shown in the right half of Figure 5.1. as part of a FIFO controller.

We have presented a few examples which illustrate the major concepts behind our DA system, but these examples only give a weak idea of its power. Parameterized schematics mixed with code lead to very concise and natural descriptions of circuits: we have described circuits using representations bearing no resemblance to traditional schematics, i.e. finite-state-machines, boolean equations, data paths, and we have little doubt that the extensibility of the system will encourage new creative development.

It is remarkable that the mechanism of annotating the source to drive the layout generation does not impose unreasonable restrictions on the style of layout: as a proof, a handful of designers have produced over the past couple of years a dozen chips ranging in complexity from small test chips, put together in a couple of hours, to full-custom circuits of over 300K transistors. The set of generators they used is quite large: in addition to the basic generators exhibited in this paper (Get, Abut, symmetries and rotations, arrays), one can place and route standard cell blocks, route blocks, assemble data path, semi-regular tilings, and pad frames. Specialized generators for logic arrays [5], and libraries of parameterized macros complete the panoply.

Although work is proceeding to improve the system, the concepts of design capture as parameterized schematics mixed with code, and the use of annotations to drive layout generation already seem to be very powerful ones. As evidence, the variety of circuits developed with minimum man power using this system.

The development of a state-of-the-art DA system cannot be dissociated from the development of state-of-the-art circuits: many designers at PARC, mainly in the Dragon project, have acted both as alpha-users and developers, providing ample feedback, challenging requests, new libraries, and generators. Among them, the author wants to acknowledge specially Rick Barth, Bertrand Serlet, and Pradeep Sindhu, who have co-authored the three papers [1, 2, 3] describing the system. Giordano Beretta, Don Curry, Jean-Marc Frailong, Christian Jacobi, Jim Gasbarro, Christian Le Cocq, Brian Preas and Mike Spreitzer have also left a paw-print on the DA system. Finally our Cedar programming environment [4] has to take some of the credit for enabling quick prototyping and development of the system.