DIRECTORY CD, CDAtomicObjects, CDDesignRules, Core, CoreClasses, Properties, PWPins, RefTab, Rope, PW; Stix: CEDAR DEFINITIONS = BEGIN ROPE: TYPE = Rope.ROPE; Techno: TYPE = CD.Technology; Layer: TYPE = CD.Layer; Layers: TYPE = LIST OF Layer; Rect: TYPE = CD.Rect; Object: TYPE = CD.Object; Instance: TYPE = CD.Instance; Position: TYPE = CD.Position; Orient: TYPE = CD.Orientation; InstanceList: TYPE = CD.InstanceList; Side: TYPE = PWPins.Side; Tab: TYPE = RefTab.Ref; Properties: TYPE = Core.Properties; CellType: TYPE = Core.CellType; Wire: TYPE = Core.Wire; RecordCell: TYPE = CoreClasses.RecordCellType; CoreInst: TYPE = CoreClasses.CellInstance; Color: TYPE = ATOM; -- for design-rules independence; something like $pol or $met2 Colors: TYPE = LIST OF Color; DRect: TYPE = CDAtomicObjects.DrawRec; -- [r: D2Basic.Rect, lev: CD.Layer] DRects: TYPE = LIST OF DRect; DRules: TYPE = CDDesignRules.DesignRules; layoutProp: ATOM; -- StickPtr (cell) on Core.CellType errorsProp: ATOM; -- LIST OF ROPE (list of errors after check) on Core.CellType pinsProp: ATOM; -- StickPtrs (wire, contact) on public Core.Wire wireGeometryProp: ATOM; -- StickPtrs (wire, contact) on internal Core.Wire instanceProp: ATOM; -- StickPtr on CoreRecord.Instance extractedCoreProp: ATOM; -- CellType on StickPtr (cell or transistor); same as Sinix wireNodesProp: ATOM; -- Nodes on internal Core.Wire GetStickPtr: PROC [cellType: CellType] RETURNS [StickPtr]; PutStickPtr: PROC [cellType: CellType, stickPtr: StickPtr]; GetWireGeom: PROC [wire: Wire] RETURNS [StickPtrs]; PutWireGeom: PROC [wire: Wire, stickPtrs: StickPtrs]; AppendWireGeom: PROC [wire: Wire, stickPtr: StickPtr]; GetInstance: PROC [coreInst: CoreClasses.CellInstance] RETURNS [StickPtr]; PutInstance: PROC [coreInst: CoreClasses.CellInstance, stickPtr: StickPtr]; Class: TYPE = REF ClassRec; ClassRec: TYPE = RECORD [ objectType: ATOM, LayoutMe: LayoutProc, ExplodeMe: ExplodeProc, MyOriginNode: OriginProc, AllMyNodes: EnumerateNodesProc, properties: Properties _ NIL ]; LayoutProc: TYPE = PROC [stickPtr: StickPtr, cell: Object, dr: DRules] RETURNS [inst: Instance]; OriginProc: TYPE = PROC [stickPtr: StickPtr] RETURNS [node: Node]; EnumerateNodesProc: TYPE = PROC [stickPtr: StickPtr] RETURNS [nodes: Nodes]; ExplodeProc: TYPE = PROC [stickPtr: StickPtr, dr: DRules]; Node: TYPE = REF NodeRec; NodeRec: TYPE = RECORD [ pos: Position _ [0, 0], private: BOOL _ FALSE]; -- a private node (e.g. from a transistor) cannot be shared Nodes: TYPE = LIST OF Node; Plate: TYPE = REF PlateRec; PlateRec: TYPE = RECORD [dr: DRect, node: Node _ NIL]; Plates: TYPE = LIST OF Plate; StickPtr: TYPE = REF StickRec; StickRec: TYPE = RECORD[ class: Class, data: REF, -- type is depending on the class dP: Position _ [0, 0], -- position of the origin of CD.Instance wrt to node.pos plates: Plates _ NIL, -- all the plates composing the CD object properties: Properties _ NIL -- could put the plate-related stuff here? ]; StickPtrs: TYPE = LIST OF StickPtr; ContactRef: TYPE = REF ContactRec; -- a contact is defined for two layers only ContactRec: TYPE = RECORD [ node: Node _ NIL, -- contact is centered on the node dx, dy: NAT _ 0, -- size for larger contacts color1, color2: Color _ NIL -- colors underneath ]; WireRef: TYPE = REF WireRec; -- defined by two nodes WireRec: TYPE = RECORD [ origin: Node _ NIL, -- lower left other: Node _ NIL, -- upper right color: Color _ NIL, -- wire color width: NAT _ 0 -- width ]; TransistorRef: TYPE = REF TransistorRec; -- straight transistors only TransistorRec: TYPE = RECORD [ gate, ch1, ch2: Node _ NIL, -- centered on gate color: Color _ NIL, -- tr. color (e.g. dif) width, length: NAT _ 0 -- size of the channel ]; StickCell: TYPE = REF StickCellRec; StickCellRec: TYPE = RECORD [ allNodes: Nodes _ NIL, -- all the nodes; very important field IRect: Rect _ [0, 0, 0, 0], -- the interestRect tab: Tab _ NIL, -- node -> Core.Wire origin: Node _ NIL, -- one of the nodes name: ROPE _ NIL -- used to name the CD cell ("foo-compacted-XY") ]; contactClass, wireClass, transistorClass, stickCellClass: Class; CreateStickCell: PROC [name: ROPE] RETURNS [stickPtr: StickPtr]; CreateNode: PROC [pos: Position, wire: Wire, cellType: CellType, private: BOOL _ FALSE] RETURNS [node: Node]; CreateContact: PROC [node: Node] RETURNS [stickPtr: StickPtr]; CreateWire: PROC [n1, n2: Node, color: Color, width: NAT _ 0] RETURNS [stickPtr: StickPtr]; CreateTransistor: PROC [gate, ch1, ch2: Node, color: Color, width, length: NAT] RETURNS [stickPtr: StickPtr]; FinishCell: PUBLIC PROC [cellType: CellType]; ConvertToDR: PUBLIC PROC [cellType: CellType, dr: DRules]; PlatesAreConnected: PROC [p1, p2: Plate, table: Tab] RETURNS [BOOL _ FALSE]; NodesAreConnected: PROC [n1, n2: Node, table: Tab] RETURNS [BOOL _ FALSE]; nTrColor, pTrColor, trGateColor: Color; Layout: LayoutProc; AllNodes: EnumerateNodesProc; Origin: OriginProc; Explode: ExplodeProc; EachStickPtrProc: TYPE = PROC [stickPtr: StickPtr, wire: Wire] RETURNS [quit: BOOL _ FALSE]; EnumerateInsts: PROC [cellType: CellType, proc: EachStickPtrProc] RETURNS [quit: BOOL]; OtherEnd: PUBLIC PROC [stickPtr: StickPtr] RETURNS [node: Node]; -- wire only END. ‚Stix.mesa Copyright c 1985 by Xerox Corporation. All rights reserved. Created by Louis Monier, October 22, 1985 11:08:27 am PDT Louis Monier, December 6, 1985 2:27:40 pm PST This module provides the basic primitives for describing a circuit at a level which is in between Core (net list) and ChipNDale (mask). The basic object is a Core.CellType decorated with Stix instances (StickPtr). The description is design-rules independent and mostly topological. The design-rules independence is expressed through the use of very simple objects and layers (the colors). These objects and colors are general enough to cover most MOS-like technologies and can be translated easily in valid masks when one provides the design rules. The hope is to obtain all the information from CDDesignRules (an extension of CDSimpleRules). The symbolic objects are defined in the topological domain: symbolic objects (contacts, wires, transistors) are described in reference to nodes. These nodes have positions, and are constraint by the objects: for example all the nodes of a wires are constraint to be on the same horizontal or vertical axis. The input can be done through creation procedures, or by parsing a simplified "stick" notation using ChipNDale rectangles and a few symbols. The technology used to do this input does not matter. Various compactors are available: they need to be able to decompose a circuit in plates (the sub-atomic entities, a rectangle and a layer; would you prefer "quarks"?) and the knowledge of electrical connectivity between plates. So far, virtual grid compactors exist. More will be written. Common types -- for convenience -- new Properties connecting Core to Stix Topological representation -- Sizes and positions are expressed in the target unit system! -- A node is a point in a topological space -- A plate is a rectangle of color pointing toward a node -- The symbolic object -- The specific types Creation procedures -- Always use the creation and inclusion procs -- Never delete something from a cell -- Must be called when all StickPtrs are in the cell -- Must be called before layout or compaction Utilities Easy access to OO procedures ΚW˜šœ ™ Jšœ Οmœ1™˜RJšœžœžœžœ˜Lšœžœ $œ˜KLšœžœžœžœ˜Jšœžœ˜)—™"Jšœ žœ #˜8Jšœ žœ =˜QJšœ žœ 0˜CJšœžœ 2˜JJšœžœ "˜7J˜Jšœžœ ;˜UJ˜Jšœžœ ˜5J˜LšΟn œžœžœ ˜:Lš‘ œžœ*˜;Lš‘ œžœžœ ˜3Lš‘ œžœ$˜5Lš‘œžœ"˜6Lš‘ œžœ&žœ ˜JLš‘ œžœ:˜KJ˜—™L™?L˜Lšœžœžœ ˜šœ žœžœ˜Lšœ žœ˜L˜L˜Lšœ˜Lšœ˜Lšœžœ˜L˜—L™Lš‘ œžœžœ0žœ˜`Lš‘ œžœžœžœ˜BLš‘œžœžœžœ˜LLš‘ œžœžœ"˜:L˜L™+Lšœžœžœ ˜šœ žœžœ˜Lšœ˜Lšœ žœžœ ;˜S—Lšœžœžœžœ˜L™L™9Lšœžœžœ ˜Lšœ žœžœžœ˜6Lšœžœžœžœ˜L˜L™Lšœ žœžœ ˜šœ žœžœ˜Jšœ ˜ Jšœžœ !˜2Jšœ 8˜RJšœžœ )˜CLšœžœ +˜HJšœ˜—Lšœ žœžœžœ ˜#J˜L™J˜Jšœ žœžœ +˜Pšœ žœžœ˜Lšœ žœ "˜5Jšœžœ  ˜1Jšœžœ ˜3Lšœ˜—J˜Jšœžœžœ  ˜7šœ žœžœ˜Lšœžœ  ˜"Lšœžœ ˜"Jšœžœ  ˜&Jšœžœ  ˜Lšœ˜—L˜Jšœžœžœ ˜Ešœžœžœ˜Lšœžœ ˜/Jšœžœ ˜0Jšœžœ  ˜1Lšœ˜—L˜Lšœ žœžœ˜#šœžœžœ˜Lšœžœ &˜>Lšœ ˜0Lšœ žœ ˜%Lšœžœ ˜(Lšœžœžœ 0˜BLšœ˜—L˜Jšœ@˜@—™L™.L™%Lš‘œžœžœžœ˜@Lš ‘ œžœ:žœžœžœ˜mLš‘ œžœžœ˜>Lš‘ œžœ%žœžœ˜[Lš‘œžœ5žœžœ˜mL˜Lšœ4™4Lš‘ œžœžœ˜-L™L™-Lš‘ œžœžœ"˜:—™ Lš ‘œžœžœžœžœ˜LLš ‘œžœžœžœžœ˜JJšœ'˜'L˜—™Lš‘œ ˜Lš‘œ˜Lš‘œ ˜Lš‘œ˜L˜Lš ‘œžœžœ"žœžœžœ˜\Lš‘œžœ.žœžœ˜WLš ‘œžœžœžœ  ˜ML˜—J˜Jšžœ˜J˜—…—–$o