CDDesignRules.mesa
Copyright © 1985 by Xerox Corporation. All rights reserved.
First definition by Christian Jacobi
Remodeled by Louis Monier November 21, 1985 5:07:18 pm PST
Louis Monier November 25, 1985 6:28:13 pm PST
DIRECTORY
CD, CDAtomicObjects, CDSimpleRules, Rope, SymTab;
CDDesignRules: CEDAR DEFINITIONS =
BEGIN
A little bit of terminology:
- a technology (ChipNDale sense) is defined by a set of layers and a set of atomic objects. For example CMosB has metal2, no buried or butting contact but small vias.
- a set of design rules defines the minimum size and spacings of layers, the legal layout of basic objects (transistors and contacts), the value of l, and more exotic rules like flatness for via or frequency of well contacts. Design rules express the difference in capabilities between fab lines trying to manufacture the same process. (By the way, if the notion of design rules is long-lived in ChipNDale, I think that even the size and shape of atomic objects should be parametrized by design rules rather than require a change in technologies; so the same transistor could exist in CMos and CMosB, but its diffusion extension would be 2m or 3m depending on the design rules). Different sets of design rules making reference to the same technology will share layer names.
- Things like electrical models for devices change from one run to another, and represent another level which is not formally introduced in ChipNDale.
This is an attempt to capture all design rules into a single module, to be shared by an extractor (Sinix), a DRC (SOS and all Gismos) and a symbolic layout system and its compactors (Stix), plus whatever tool would need to access details of the geometrical design rules.
It is impossible to capture all the aspects of a technology. We are mostly concerned with the geometrical representation of devices and wires, and ignore other things which are technology-dependent because there are too many of them (name of CIF layers, parameters for mask generation, . . . ). For example we don't address here the problem of describing the electrical properties of the devices (although a simplified model could be used by a QAD simulator).
Basics
DesignRules: TYPE = REF DesignRulesRep;
DesignRulesRep:
TYPE =
RECORD [
atom: ATOM, -- unique to a set of design rules
techno: CD.Technology, -- can be shared by several sets of design rules
lambda: INT,
gateSDNodeSp: INT, -- typically 2 (target lambda)
standardTrSize: CD.Position,
trPolExt, trDifExt: INT,
pol, met, met2, cut, cut2, gate: CD.Layer,
ndif, pdif, wndif, wpdif, nwell, pwell, nwellCont, pwellCont: CD.Layer
];
DRect:
TYPE = CDAtomicObjects.DrawRec;
-- [r: D2Basic.Rect, lev: CD.Layer ← CD.highLightError]
DRects: TYPE = LIST OF DRect;
ROPE: TYPE = Rope.ROPE;
NotKnown: ERROR;
-- The atom should be something like $CMosBICL1micron
FindRules:
PROC[a:
ATOM]
RETURNS [dr: DesignRules];
--NIL if not found
Distance rules
MinWidth:
PROC [dr: DesignRules, layer:
CD.Layer]
RETURNS [
CD.Number];
-- Minimum width of conductors.
-- (Width of interrest rect).
MinDist:
PROC [dr: DesignRules, l1, l2:
CD.Layer]
RETURNS [
CD.Number];
-- Minimum distance between unconnected conductors.
-- 0 if no interaction.
-- Error if l1 and l2 from different technologies.
-- (Distance of interrest rects).
MinConnectedDist:
PROC [dr: DesignRules, l1, l2:
CD.Layer]
RETURNS [
CD.Number];
-- Minimum distance between connected conductors.
-- 0 if no interaction.
-- Error if l1 and l2 from different technologies.
-- (Distance of interrest rects).
Object generators
GetTechnology: PROC [dr: DesignRules] RETURNS [CD.Technology];
-- why not DesignRules?
GetLayer:
PROC [technology, layer:
REF]
RETURNS [
CD.Layer];
-- Tries to figure out a layer, given names.
-- Use only to get technology specific names.
-- A little bit more forgiving than CD.FetchLayer...
-- Error if not known.
-- pins are techno-indep., so I should not bother...
Pin: PROC [size: CD.Position] RETURNS [CD.Object];
Rect:
PROC [size:
CD.Position, layer:
CD.Layer]
RETURNS [
CD.Object];
-- size: interest rect
Contact:
PROC [dr: DesignRules, l1, l2:
CD.Layer, size:
CD.Position]
RETURNS [
CD.Object];
-- NIL if certain complications or no contact possible...
-- use CD.InterestRect to get size;
-- CHECK size: procedure may make approximations !
Transistor:
PROC [dr: DesignRules, difL:
CD.Layer, w, l:
CD.Number]
RETURNS [
CD.Object];
-- NIL if some complication or no contact possible...
-- w and l are gate width and length, not object size
-- procedure may make approximations
-- use CD.InterestRect to get object size;
LayerOk: PROC [dr: DesignRules, layer: CD.Layer] RETURNS [BOOL];
ObjectClassOk: PROC [dr: DesignRules, class: CD.ObjectClass] RETURNS [OKness];
OKness: TYPE = {yes, maybe, no};
--maybe means: check each object
ObjectOk: PROC [dr: DesignRules, ob: CD.Object] RETURNS [BOOL];
Getting information on the inside
Explode:
PROC [dr: DesignRules, object:
CD.Object]
RETURNS [dummy:
CD.Object];
--returns a dummy cell which is NOT part of the design
--dummy must not be modified
--dummy contains only symbolic instances (pins) denoting the interconnection areas
DummyGateCell: PROC [dr: DesignRules, trans: CD.Object] RETURNS [--READONLY--CD.Object];
--dummy cell has symbolic object instances denoting the gate area
TransistorRatio: PROC [trans: CD.Object] RETURNS [w, l: CD.Number];
--not size !
Well (or implant if NMos) surround rules
NeedSurround:
PROC [dr: DesignRules, layer:
CD.Layer]
RETURNS [surList:
LIST
OF LayerAndDistance];
-- treat surList as READONLY
LayerAndDistance:
TYPE =
RECORD [layer:
CD.Layer, amount:
CD.Number];
--positive means grow
SurroundForClassOk: PROC [dr: DesignRules, class: CD.ObjectClass, layer: CD.Layer] RETURNS [OKness];
-- objects of the class with layer: layer will have surround for sure and testing it is not necessary
END.