SXUserExtractImpl.mesa
Copyright © 1984, 1985 by Xerox Corporation. All rights reserved.
Written by Shand, March 7, 1985 8:41:53 pm PST
Last Edited by Shand, March 13, 1985 4:42:32 am PST
Last Edited by Jacobi, April 8, 1985 12:42:12 pm PST
Last edited by: gbb July 17, 1985 5:52:21 pm PDT
DIRECTORY
Atom USING [GetPropFromList, PutPropOnList],
CD USING [combined, CreateDrawRef, DrawRectProc, DrawRef, Instance, Layer],
CDBasics USING [Intersection, NonEmpty, ToRect],
CDInstances USING [NewInstance],
CDOps USING [LayerName],
CDOrient USING [original, MapRect],
CDPinObjects USING [EnumeratePins, GetLayer, GetName, GetOwner, InstanceEnumerator],
IO USING [Close, EndOf, Error, RIS, SkipWhitespace, STREAM],
Rope USING [Cat, Equal, ROPE],
SX USING [AddRect, AdjustNode, Circuit, CircuitNode, IllegalLayer, LogicalCell, SignalName, SpinifexLayerIndex],
SXAccess,
SXAccessInternal,
SXAtoms USING [SignalName, spinifexCircuitDescription],
SXUserExtract,
SymTab USING [Create, Fetch, Ref, Store];
SXUserExtractImpl: CEDAR PROGRAM
IMPORTS Atom, CD, CDBasics, CDInstances, CDOps, CDOrient, CDPinObjects, IO, Rope, SX, SXAccess, SXAccessInternal, SXAtoms, SymTab
EXPORTS SXUserExtract =
BEGIN
ConnectionPin: PROCEDURE [app: CD.Instance] RETURNS [BOOLEAN] ~ {
RETURN [CDPinObjects.GetOwner[app] = NIL AND CDPinObjects.GetLayer[app] # CD.combined]
};
DataForRects: TYPE ~ RECORD [
pinLayer: CD.Layer,
pinName: Rope.ROPE,
cir: REF SX.Circuit,
ports: SymTab.Ref
];
TranslateCell: PUBLIC PROCEDURE [cell: REF SX.LogicalCell, CircuitDescription: Rope.ROPE] ~ {
AddPinRects: CDPinObjects.InstanceEnumerator ~ {
IF ConnectionPin[inst] THEN {
dataRef: REF DataForRects ← NEW[DataForRects];
dr: CD.DrawRef ~ CD.CreateDrawRef[NIL];
fakeAppl: CD.Instance = CDInstances.NewInstance[ob~ cell.cellObj];
fakeAppl.location ← [0, 0];
dr.drawRect ← CaptureGeomInPin;
dr.devicePrivate ← dataRef;
dr.stopFlag ← SXAccess.stopFlag;
dr.interestClip ← CDOrient.MapRect[itemInCell~ CDBasics.ToRect[[0,0], inst.ob.size], cellSize~ inst.ob.size, cellInstOrient~ inst.orientation, cellInstPos~ inst.location];
dataRef.pinLayer ← CDPinObjects.GetLayer[inst];
dataRef.pinName ← CDPinObjects.GetName[inst];
dataRef.cir ← cell.circuit;
dataRef.ports ← ports;
cell.cellObj.class.drawMe[fakeAppl, [0, 0], CDOrient.original, dr ! SX.IllegalLayer => { SXAccessInternal.PutError[ob: cell.cellObj, r: dr.interestClip,
message: Rope.Cat["Material on level ", CDOps.LayerName[dataRef.pinLayer], " may not appear as an isolated rectangle.\n"]];
GOTO BadRect }
];
EXITS BadRect => NULL
};
quit ← FALSE
}; -- end AddPinRects
ports: SymTab.Ref ~ SymTab.Create[521];
-- Flag this cell for special output handling.
cell.circuit.properties ← cell.circuit.properties.PutPropOnList[ SXAtoms.spinifexCircuitDescription, SXAtoms.spinifexCircuitDescription];
IF ~ Rope.Equal [CircuitDescription, "()"] THEN {
[] ← CDPinObjects.EnumeratePins[cell.cellObj, AddPinRects];
ReadPortOrder[ cell, IO.RIS[CircuitDescription], ports];
And now do something about making node order match port order.
};
Now do something to generate cell exclusion regions.
Do bloating & shrinking cleanups on these regions
and something to make sure pins are accessible.
And insert the resulting boxes using AddBox.
};
CaptureGeomInPin: CD.DrawRectProc -- [r: DesignRect, l: Layer, pr: DrawRef] -- ~ {
data: REF DataForRects ~ NARROW[pr.devicePrivate];
IF l = data.pinLayer THEN {
r ← CDBasics.Intersection[r, pr.interestClip];
IF CDBasics.NonEmpty[r] THEN {
-- value parameter may be NIL node has not been added yet
node: REF SX.CircuitNode ~ SX.AddRect[ cir~ data.cir, lev~ l, dim~ r, value~ NARROW[data.ports.Fetch[data.pinName].val]];
IF node # NIL THEN {
Layers: TYPE ~ SX.SpinifexLayerIndex;
[] ← data.ports.Store[data.pinName, node];
FOR layer: Layers IN [Layers.FIRST .. SXAccess.sxTech.numSpinifexLayers) DO
SX.AdjustNode[node, layer, 0, 0, absolute];
ENDLOOP;
IF node.properties.GetPropFromList[SXAtoms.SignalName] = NIL THEN
node.properties ← node.properties.PutPropOnList[SXAtoms.SignalName, NEW[ SX.SignalName ← [name~ data.pinName]]]
};
}
}
};
ReadPortOrder: PROC [cell: REF SX.LogicalCell, from: IO.STREAM, ports: SymTab.Ref] ~ {
-- Process SpinifexCircuitDescription property (a ROPE) to determine order of Thyme ports for cell.
ENABLE IO.Error => {
};
DO
[] ← from.SkipWhitespace[];
IF from.EndOf[] THEN EXIT;
EXIT;
ENDLOOP;
from.Close[];
};
END.
Edited on May 6, 1985 11:26:55 am PDT, by Beretta
Converted to ChipNDale CD20