<> <> <> <> <> <> DIRECTORY Ascii, Atom, CD, CDDirectory, CDIO, CDObjectProcs, CDProperties, Convert, Core, CoreRecord, FS, IO, RefTab, Rope, SX, SXAtoms, SXOutput, SymTab, TerminalIO, TiogaOps ; SXOutputPrivate: CEDAR DEFINITIONS ~ BEGIN <<-- TYPES from SX.>> Circuit: TYPE ~ SX.Circuit; CircuitNode: TYPE ~ SX.CircuitNode; AreaPerimRec: TYPE ~ SX.AreaPerimRec; NodeLinkage: TYPE ~ SX.NodeLinkage; MergeRec: TYPE ~ SX.MergeRec; TechHandle: TYPE ~ SX.TechHandle; MergeRecList: TYPE ~ SX.MergeRecList; SignalName: TYPE ~ SX.SignalName; LogicalCell: TYPE ~ SX.LogicalCell; <<-- TYPES from elsewhere.>> ROPE: TYPE ~ Rope.ROPE; ROPEList: TYPE ~ LIST OF ROPE; <<-- Naming>> Naming: TYPE ~ REF NamingRep; NamingRep: TYPE ~ RECORD [next: Naming, named: REF ANY, prefixes: ROPEList, name: ROPE, explicit, collided, squash: BOOL _ FALSE, count: INTEGER _ CountBase-1]; < this is not really a name for anything>> <> GetANaming: PROC [thing: REF ANY, insistValid: BOOL _ FALSE] RETURNS [naming: Naming]; Valid: PROC [naming: Naming] RETURNS [valid: BOOL]; GetAName: PROC [thing: REF ANY] RETURNS [name: ROPE]; NamingName: PROC [naming: Naming] RETURNS [name: ROPE]; HasAskedName: PROC [thing: REF ANY] RETURNS [asked: BOOL]; NamingAsked: PROC [naming: Naming] RETURNS [asked: BOOL]; EnumerateNames: PROC [thing: REF ANY, PerName: PROC [name: ROPE, valid: BOOL], onlyValid: BOOL _ TRUE]; ReverseNamings: PROC [oldFirst: Naming] RETURNS [newFirst: Naming]; SortNamings: PROC [oldFirst: Naming] RETURNS [newFirst: Naming]; PrintNaming: PROC [to: IO.STREAM, naming: Naming, insert: ROPE _ NIL]; <<-- Name generator customization>> CountBase: INTEGER ~ 1; <<-- Assistant procs>> AddIntermediateNodes: PROC [cellList: LIST OF REF LogicalCell]; CleanUp: PROC [cellList: LIST OF REF LogicalCell]; <<-- Randomness>> isPort, actualCellInstanceName, actualSignalName: ATOM; ValidMerge: PROC [MergeRec] RETURNS [BOOL]; PrintRoseInstantiationTransformation: PROC [to: IO.STREAM, appl: CD.Instance]; PrintRoseInstanceBounds: PROC [to: IO.STREAM, appl: CD.Instance]; NameTransType: PROC [desWDir: ROPE, obj: CD.Object, dfStream: IO.STREAM, type, mode: ATOM, length, width: CD.Number] RETURNS [name: ROPE]; UnNameTransType: SXOutput.LinkageHousekeeper; <> QuoteProc: TYPE ~ PROCEDURE [name: ROPE] RETURNS [ROPE]; PrintStrayProc: TYPE ~ PROCEDURE [Stream: IO.STREAM, node: REF CircuitNode]; PrintNodeLocProc: TYPE ~ PROCEDURE [Stream: IO.STREAM, node: REF CircuitNode]; <> PrintHeadProc: TYPE ~ PROCEDURE [obj: CD.Object, name: ROPE]; PrintFormalProc: TYPE ~ PROCEDURE [qName: ROPE, first: BOOL, node: REF CircuitNode]; PrintStartBodyProc: TYPE ~ PROCEDURE [cellName: ROPE]; PrintLocalNodeProc: TYPE ~ PROCEDURE [node: REF CircuitNode]; PrintNodeAliasesProc: TYPE ~ PROCEDURE [node: REF CircuitNode, alias: Naming]; PrintInstanceHeadProc: TYPE ~ PROCEDURE [inst: CD.Instance, defName: ROPE]; PrintActualProc: TYPE ~ PROCEDURE [qActualNode, qFormalPort: ROPE, actualNum: CARDINAL]; PrintInstanceEndProc: TYPE ~ PROCEDURE []; PrintBodyEndProc: TYPE ~ PROCEDURE []; <> coreDesign: Core.Design; coreCellBuffer: Core.CellType; coreCellInstance: CoreRecord.RecordCellType; coreInstanceBuffer: CoreRecord.CellInstance; corePortBuffer, coreNodeBuffer, corePortInstances: LIST OF Core.Wire; strayBuffer: Core.Properties; QuoteCore: QuoteProc; ComputeStray: PrintStrayProc; InsertCell: PrintHeadProc; InsertPort: PrintFormalProc; EndPortList: PrintStartBodyProc; InsertNode: PrintLocalNodeProc; CreateInstance: PrintInstanceHeadProc; InsertPortInstance: PrintActualProc; EndPortInstanceList: PrintInstanceEndProc; SetDesignProp: PROCEDURE [cdD: CD.Design, coreD: Core.Design] END. <> <> <> <> <> <> <<>>