[Pixel]<Chipndale>6.0>SpinifexT>SX.mesa!3

SX.mesa

Spinifex main definitions; Data structures.

Written by Shand, March 11, 1985 8:01:11 pm PST

Last Edited by: Jacobi, April 5, 1985 1:01:19 pm PST

Bowers, September 4, 1985 5:43:44 pm PDT

Last edited by: gbb August 7, 1985 10:48:36 am PDT

DIRECTORY

Atom USING [PropList],

CD USING [Instance, InstanceList, Layer, Number, Object, Orientation, Position, Rect],

CDOrient USING [original],

RefTab USING [Ref],

Rope USING [ROPE],

SXQuadTree USING [QuadTreeRoot, RectDelta];

SX: CEDAR DEFINITIONS =

BEGIN

TranslateGeometry: PROCEDURE [cell: REF LogicalCell];

--Translates ChipNDale layers into Spinifex layers (e.g. only explicit contacts [which must be correct and hence are not checked] are allowed. Also a node number is assigned, which is used to identify the nodes.
The translation is performed using the drawRect mechanism of ChipNDale. The ChipNDale design is translated into a quad-tree. It is not possible to use a tesselation because of overlaps.
The quad-tree contains only cells already analysed. There are four types of rectangles: 1. constraints; 2. material; 3. extra constraint rectangles for transistors; 4. interlayer checks. Everithing that is not a rectangle is considered to be a child.

-- AddBox adds a box to a particular analysis layer when fine control or asymetric interest bloating is required. The box, of dimension dim is transform according to appl.

-- Escape mechanism, i.e. used to get around AddRect.

AddBox: PROCEDURE [ cir: REF Circuit,
spinifexLayer: SpinifexLayerIndex,
dim: CD.Rect,
inst: CD.Instance ← NIL,
pos: CD.Position ← [0,0],
orient: CD.Orientation ← CDOrient.original,
interestBloat: SXQuadTree.RectDelta ← [0,0,0,0],
value: REF ANY ← NIL]

RETURNS [cirNode: REF CircuitNode ← NIL];

-- AddRect adds a Rectangle from a normal chipndale mask level, to each of the analysis layers which the techHandle dictates. May raise ERROR IllegalLayer.

AddRect: PROCEDURE [ cir: REF Circuit,
lev: CD.Layer,
dim: CD.Rect,
inst: CD.Instance ← NIL,
pos: CD.Position ← [0,0],
orient: CD.Orientation ← CDOrient.original,
value: REF CircuitNode ← NIL]

RETURNS [cirNode: REF CircuitNode ← NIL];

IllegalConstruct: ERROR [rect: CD.Rect, reason: Rope.ROPE];

IllegalLayer: ERROR [rect: CD.Rect, lev: CD.Layer];

CreateLinkage: PROCEDURE [ cir: REF Circuit, source: CD.Instance, length, width: CD.Number] RETURNS [REF NodeLinkage];

LinkageAttach: PROCEDURE [link: REF NodeLinkage, attachType: ATOM, node: REF CircuitNode ← NIL];

NormalizeCircuit: PROCEDURE [cir: REF Circuit];

LookupNode: PROCEDURE [l: REF CircuitNode] RETURNS [REF CircuitNode];

FindRootNode: PROCEDURE [ -- look at HighlightNode for usage
circuit: REF Circuit,
subcircuitNode: REF CircuitNode,
qualifier: LIST OF CD.Instance,
insertIfNotInCircuit: BOOLEAN ← FALSE
]
RETURNS [
node: REF CircuitNode,
rootQualifier: LIST OF CD.Instance];

MergeNode: PROCEDURE [circuit: REF Circuit, to, from: REF CircuitNode];

--node "from" will be superceded to by "to"

-- Combines areas, perimeters, and properties

AdjustmentMode: TYPE = {relative, absolute};

AdjustNode: PROCEDURE [node: REF CircuitNode, layer: SpinifexLayerIndex, area: INT, perim: INT, mode: AdjustmentMode ← relative];

AnalysisState: TYPE = {notYetDone, useCircuit, reservedForFuture};

LogicalCell: TYPE = RECORD [

circuit: REF Circuit ← NIL,

cellObj: CD.Object, --bad circular ref, REMOVE

analysisState: AnalysisState ← notYetDone,

rootOnInvocation: REF ← NIL, --must do special check for root cells

lastInvocation: REF ← NIL,

errorCount: INT ← 0,

errorContext: Rope.ROPE ← NIL, -- Place where errors have been put if not in this cell.

privateForSX: REF ← NIL --for future use

];

--A node is a conductive region. When nodes are merged as a result of an overlap or abutment of similar rectangles, the estimated capacitance to ground must be adjsted due to the change in perimeter and area of these regions when combined.

Circuit: TYPE = RECORD [

nodes: LIST OF REF CircuitNode ← NIL,

linkages: LIST OF REF NodeLinkage ← NIL,

linkageCount: RECORD [inSelf: INT ← 0, inChildren: INT ← 0],

subcircuits: CD.InstanceList ← NIL, -- copies; have instance names

mergeDirectory: RefTab.Ref ← NIL, -- establishes a correspondence between a node in this cell and a node in a cell at the end of a chain of cell instantations. Key: Circuit node (of a subcircuit); val: MergeRecList.

properties: Atom.PropList ← NIL,

invocationKey: INT, --remove !!

spinifexLayers: ARRAY SpinifexLayerIndex OF SXQuadTree.QuadTreeRoot -- build up on 1st step: translate

];

CircuitNode: TYPE = RECORD [

superceded: REF CircuitNode ← NIL, -- NIL if analysis finished

dim: LIST OF AreaPerimRec ← NIL,

loc: NodeLocation,

properties: Atom.PropList ← NIL -- Cedar

];

NodeLocation: TYPE = RECORD [

xy: CD.Position,

layer: SpinifexLayerIndex

];

AreaPerimRec: TYPE = RECORD [

layer: SpinifexLayerIndex,

area, perim: INT

];

SignalName: TYPE = RECORD [

depth: INTEGER ← 0,

name: Rope.ROPE,

alias: REF SignalName ← NIL,

makePort: BOOL ← FALSE -- in a root cell it will be considered to be a port

];

-- Constraint may contain circular REF chains, however they are a small in number fixed at compile time by the tech. dependent client software.

maxConstraints: INTEGER = 16;

ConstraintIndex: TYPE = [0..maxConstraints) ← ConstraintIndex.FIRST;

spaceIndex: ConstraintIndex = 0; -- space regions.

nodeIndex: ConstraintIndex = 1; -- node regions.

excludeIndex: ConstraintIndex = 2; -- region excluded by Opaque cell.

violateIndex: ConstraintIndex = 3; -- Opaque cell exclusion region violated

techCIndexBase: ConstraintIndex = 4; -- Technology dependent clients should start number their constraints in each layer from here.

Constraint: PUBLIC TYPE = RECORD [ -- belongs to the technology

name: ATOM,

index: ConstraintIndex, -- index into the constrain array

hasCorrespondingNode: BOOLEAN ← FALSE, -- used where connectivity affects the rule and there is a corresponding layer which has the node associated with this region.

correspondingNodeLayer: SpinifexLayerIndex ← SpinifexLayerIndex.FIRST, -- way to attach node values to constraints by looking at other layers.

specificCorrespondingNode: REF SX.CircuitNode ← NIL -- Specific node to which constraint is connected

];

ConstraintPtr: TYPE = REF Constraint;

ConstraintArray: TYPE = ARRAY ConstraintIndex OF ConstraintPtr ← ALL[NIL];

-- This table looked up when constraints overlap other constraints or nodes.

-- The first Row (and Column) of the ARRAY (corresponding to spaceIndex) actually hold in each Column (Respectively Row) position, the Contraint having that index.

-- NIL entries in the table are defined to mean this pair should map to node and should only arise in the Column (Respectively Row) corresponding to nodeIndex.

ConstraintResolution: TYPE = ARRAY ConstraintIndex OF ConstraintArray;

NodeLinkage: TYPE = RECORD [ -- transistors

source: CD.Instance,

l, w: CD.Number, -- length, width

nodes: LIST OF REF AttachedNode ← NIL

];

AttachedNode: TYPE = RECORD [

attachmentType: ATOM, -- e.g. $Gate, $Drain, $Source

node: REF CircuitNode

];

MergeRecList: TYPE = LIST OF MergeRec;

MergeRec: TYPE = RECORD [

applChain: LIST OF CD.Instance, -- bottom up, one application per subcircuit

becomes: REF CircuitNode -- in the parent circuit

];

ConversionProc: TYPE = PROCEDURE [inst: CD.Instance, pos: CD.Position, orient: CD.Orientation, cir: REF Circuit];

BoxMapProc: TYPE = PROCEDURE [cir: REF Circuit, dim: CD.Rect, inst: CD.Instance, pos: CD.Position, orient: CD.Orientation, node: REF CircuitNode] RETURNS [cirNode: REF CircuitNode ← NIL];

maxSpinifexLayer: INTEGER = 8;

SpinifexLayerIndex: TYPE = [0..maxSpinifexLayer);

-- Constraints contain unique (for each SpinifexLayer) small integers (ConstraintIndex) which are then used to access the trigger tables in GeometricRules, the integers are relevant only within a given SpinifexLayer. Space regions map to spaceIndex and node regions map to nodeIndex. The trigger tables must be hand generated by the tech dependent client and are therefore error prone.

TechHandle: TYPE = RECORD [

numSpinifexLayers: SpinifexLayerIndex, -- Technology dependent (NMOS: 3, CMOS: 6).

spinifexLayerNames: ARRAY SpinifexLayerIndex OF LayerNames, -- For Thyme

layerInterestBloat: ARRAY SpinifexLayerIndex OF INTEGER ← ALL[0], -- (design number). Because bloat depends on material. These fields hold the maximum.

rules: ARRAY SpinifexLayerIndex OF LIST OF REF GeometricRule ← ALL[NIL],

constraintResolutions: ARRAY SpinifexLayerIndex OF REF ConstraintResolution ← ALL [NIL],

cdLayerMapping: ARRAY CD.Layer OF LIST OF MapRec ← ALL[NIL], -- Map from ChipNDale rectangles to quad-tree rectangles. A ChipNDale rectangle may map (in TranslateGeometry) to several spinifex layers, as a conductive region on one, and as contraints on other conductive regions on other spinifex layers.

illegalLayer: ARRAY CD.Layer OF BOOLEAN ← ALL[TRUE], -- To detect isolated curts that should only be used inside objects.

combineNodeProperties: CombineNodePropertyProc ← NIL, -- For technology dependent properties. For merging phase.

cellPostProcess: CellPostProcessProc ← NIL -- For technology dependent manipulation and checking. (e.g. cmos n-well connects)

];

CombineNodePropertyProc: TYPE = PROCEDURE [circuit: REF Circuit, to, from: Atom.PropList, fromNesting: LIST OF CD.Instance] RETURNS [Atom.PropList];

-- to: top level; from: deeper level

CellPostProcessProc: TYPE = PROCEDURE [cell: REF LogicalCell];

LayerNames: TYPE = RECORD [

layerId: ATOM ← NIL,

thymeName: Rope.ROPE ← NIL

];

MapRec: TYPE = RECORD [

spinifexLayer: SpinifexLayerIndex,

bloatFactor: INTEGER, -- Interest Bloat. short design number

value: REF ANY ← NIL -- There are 3 possiblities.

NIL => A new the region represents conductive material on this layer and a new node is created.

REF Constraint => region represents a constraint on other material in this layer.

REF BoxMapProc => A procedural escape for more complex rectangle mapping. (e.g. for mapping n-well)

];

-- So how does checking work? The four quads around a corner are mapped through trigger1 to TRUE/FALSE value for each quadrant. The TRUE area represents 'stuff' and if it forms a convex or concave corner a check is made of size extent into the corresponding 'non-stuff' in the FALSE region. To do a width check we map space to TRUE and the material being width checked to FALSE, thus an appropriate check is generated extending into the material. The check fails if anything in the check region maps through trigger2 to TRUE. If okIfConnected is TRUE then the violation is overidden if trigger1 and trigger2 circuit nodes and are the same.

GeometricRule: TYPE = RECORD [

extent: INTEGER,

message: Rope.ROPE ← NIL,

okIfConnected: BOOLEAN ← FALSE,

trigger1, trigger2: PACKED ARRAY ConstraintIndex OF BOOLEAN ← ALL[FALSE]

];

Stuff for Core

TechInfo: TYPE = REF TechRec;

TechRec: TYPE = RECORD [
name: Rope.ROPE,
layers: ARRAY SX.SpinifexLayerIndex OF RECORD [
id: ATOM,
thymeName: Rope.ROPE]];

END.

Edited on January 22, 1985 3:15:50 pm PST, by Beretta

Added some comments

Edited on January 30, 1985 8:19:08 pm PST, by Jacobi

Added some comments

Edited on February 25, 1985 7:45:02 pm PST, by Jacobi

Added stopFlag: REF BOOL

Edited on March 4, 1985 3:27:07 pm PST, by Shand

Spinifex DRC errors now reported through CDErrors module.

changes to: LogicalCell Changed role for errorContext field in LogicalCell RECORD.

Edited on March 7, 1985 12:52:32 pm PST, by Shand

changes to: CellPostProcessProc Added isRoot parameter., EnumerateGeometry Added defaulting to data parameter

Edited on March 9, 1985 5:22:28 pm PST, by Beretta & Shand

Improved encoding of the constraints. They now are an array and the conflicts are resolved looking up a table.

changes to: Constraint: deleted fields for constraint resolution,
ConstraintPtr: value put into the rectangles,
ConstraintResolution: table looked up when constraints overlap other constraints or nodes,
TechHandle: included constraintResolutions rather than having them referenced through the Constraint RECORD itself., LayerNames to include an id field as a debugging aid, nodeIndex & spaceIndex defined in terms of ConstraintIndex, rather than absolute INTs, techCIndexBase added to tell technology dependent clients where to start numbering from

Edited on March 10, 1985 3:33:11 pm PST, by Shand

Deleted obsolete field attached from CircuitNode. Added new field for specify the location of some point on a node (for Crystal and such programs).

Deleted obsolete fields areaAdjustment, perimAdjustment from AttachedNode, and corresponding parameters from LinkageAttach. Same effect may noe be obtained by Tech dep clients using AdjustNode.

changes to: CircuitNode, NodeLocation, LinkageAttach, AttachedNode

Edited on March 11, 1985 8:01:11 pm PST, by Shand

changes to: SignalName added default initialization to depth field., QuadTreeRoot Deleted obsolete field unsortedBoxes, QuadTree added field defaulting., spaceIndex, nodeIndex, excludeIndex, violateIndex, techCIndexBase

Edited on March 27, 1985 5:13:38 pm PST, by Beretta & Jacobi

changes to: spaceIndex, nodeIndex, excludeIndex, violateIndex, techCIndexBase

Put in explicit constants.

Edited on April 3, 1985 10:14:43 am PST, by Jacobi

changes to: module renamed to SX.

Edited on April 4, 1985 9:27:07 am PST, by Jacobi

changes to: LogicalCell, Circuit.

Edited on April 5, 1985 11:58:31 am PST, by Jacobi

changes to: LogicalCell: include rootOnInvocation field.

Edited on April 8, 1985 5:29:29 pm PST, by Jacobi

Error message stuff removed.

Edited on May 6, 1985 11:26:55 am PDT, by Beretta

Converted to ChipNDale CD20

Edited on June 4, 1985 3:41:34 pm PDT, by Beretta

Created a separate module for the Quad Tree data structure

Edited on July 8, 1985 3:54:09 pm PDT, by Beretta

Added a field to permit the output of formal parameters (ports) on root cells.

changes to: SignalName: it is set to true if there is a property Export with value $TRUE

Last edited by: gbb July 23, 1985 4:37:38 pm PDT

Added storage of length, width for transistors.

changes to: CreateLinkage: new parameters, NodeLinkage: new fields.

gbb August 7, 1985 10:48:11 am PDT

Added stuff for Core

changes to: TechInfo: new, TechRec: new