* First pass at Tamarin microcode 1/2/86
* Alan Bell;

* Second Pass 8/4/86
* Bob Krivacic;

* Other Opcodes
BLT, BITBLT
Get, Putfield;

* ------------------------------------------------------;
* Constants;
* ------------------------------------------------------;

* 'T;
Label_'T		
		EUop_D2 Tag_D2 RD2addr_T Waddr_Tos' Tos'_Tos+1 NewTos_Tos' NextInstA_Done;

Label_SetT		
		EUop_D2 Tag_D2 RD2addr_T Waddr_Tos NextInstA_Done;

* 'NIL;
Label_'Nil		
		EUop_D2 Tag_D2 RD2addr_Nil Waddr_Tos' Tos'_Tos+1 NewTos_Tos' NextInstA_Done;

Label_SetNil	
		EUop_D2 Tag_D2 RD2addr_Nil Waddr_Tos NextInstA_Done;

* '0;
Label_'0		
		EUop_D2 Tag_Int RD2addr_MuxRdSel MuxRdSel_K  K_0 Waddr_Tos' 
			Tos'_Tos+1 NewTos_Tos' NextInstA_Done;

* '1;
Label_'1		
		EUop_D2 Tag_Int RD2addr_MuxRdSel MuxRdSel_K  K_1 Waddr_Tos' 
			Tos'_Tos+1 NewTos_Tos' NextInstA_Done;

* 'UNBOUND;
Label_'Unbound	
		EUop_D2 Tag_D2 RD2addr_Unbound Waddr_Tos' Tos'_TOS+1 NewTos_TOS' NextInstA_Done;

*  SIC,SICX,ICONST;
Label_IntConst	
		EUop_D1 Tag_Int RD1addr_IBufData
 			Waddr_TOS' TOS'_TOS+1 NewTos_Tos' NextInstA_Done;
	
*  SYMBOLCONST;
Label_SymbConst	
		EUop_D2<8>Shl24/D1<24> Tag_D2<8:7> RD2addr_MuxRdSel MuxRdSel_K  K_SymbTypeBits 
			RD1addr_IBufData Waddr_TOS' TOS'_TOS+1 NewTos_Tos' NextInstA_Done;

*  FCONST;
Label_FConst		
		EUop_D2<2>Shl24/D1<30> Tag_D2<8:7> RD2addr_MuxRdSel MuxRdSel_K  K_FloatTypeBits 
			RD1addr_IBufData Waddr_TOS' TOS'_TOS+1 NewTos_Tos' NextInstA_Done;

*  XCONST;
Label_XConst		
		EUop_D2<2>Shl24/D1<30> Tag_D2<8:7> RD2addr_MuxRdSel MuxRdSel_K  K_XTypeBits 
			RD1addr_IBufData Waddr_TOS' TOS'_TOS+1 NewTos_Tos' NextInstA_Done;

*  PCONST;
Label_PConst		
		EUop_D2<2>Shl24/D1<30> Tag_D2<8:7> RD2addr_MuxRdSel MuxRdSel_K  K_PtrTypeBits 
			RD1addr_IBufData Waddr_TOS' TOS'_TOS+1 NewTos_Tos' NextInstA_Done;

* ------------------------------------------------------;
* Variable Access;
* ------------------------------------------------------;

* VARX;
Label_Varx	
		EUop_D1 Tag_D1 Raddr_IBufN Waddr_Tos' TOS'_Tos+1 NewTos_Tos' NextInstA_Done;

* VARX_;
Label_Varx_
		EUop_D1 Tag_D1 Raddr_Tos Waddr_IBufN NextInstA_Done;

* VARK;
Label_Vark	
		EUop_D1 Tag_D1 Raddr_0<4>/OpCode<4> Waddr_Tos' Tos'_Tos+1 NewTos_Tos' NextInstA_Done;

* VARK_;
Label_Vark_
		EUop_D1 Tag_D1 Raddr_Tos Waddr_0<4>/OpCode<4> NextInstA_Done;

* VARK_^;
Label_Vark_^
		EUop_D1 Tag_D1 Raddr_Tos Waddr_0<4>/OpCode<4> Tos'_Tos-1 NewTos_Tos' NextInstA_Done;

* GVAR;
Label_GVar
		EUop_+  Tag_Int RD1addr_IBufData RD2addr_MuxRdSel MuxRdSel_K K_ValueCellOffset 
			W2addr_MarD1;
		Cycle_R1 W2addr_MarMem CondCode_NoFault  NextInstB_PageFault;
		EUop_D1 Tag_D1 RD1addr_Mar Waddr_Tos' Tos'_Tos+1 NewTos_Tos' 
			CondCode_Boundp Cwrite NextInstA_Done NextInstB_Ufn-0d;

* GVAR_;
Label_GVar_
		EUop_+  Tag_Int RD1addr_IBufData RD2addr_MuxRdSel MuxRdSel_K K_ValueCellOffset 
			W2addr_MarD1;
Label_RefCountStore
		Cycle_R1 Waddr_K WCxt_K K_Decref CondCode_NoFault  NextInstB_PageFault;
		Cycle_W1 Dswap Raddr_Tos CondCode_NoFault NextInstB_PageFault;
		EUop_D1 Tag_D1 Raddr_Tos Waddr_K WCxt_K K_Incref Misc_SetRefCount NextInstA_DoJmp1;


* OVAR1.X 		(Needs precondition notframesempty, fail is ufn);
Label_Ovar1.X
		EUop_D1 Tag_D1 Raddr_IBufN RCxt_Prev Waddr_Tos' Tos'_Tos+1 NewTos_Tos'  NextInstA_Done;

* OVAR1.X_	(Needs precondition notframesempty, fail is ufn);
Label_Ovar1.X_
		EUop_D1 Tag_D1 Raddr_TOS Waddr_IBufN WCxt_Prev NextInstA_Done;

* ------------------------------------------------------;
* Free Variable References;
* ------------------------------------------------------;


*  FVARX;
Label_FVarx
		EUop_D1 Tag_D1 Raddr_IBufN W2addr_MarD1 CondCode_Boundp NextInstB_Ufn-0d;
		Cycle_R1 Waddr_Tos' Tos'_Tos+1 NewTos_TOS'
			CondCode_NoFault Cwrite NextInstA_Done NextInstB_PageFault;

* FVARX_;
Label_FVarx_
		EUop_D1 Tag_D1 Raddr_IBufN W2addr_MarD1 CondCode_Stackp NextInstB_FvarCheck;
		Cycle_W1 Dswap Raddr_Tos CondCode_NoFault Cwrite NextInstA_Done NextInstB_PageFault;

*  FVARM;
*	- Read frame extension, add offset to start of variables, trap if unbound;
*	- Read the variable cell at offset X;
*	- trap if unbound;
*	- Read the variable value;
 
Label_FVarM
		EUop_+ Tag_D1 Raddr_K K_Fx  RD2addr_MuxRdSel MuxRdSel_IBufN W2addr_MarD1
			CondCode_Boundp NextInstB_Ufn-0d;
		Cycle_R1 Waddr_K WCxt_K K_Rtmp1 CondCode_NoFault NextInstB_PageFault;
		EUop_D1 Tag_D1 Raddr_K RCxt_K K_Rtmp1 W2addr_MarD1 CondCode_Boundp NextInstB_Ufn-0d;
		Cycle_R1 Waddr_Tos' Tos'_Tos+1 NewTos_Tos' 
			CondCode_NoFault Cwrite NextInstA_Done NextInstB_PageFault;

* FVARM_;
*	- Read frame extension, add offset to start of variables, trap if unbound;
*	- Read the variable cell at offset X;
*	- trap if not a stack pointer (must ref count);
*	- Store the variable value;

Label_FVarM_
		EUop_+ Tag_D1 Raddr_K K_Fx  RD2addr_MuxRdSel MuxRdSel_IBufN W2addr_MarD1
			CondCode_Boundp NextInstB_Ufn-1d;
		Cycle_R1 Waddr_K WCxt_K K_Rtmp1 CondCode_NoFault NextInstB_PageFault;
		EUop_D1 Tag_D1 Raddr_K RCxt_K K_Rtmp1 W2addr_MarD1 CondCode_Stackp NextInstB_FvarCheck;
		Cycle_W1 Dswap Raddr_Tos CondCode_NoFault Cwrite NextInstA_Done NextInstB_PageFault;

* See if a reference counted FVAR opcode;
* (i.e. Mar is bound);

Label_FvarCheck
		RD1addr_Mar CondCode_Boundp NextInstA_RefCountStore NextInstB_Ufn-1d;



* ------------------------------------------------------;
* Internal Global Registers;
* ------------------------------------------------------;

* IREGX ;
Label_IReg.X
		EUop_D1 Tag_D1 Raddr_IBufN RCxt_K K_256 Waddr_Tos' Tos'_Tos+1 NewTos_Tos' 
			NextInstA_Done;

* IREGX_;
Label_IReg.X_
		EUop_D1 Tag_D1 Raddr_Tos Waddr_IBufN WCxt_K K_256  NextInstA_Done;	


	
* ------------------------------------------------------;
* Stack Modification
* ------------------------------------------------------;

* COPY;
Label_Copy
		EUop_D1 Tag_D1 Raddr_Tos Waddr_Tos' Tos'_Tos+1  NewTos_Tos' NextInstA_Done;

*  SWAP;
Label_Swap
		EUop_D1 Tag_D1 Raddr_Tos RD2addr_raddr-1 Waddr_Tos' Tos'_Tos-1  W2addr_MarD2;
		EUop_D1 Tag_D1 RD1addr_Mar  Waddr_Tos NextInstA_Done;

* POP;
Label_Pop
		Tos'_Tos-1 NewTos_Tos' NextInstA_Done;

* MOVETOS;
Label_MoveTos
		EUop_D1 Tag_D1 Raddr_Tos Waddr_IBufN NewTos_IBufN NextInstA_Done;

* SETTOS;
Label_SetTos
		NewTos_IBufN NextInstA_Done;

* ------------------------------------------------------;
* Type Checking ;
* ------------------------------------------------------;


* INTEGERP;
Label_Integerp
		EUop_D2 Tag_D2 Raddr_Tos Waddr_Tos RD2addr_NIL
			CondCode_~Integerp CWrite  NextInstA_Done NextInstB_Done;

* FLOATP;
Label_Floatp
		EUop_D2 Tag_D2 Raddr_Tos Waddr_Tos RD2addr_NIL
			CondCode_~Floatp CWrite  NextInstA_Done NextInstB_Done;

* POINTERP;
Label_Pointerp
		EUop_D2 Tag_D2 Raddr_Tos Waddr_Tos RD2addr_NIL
			CondCode_~Pointerp CWrite  NextInstA_Done NextInstB_Done;

* XTYPEP;
Label_Xtypep
		EUop_D2 Tag_D2 Raddr_Tos Waddr_Tos RD2addr_NIL
			CondCode_~Xtypep CWrite  NextInstA_Done NextInstB_Done;

* CONSP;
Label_Consp
		EUop_D2 Tag_D2 Raddr_Tos  Waddr_Tos RD2addr_NIL
			Condcode_~Consp  CWrite  NextInstA_Done NextInstB_Done;

* GETTYPEBITS;
Label_TypeBits
		EUop_D1<8>Shr24 Tag_Int Raddr_Tos Waddr_Tos NextInstA_Done;

* GETPTRBITS;
Label_PtrBits
		EUop_D2<8>Shl24/D1<24> Tag_D2<8:7> Raddr_Tos RD2addr_MuxRdSel MuxRdSel_K K_IntTypeBits  
			Waddr_Tos NextInstA_Done;

* SUBTYPEP.N;
Label_SubTypep
		EUop_D1<8>Shr24 Tag_Int Raddr_Tos  W2addr_Tmp1D1;
		RD2addr_Tmp1 RD1addr_IBufData
			CondCode_D1<7x>=D2<7x> NextInstA_SetT NextInstB_SetNil;

* FLAGTYPEP.N;
Label_FlagTypep
		EUop_D1<8>Shr24 Tag_Int Raddr_Tos  W2addr_Tmp1D1;
		RD2addr_Tmp1 RD1addr_IBufData
			CondCode_D1<8>=D2<8> NextInstA_SetT NextInstB_SetNil;


* SETTYPE.N;
Label_SetType
		EUop_D2<2>Shl24/D1<30> Tag_D2<8:7> Raddr_Tos RD2addr_MuxRdSel MuxRdSel_IBufN Waddr_Tos NextInstA_Done;

* SETSUBTYPE;
Label_SetSubType
		EUop_D2<8>Shl24/D1<24> Tag_D2<8:7> Dswap Raddr_Tos RD2addr_Raddr-1
			Waddr_Tos' Tos'_Tos-1 NewTos_Tos' NextInstA_Done;		


* ------------------------------------------------------;
* Binary Stack Instructions ;
* ------------------------------------------------------;

* EQ;
Label_Eq
		Raddr_Tos RD2addr_Raddr-1  Tos'_Tos-1 NewTos_Tos'
			CondCode_D1=D2 NextInstA_SetT NextInstB_SetNil;

* EQL	 ;
Label_Eql
		Raddr_Tos RD2addr_Raddr-1  Tos'_Tos-1 NewTos_Tos'
			CondCode_D1=D2 CWrite NextInstA_SetT;
		Raddr_Tos RD2addr_Raddr-1 Tos'_Tos-1 NewTos_Tos'
			CondCode_~NumberpD1D2 Cwrite NextInstA_SetNil NextInstB_Ufn-2;

* EQP EQUAL CEQUAL;
Label_Eqp
		Raddr_Tos RD2addr_Raddr-1 Tos'_Tos-1 NewTos_Tos'
			CondCode_D1=D2 CWrite NextInstA_SetT NextInstB_Ufn-2;

* GREATERP;
Label_Greater
		EUop_Diff1s Tag_Int Dswap Raddr_Tos RD2addr_Raddr-1 Tos'_Tos-1 NewTos_Tos'
			CondCode_IntegerD1D2 Cwrite NextInstB_Ufn-2;
		EUop_D2 Tag_D2 RD2addr_T Waddr_Tos
			CondCode_Greaterp Cwrite NextInstA_Done NextInstB_SetNil;


* PLUS;
Label_Plus	
		EUop_+ Tag_Int Raddr_Tos RD2addr_Raddr-1 W2addr_Tmp1D1
			CondCode_IntegerD1D2 NextInstB_Ufn-2;
		EUop_D2 Tag_Int RD2addr_Tmp1 Waddr_Tos' Tos'_Tos-1 NewTos_Tos'
			CondCode_NoOverflow CWrite NextInstA_Done NextInstB_Ufn-2;

* DIFF;
 Label_Diff
		EUop_Diff2s Tag_Int Dswap Raddr_Tos RD2addr_Raddr-1 W2addr_Tmp1D1
			CondCode_IntegerD1D2 NextInstB_Ufn-2;
		EUop_D2 Tag_Int RD2addr_Tmp1 Waddr_Tos' Tos'_Tos-1 NewTos_Tos'
			CondCode_NoOverflow CWrite NextInstA_Done NextInstB_Ufn-2;

* AND;
Label_And	
		EUop_And Tag_Int Raddr_Tos RD2addr_Raddr-1 Waddr_Tos' Tos'_Tos-1 NewTos_Tos'
			CondCode_IntegerD1D2 CWrite NextInstA_Done NextInstB_Ufn-2;

* OR;
Label_Or
		EUop_Or Tag_Int Raddr_Tos RD2addr_Raddr-1 Waddr_Tos' Tos'_Tos-1 NewTos_Tos'
			CondCode_IntegerD1D2 CWrite NextInstA_Done NextInstB_Ufn-2;

* XOR;
Label_Xor
		EUop_Xor Tag_Int Raddr_Tos RD2addr_Raddr-1 Waddr_Tos' Tos'_Tos-1 NewTos_Tos'
			CondCode_IntegerD1D2 CWrite NextInstA_Done NextInstB_Ufn-2;

* ------------------------------------------------------;
* Unary Stack Instructions ;
* ------------------------------------------------------;

* NEG;   
Label_Neg
		EUop_D2 Tag_Int Raddr_Tos RD2addr_MuxRdSel MuxRdSel_K K_0 W2addr_MarD1
			CondCode_Integerp NextInstB_Ufn-1;
		EUop_Diff2s Tag_Int Dswap Raddr_Tos RD1addr_Mar Waddr_Tos 
			CondCode_~MinIntD2 Cwrite NextInstA_Done NextInstB_Ufn-1;


* ------------------------------------------------------;
*  Shift Operations;
* ------------------------------------------------------;

* ASH;
Label_Ash	
		EUop_D1 Tag_Int Dswap Raddr_Tos RD2addr_Raddr-1 W2addr_MarD1 NewArg_D2
			CondCode_IntegerD1D2 NextInstB_Ufn-2;
		EUop_D1 Raddr_Tos CondCode_PosIntegerp  NextInstB_Arsh;

*	- Arithmetic left shift ... check shift amout;

		EUop_Diff1s Raddr_Tos RD2addr_MuxRdSel MuxRdSel_K K_29;
		CondCode_NotGreaterp NextInstB_Ufn-2;

Label_Alsh1	CondCode_Arg=0  NextInstA_Alsh2;
		EUop_Lshft1 Tag_Int RD1addr_Mar W2addr_MarD1 NewArg_Arg' Arg'_Arg-1
			Condcode_PosIntegerp NextInstA_Alsh1 NextInstB_Ufn-2;
Label_Alsh2	EUop_D1 Tag_Int RD1addr_Mar Waddr_Tos' Tos'_Tos-1 NewTos_Tos' 
			CondCode_PosIntegerp Cwrite NextInstA_Done NextInstB_Ufn-2;

*	- Arithmetic right shift ... check shift amout;

Label_Arsh	EUop_D2  Tag_Int RD2addr_MuxRdSel MuxRdSel_K K_0 W2addr_MarD1;
		EUop_Diff1s Tag_Int Dswap Raddr_Tos RD1addr_Mar 
			Waddr_K K_Rtmp1 WCxt_K W2addr_MarD1
			CondCode_Arg=0 NextInstA_Pop;
		EUop_Diff1s Tag_Int RD1addr_Mar RD2addr_MuxRdSel MuxRdSel_K K_28;
		Dswap Raddr_K K_Rtmp1 RCxt_K Tos'_Tos-1 NewTos_Tos' NewArg_D2
 			CondCode_NotGreaterp  Cwrite NextInstB_Ufn-2;
		EUop_Arsh1 Tag_Int Raddr_Tos Waddr_Tos Arg'_Arg-1 NewArg_Arg'
			CondCode_Arg=0 NextInstA_Done NextInstB_Rpt;

* LLSH.N;
Label_Llsh.N
		EUop_D1 Tag_Int Raddr_Tos W2addr_MarD1 NewArg_IBufN
			CondCode_Integerp  NextInstB_Ufn-1d;
Label_Lsh1	CondCode_Arg=0  NextInstA_Lsh2;
		EUop_Lshft1 Tag_Int RD1addr_Mar W2addr_MarD1 NewArg_Arg' Arg'_Arg-1
			Condcode_PosIntegerp NextInstA_Lsh1 NextInstB_Ufn-1d;
Label_Lsh2	EUop_D1 Tag_Int RD1addr_Mar Waddr_Tos 
			CondCode_PosIntegerp Cwrite NextInstA_Done NextInstB_Ufn-1d;

* LRSH.N;
Label_Lrsh.N
		EUop_D1 Tag_Int Raddr_Tos W2addr_MarD1 NewArg_IBufN
			CondCode_Integerp  NextInstB_Ufn-1d;
		Arg'_Arg-1 NewArg_Arg' CondCode_Arg=0 NextInstA_Done;
		EUop_Rshft1 Tag_Int Raddr_Tos Waddr_Tos NewArg_Arg' Arg'_Arg-1
			CondCode_Arg=0  NextInstA_Done NextInstB_Rpt;




* ------------------------------------------------------;
*  Address Calculation;
* ------------------------------------------------------;

* GETPTR.N;
Label_Getptr
		EUop_+ Tag_D2 Dswap Raddr_Tos RD1addr_IBufData W2addr_MarD1
			Condcode_PointerpD2 NextInstB_Ufn-1d;
		Cycle_R1 Waddr_Tos 
			CondCode_NoFault Cwrite NextInstA_Done NextInstB_PageFault;

* PUTPTR.N;
Label_Putptr
		EUop_D2 Tag_D2 Raddr_Tos RD2addr_Raddr-1 W2addr_MarD1   
			Condcode_PointerpD2  NextInstB_Ufn-2d;
		EUop_+ Tag_D1 RD1addr_Mar  RD2addr_MuxRdSel MuxRdSel_IBufN W2addr_MarD1;
		Cycle_W1 Dswap Raddr_Tos Tos'_Tos-1 NewTos_Tos' 
			CondCode_NoFault  CWrite NextInstA_Done NextInstB_PageFault;

* RPLPTR.N;
Label_Rplptr
		EUop_D2 Tag_D2 Raddr_Tos RD2addr_Raddr-1 W2addr_MarD1   
			Condcode_PointerpD2  NextInstB_Ufn-2d;
		EUop_+ Tag_D1 RD1addr_Mar  RD2addr_MuxRdSel MuxRdSel_IBufN W2addr_MarD1 
			NextInstA_RefCountStorePop;


* ADDBASE;
Label_Addbase
		EUop_+ Tag_D2 Raddr_Tos RD2addr_Raddr-1 Waddr_Tos' Tos'_Tos-1 NewTos_TOS'  
			Condcode_IntegerpD1&PointerpD2 Cwrite NextInstA_Done NextInstB_Ufn-2;



* ------------------------------------------------------;
* List Operations ;
* ------------------------------------------------------;

* CAR;
Label_Car
		EUop_D1 Tag_D1 Raddr_Tos W2addr_Mard1 CondCode_Consp NextInstB_CxrNil;
Label_GetMem
		Cycle_R1  Waddr_Tos 
			CondCode_NoFault  CWrite NextInstA_Done NextInstB_PageFault;


* CDR;
Label_Cdr
		EUop_+ Tag_D1 Raddr_Tos  RD2addr_MuxRdSel MuxRdSel_K K_1 W2addr_Mard1 
			CondCode_Consp  NextInstA_GetMem NextInstB_CxrNil;
Label_CxrNil
		EUop_D1  Raddr_Tos  RD2addr_Nil 
			Condcode_D1=D2  NextInstA_Done NextInstB_Ufn-1;

* SETF-CAR;
Label_Setf-Car
		EUop_D1 Tag_D1 Dswap Raddr_Tos RD2addr_Raddr-1 W2addr_Mard1 
			CondCode_Consp NextInstB_Ufn-2;
Label_RefCountStorePop
		Cycle_R1 Waddr_K WCxt_K K_Decref CondCode_NoFault  NextInstB_PageFault;
		Cycle_W1 Dswap Raddr_Tos CondCode_NoFault  NextInstB_PageFault;
		EUop_D1 Tag_D1 Raddr_Tos Waddr_K WCxt_K K_Incref Tos'_Tos-1 NewTos_Tos'
			Misc_SetRefCount NextInstA_DoJmp1;


* SETF-CDR;
Label_Setf-Cdr
		EUop_D1 Tag_D1 Dswap Raddr_Tos RD2addr_Raddr-1 W2addr_Mard1 
			CondCode_Consp NextInstB_Ufn-2;
		EUop_+ Tag_D1 RD1addr_Mar  RD2addr_MuxRdSel MuxRdSel_K K_1 W2addr_Mard1
			NextInstA_RefCountStorePop;



* ------------------------------------------------------;
* Call and Return;
* ------------------------------------------------------;

* FnCall;
	* This calls a function.  The IBufData is the Symbol # (address) of the symbol
	*  definition cell, where the function definition cell can be found.
 	* The function cell  is fetched to get  the function header.  The header is
	* then fetched and the PC is latched from the header and the low 3 bits
	* of N.  No more page faults are possible.  The old PC is latched and the
	* current frame becomes the callee.  The frame is set to unbind. The 
	* arguments are copied to the new frame.;  
	* NOTE: assumes UFN tables are locked into memory.

*		- Comput address of definition cell;
*		- Read the definition cell,  set # args;

Label_FnCall
	EUop_+ Tag_D1 Dswap RD1addr_IBufData RD2addr_MuxRdSel MuxRdSel_K K_DefCellOffset 
		W2Addr_MarD1;
	Cycle_R1 W2Addr_MarMem NewArg_0<4>/Opcode<4>
		CondCode_NoFault NextInstB_PageFault;

*		- Comput address of stack header, check for a ccodep;
*		- Read 1st 4 words of function definition header;
*		- Clear Stack to Unbinds;

Label_Fn1	
	EUop_+4 Tag_D1 RD1addr_Mar W2addr_MarD1 NewArg2_Arg NewArg_K K_StkHdr
		CondCode_CCodeP NextInstB_Fn5;
	Cycle_R4 WCxt_Next Waddr_Arg<6>/QW<2> 
		EUop_+4 Tag_D1 RD1addr_Mar W2addr_MarD1
		CondCode_NoFault NextInstB_PageFault;
	EUop_D2 Tag_D2 RD2addr_Unbound Waddr_K K_PVar WCxt_Next Misc_WriteOctal NewArg_Arg2;
Label_Fn2
	EUop_D2 Tag_D2 RD2addr_Nil Waddr_K K_IVar WCxt_Next Misc_WriteOctal;



* 		- Save PC into its location in the current stack frame;
*		- Set the PC of the new frame's PC + # Args;

	EUop_D2 Tag_Int RD2addr_PC Waddr_K K_Pc Misc_Oplength=0&SetInitialRefill;
	EUop_+ Tag_Int RD1addr_Mar RD2addr_MuxRdSel MuxRdSel_Arg  W2Addr_MarD1;
	Cycle_R1 Waddr_K WCxt_Next  K_Pc;
	EUop_D1 Tag_Int Raddr_K RCxt_Next K_PC W2addr_PCD1;


*		- Test for 0 paramaters, Set NewArg2 to 1st IVAR
*		- Set Arg to last IVAR position
*		- Copy the paramaters (# parms in Arg);

	EUop_D2 Tag_Int RD2addr_MuxRdSel MuxRdSel_K K_Ivar NewArg2_K W2addr_MarD1
		NewArg_Arg' Arg'_Arg-1
		CondCode_Arg#0 NextInstB_Fn3;
	EUop_+ Tag_Int RD1addr_Mar  RD2addr_MuxRdSel MuxRdSel_Arg W2addr_Tmp1D1;
	RD2addr_Tmp1 NewArg_D2;

	EUop_D1 Tag_D1 Raddr_Tos WCxt_Next Waddr_Arg
		NewTos_Tos' Tos'_Tos-1 NewArg_Arg' Arg'_Arg-1
		CondCode_Arg=Arg2  NextInstB_Rpt;

*		- Save the Stack Pointer into current stack frame;
*		- Set the SP of the new frame, switch context;

Label_Fn3
	EUop_D1<24>/D2<8> Tag_D1 RD2addr_MuxRdSel MuxRdSel_Tos Raddr_K Waddr_K K_StkHdr;
	EUop_D2 Tag_D2 Dswap Raddr_K K_StkHdr  RCxt_Next WCxt_Next NewTos_D2 
		NewTopCxt_Next  NextInstA_Done;

*	- Note: Arg must already be Stkhdr & Arg2 the # arguments
*	- Undefined function, lets Ufn to UndefFn function;
*	- Read the stack header for UndefFn;
*	- Clear the Stack;
*	- Set the Name of the Undefn function as the 1st Pvar;
*	- Go copy the other parms & call the function;

Label_Fn5	
	EUop_+4 Tag_D1 Raddr_K K_UndefFn RCxt_K W2Addr_MarD1;
	Cycle_R4 WCxt_Next Waddr_Arg<6>/QW<2> 
		EUop_+4 Tag_D1 RD1addr_Mar W2addr_MarD1
		CondCode_NoFault NextInstB_PageFault;
	EUop_D2 Tag_D2 RD2addr_Unbound Waddr_K K_PVar WCxt_Next Misc_WriteOctal NewArg_Arg2;
	EUop_D2<8>Shl24/D1<24> Tag_D2<8:7> RD1addr_IBufData RD2addr_MuxRdSel 
		MuxRdSel_K K_SymbTypeBits W2addr_Tmp1D1;
	EUop_D2 Tag_D2 RD2addr_Tmp1 Waddr_K K_PVar WCxt_Next  NextInstA_Fn2;

* ApplyFn;
*	- Check for a Ccodep & valid # args;
*	- Check for Atom# & valid # args;
*	- Get function definition cell from Atom#;

Label_ApplyFn	
	EUOp_D1 Tag_D1 Raddr_Tos RD2addr_Raddr-1  W2addr_MarD1 NewArg_D2
		CondCode_D2=Int<8&D1=CCodeP NextInstA_AFn6;
	EUOp_D1 Tag_D1 Raddr_Tos RD2addr_Raddr-1  W2addr_MarD1 NewArg_D2
		CondCode_D2=Int<8&D1=Atom NextInstB_Ufn-2;
	EUop_+ Tag_D1 RD1addr_Mar RD2addr_MuxRdSel MuxRdSel_K K_DefCellOffset W2Addr_MarD1;
	Cycle_R1 W2Addr_MarMem CondCode_NoFault NextInstB_PageFault;

*	- Bump Mar to stack header, Check for NLambdaStar;
*	- Read the stack header of function definition;
*	- Set the stack to Unbinds;
*	- Make sure the Apply Ufn is in mem if a trap on entry is set;
*	- Pop off the 2 apply args & call function;

Label_AFn6
	EUop_+4 Tag_D1 RD1addr_Mar W2addr_MarD1 NewArg_K K_StkHdr NewArg2_Arg
		CondCode_CCodeP&~NLambdaStarP NextInstB_Ufn-2;
	Cycle_R4 WCxt_Next Waddr_Arg<6>/Qw<2> Tos'_Tos-1 NewTos_Tos'
		EUop_+4 Tag_D1 RD1addr_Mar W2addr_MarD1
		CondCode_NoFault Cwrite NextInstB_PageFault;
	EUop_D2 Tag_D2 RD2addr_Unbound Waddr_K K_PVar WCxt_Next Misc_WriteOctal
 		NewArg_Arg2 Tos'_Tos-1 NewTos_Tos' NextInstA_Fn2;


* RET;
*	- Check trap on exit flag;
*	- Save the return value;
*	- Set the SP to that of the returnee's, check for trap on return;
*	- Set the PC to the returnee's, set new context;
*	- Push the return value & return;

Label_Ret	
	EUop_D1 Tag_Int Raddr_K K_StkHdr CondCode_TrapOnExit NextInstA_Ufn-1;
	EUop_D1 Tag_D1  Raddr_Tos W2addr_Tmp1D1;
	EUop_D2 Tag_Int RCxt_Prev Dswap Raddr_K K_StkHdr NewTos_D2 
		CondCode_~TrapOnReturnToD2 CWrite NextInstB_Ufn-1;
	EUop_D1 Tag_Int RCxt_Prev Raddr_K K_Pc W2Addr_PcD1 NewTopCxt_Prev 
		Misc_Oplength=0&SetInitialRefill;
	EUop_D2 Tag_D2 RD2addr_Tmp1 Waddr_Tos' Tos'_Tos+1 NewTos_Tos'  NextInstA_Done;

* RETNP;
*	- Check trap on exit flag;
*	- Set the SP to that of the returnee's;
*	- Set the PC to the returnee's, set new context;

Label_Retnp	
	EUop_D1 Tag_Int Raddr_K K_StkHdr CondCode_TrapOnExit NextInstA_Ufn-0;
	EUop_D1 Tag_Int RCxt_Prev Raddr_K K_Pc W2Addr_PcD1 NewTopCxt_Prev 
		Misc_Oplength=0&SetInitialRefill;
	Dswap Raddr_K K_StkHdr NewTos_D2 NextInstA_Done;


* RETEI;
*	- Check for trap on exit;
*	- Set returnee's SP, enable interrupts;
*	- Set returnee's PC, set new context;

Label_Retei
	Raddr_K K_StkHdr CondCode_TrapOnExit NextInstA_Ufn-0;
	EUop_D1 Tag_Int RCxt_Prev Raddr_K K_Pc W2Addr_PcD1 NewTopCxt_Prev 
		Misc_Oplength=0&SetInitialRefill;
	Dswap Raddr_K K_StkHdr NewTos_D2 NextInstA_Enbint;

* ------------------------------------------------------;
*  UFN handling;
* ------------------------------------------------------;

* UFN;
Label_Ufn-0	NewArg_K K_0 CondCode_FramesFull NextInstA_UfnDump NextInstB_Ufn;
Label_Ufn-1	NewArg_K K_1 CondCode_FramesFull NextInstA_UfnDump NextInstB_Ufn; 
Label_Ufn-2	NewArg_K K_2 CondCode_FramesFull NextInstA_UfnDump NextInstB_Ufn;
Label_Ufn-3	NewArg_K K_3 CondCode_FramesFull NextInstA_UfnDump NextInstB_Ufn;

Label_Ufn-0d	NewArg_K K_1 CondCode_FramesFull NextInstA_UfnDump NextInstB_Ufn-Dat; 
Label_Ufn-1d	NewArg_K K_2 CondCode_FramesFull NextInstA_UfnDump NextInstB_Ufn-Dat; 
Label_Ufn-2d	NewArg_K K_3 CondCode_FramesFull NextInstA_UfnDump NextInstB_Ufn-Dat; 

Label_Ufn-Dat
		EUop_+ Tag_D1 Raddr_K K_Ufnbase RCxt_K RD2Addr_MuxRdSel MuxRdSel_Opcode 
			W2addr_MarD1;
		Cycle_R1 W2addr_MarMem  CondCode_NoFault NextInstB_PageFault;
		EUop_D1 Tag_Int RD1addr_IBufData Waddr_Tos' Tos'_Tos+1 NewTos_Tos' NextInstA_Fn1;

Label_Ufn
		EUop_+ Tag_D1 Raddr_K K_Ufnbase RCxt_K RD2Addr_MuxRdSel MuxRdSel_Opcode 
			W2addr_MarD1;
		Cycle_R1 W2addr_MarMem CondCode_NoFault NextInstA_Fn1 NextInstB_PageFault;

Label_UfnDump	Misc_OpLength=0 NextInstA_DumpFrame;


* ------------------------------------------------------;
*  Page Faults;
* ------------------------------------------------------;

* NOTE: 	This should NEVER occur ..... and we should so something special here, 
* 		like going to special Fn & clearing frames.;

Label_DumpPageFault
		NextInstA_DumpPageFault;

* Normal page fault handler.  Set fault address and call the page fault routine;

Label_PageFault
		EUop_D1 Tag_Int RD1addr_Mar Waddr_Tos' Tos'_Tos+1 NewTos_Tos' NewArg_K K_1 
			Misc_OpLength=0 CondCode_FramesAvail Cwrite NextInstB_DumpFrame;
		EUop_D1 Tag_D1 Raddr_K K_PFCode RCxt_K W2addr_MarD1 NextInstA_Fn1;

* ------------------------------------------------------;
*  Special Precondition Functions;
* ------------------------------------------------------;


* REFRESH	Cycle through all of the internal registers;
Label_Refresh
		NewArg_K K_0 Misc_ResetRefresh;
		NewArg2_K K_39 Misc_Reset-Vmm;
		EUop_D1 Tag_D1 RCxt_K WCxt_K K_0 Raddr_Arg Waddr_Arg Arg'_Arg+1 NewArg_Arg'
			CondCode_Arg=Arg2 NextInstB_Rpt;
		NewArg_K K_0;
		EUop_D1 Tag_D1 RCxt_K WCxt_K K_64 Raddr_Arg Waddr_Arg Arg'_Arg+1 NewArg_Arg'
			CondCode_Arg=Arg2 NextInstB_Rpt;
		NewArg_K K_0;
		EUop_D1 Tag_D1 RCxt_K WCxt_K K_128  Raddr_Arg Waddr_Arg Arg'_Arg+1 NewArg_Arg'
			CondCode_Arg=Arg2 NextInstB_Rpt;
		NewArg_K K_0;
		EUop_D1 Tag_D1 RCxt_K WCxt_K K_192 Raddr_Arg Waddr_Arg Arg'_Arg+1 NewArg_Arg'
			CondCode_Arg=Arg2 NextInstB_Rpt;
		NewArg_K K_0;
		EUop_D1 Tag_D1 RCxt_K WCxt_K K_256 Raddr_Arg Waddr_Arg Arg'_Arg+1 NewArg_Arg'
			CondCode_Arg=Arg2 NextInstA_Done NextInstB_Rpt;


	* This initilizes the machine by setting the PC to 0 and then
	* starting the machine.  May have to be careful that it can load
	* PC directly before DONE.;

Label_Reset 
		Misc_Reset EUop_D2 Tag_Int RD2addr_MuxRdSel MuxRdSel_K K_0 NewArg_K 
			W2addr_PcD1 NewBotCxt_K NewtopCxt_K;
		EUop_D2 Tag_Int RD2addr_MuxRdSel MuxRdSel_Arg Waddr_K WCxt_K K_IrqCount;
		K_Pvar NewTos_K  NextInstA_Done;



Label_Interrupt
		EUop_D1 Tag_D1 Raddr_K K_IntCode RCxt_K W2addr_MarD1 Misc_ResetInterrupt;
		Misc_ResetInterruptenable  NewArg_K K_0;
		EUop_Diff1s Tag_Int Raddr_K RCxt_K RD2addr_MuxRdSel MuxRdSel_Arg 
			Waddr_K WCxt_K K_IrqCount NextInstA_Fn1;


Label_AdjustFrames
		EUop_D1 Tag_D1 Raddr_K K_FrameFlagCode RCxt_K W2addr_MarD1 Misc_Resetstackrefill;
		NewArg_K K_0 NextInstA_Fn1;


Label_RefCount
		EUop_D1 Tag_D1 Raddr_K K_RefCountCode RCxt_K W2addr_MarD1;
		EUop_D1 Tag_D1 Raddr_K RCxt_K K_Decref Waddr_Tos' Tos'_Tos+1 NewTos_Tos';
		EUop_D1 Tag_D1 Raddr_K RCxt_K K_Incref Waddr_Tos' Tos'_Tos+1 NewTos_Tos';
		Misc_ResetRefcount NewArg_K K_2 NextInstA_Fn1;
* ------------------------------------------------------;
* Instruction Fetch;
* ------------------------------------------------------;


	* This performs a IBuf reload by doing a quadword fetch at the
	* correct location.  PcAddr logic does most of the real work.;

Label_LoadIBuf
		Cycle_R4 RD1addr_PcAddr W2addr_IBufD2PcD1 EUop_+16 Tag_Int
			Misc_ResetInitialRefill 
			CondCode_NoFault NextInstA_Done NextInstB_IBufPageFault;


	* LoadIBuf page fault routine.  Setup correct page fault address for page fault code ;

Label_IBufPageFault
		EUop_D1 Tag_Int RD1addr_PcAddr W2addr_MarD1;
		EUop_Rshft1 Tag_Int RD1addr_Mar W2addr_MarD1;
		EUop_Rshft1 Tag_Int RD1addr_Mar W2addr_MarD1 NextInstA_PageFault;



* ------------------------------------------------------;
* Other Special Opcodes;
* ------------------------------------------------------;


Label_Stop 	Misc_Stop NextInstA_Stop;


Label_Reset-Vmm
		Misc_Reset-Vmm NextInstA_Done;


Label_WriteOctNil
		EUop_D2 Tag_D2 RD2addr_Nil Waddr_IBufN Misc_WriteOctal NextInstA_Done;


Label_WriteOctUnbound
		EUop_D2 Tag_D2 RD2addr_Unbound Waddr_IBufN  Misc_WriteOctal NextInstA_Done;


Label_SetMemLock
		Misc_SetMemLock NextInstA_Done;

Label_ClrMemLock
		Misc_ResetMemLock NextInstA_Done;


Label_SetOutputInt
		Misc_SetOutputInt NextInstA_Done;

Label_ClrOutputInt
		Misc_ResetOutputInt NextInstA_Done;


* DISINT;
Label_Disint
		NewArg_K K_1 Misc_resetinterruptenable;
		EUop_Diff2s Tag_Int Raddr_K RCxt_K Waddr_K WCxt_K K_IrqCount 
			RD2addr_MuxRdSel MuxRdSel_Arg NextInstA_Done;

* ENBINT;
* IrqCount values:
*	1   	not disabled
*	0   	1 disable
*	-1	2 disables
*	-2	3 disables
*	etc.	;
Label_Enbint 
		NewArg_K K_1;
		EUop_+ Tag_Int Raddr_K RCxt_K K_IrqCount Waddr_K WCxt_K
			RD2addr_MuxRdSel MuxRdSel_Arg
			CondCode_~PosIntegerp Cwrite NextInstA_Done;
		EUop_D2 Tag_Int RD2addr_MuxRdSel MuxRdSel_Arg K_IrqCount Waddr_K WCxt_K
			Misc_setinterruptenable  NextInstA_Done;

* MYCLINK;
Label_MyClink
		EUop_D1 Tag_D1 Raddr_K K_Clink Waddr_Tos' Tos'_Tos+1 NewTos_Tos' NextInstA_Done;

* MYCLINK_;
Label_MyClink_ 
		EUop_D1 Tag_D1 Raddr_Tos Waddr_K K_Clink  NextinstA_Done;  



* ------------------------------------------------------;
*  Stack Frame Swapping;
* ------------------------------------------------------;

* LOAD;
	* This loads the previous frame. 
	*  Assumes:	only executed on a return.
	*		no further page faults on frame after 1st quadword.
	*  -  It sets free and MAR to the current frame's clink + 4 (to index start of stack data).
	*  -  It does a quad word load (to get TOS) & Sets Newarg to 0.
	*  -  It sets up loop count & checks for TrapOnReturn to flag, Also sets Botom = In.
	*  -  It repeats quad word loads till past the TOS. ;

Label_LoadFrame
	EUop_+4 Tag_D1 Raddr_K K_CLink W2Addr_MarD1;
	NewArg_K K_0;
	Cycle_R4 EUop_+4 Tag_D1 RD1addr_MAR W2Addr_MarD1 Waddr_Arg<6>/QW<2> WCxt_Prev
		NewArg_K K_4
		CondCode_NoFault Cwrite NextInstB_PageFault;
	Dswap Raddr_K K_StkHdr  RCxt_Prev NewArg2_D2<6>/0<2> NewBotCxt_Bot=In;
	Cycle_R4 EUop_+4 Tag_D1 RD1addr_MAR W2Addr_MarD1 Waddr_Arg<6>/QW<2>
		WCxt_Prev Arg'_Arg+4 NewArg_Arg' 
		CondCode_Arg=Arg2  NextInstA_Done NextInstB_Rpt;   

* DUMP;
	* This dumps the last frame.  
	*  -  Get the next free pointer by following the Clink of the last frame.
	*  -  Read the free pointer from memory.
	*  -  Save the free frame's address.
	*  -  Add 4 to the free pointer setting MAR, get the SP of the prev frame and set NewArg2.
	*  -  Write quad words till past the SP (in NewArg2).
	*  -  Set the new bottom context.
	*  -  Set the Clink of the new last frame to that of the frame we just wrote out. Check "last frame" tag.
	*  -  Note exception for frame overflow. ;
	*  -  NOTE: an extra instruction to get Clink + NextLink;

Label_DumpFrame
	EUop_D1 Tag_D1 Raddr_K K_Clink RCxt_Last W2addr_MarD1;
	EUop_+ Tag_D1 RD1addr_Mar RD2addr_MuxRdSel MuxRdSel_K K_NextLink W2addr_MarD1;
	Cycle_R1 W2Addr_MarMem CondCode_NoFault Cwrite NextInstB_DumpPageFault;
	EUop_D1 Tag_D1 RD1addr_Mar W2addr_Tmp1D1;
	EUop_+4 Tag_D1 Dswap RD1addr_Mar W2Addr_MarD1 Raddr_K K_StkHdr 
		NewArg2_D2<6>/0<2> RCxt_Last;
	Cycle_W1 Dswap Raddr_K RCxt_Last CondCode_NoFault  NextInstB_DumpPageFault NewArg_K K_0;
	Cycle_W4 Dswap Raddr_Arg<6>/QW<2> RCxt_Last
		EUop_+4 Tag_D1 RD1addr_MAR W2Addr_MarD1 
		Arg'_Arg+4 NewArg_Arg' CondCode_Arg=Arg2 NextInstB_Rpt;
	NewBotCxt_Bot=Out;
	EUop_D2 Tag_D2 RD2addr_Tmp1 Waddr_k K_Clink WCxt_Last Condcode_NoFlagBitD2 NextInstA_Done;
	Misc_setstackrefill  NextInstA_DoJmp1;

* ------------------------------------------------------;
* Jumps;
* ------------------------------------------------------;

* NOPx;
Label_DoJmp1 
		NextInstA_Done;

* JUMPK;
Label_Jumpk
		EUop_D2 Tag_Int RD2addr_PC W2addr_MarD1 NewArg_0<4>/Opcode<4> 
			Misc_Oplength=0&SetInitialRefill;
		EUop_+ Tag_Int RD1addr_Mar RD2addr_MuxRdSel MuxRdSel_Arg W2addr_PCD1 NextInstA_Dojmp1;

* TJUMPK;
Label_Tjumpk
		EUop_nop Raddr_Tos Tos'_Tos-1 NewTos_Tos' Rd2addr_Nil
			Condcode_D1=D2 NextInstA_Done NextInstB_Jumpk;
* FJUMPK;
Label_Fjumpk
		EUop_nop Raddr_Tos Tos'_Tos-1 NewTos_Tos' Rd2addr_Nil
			Condcode_D1#D2 NextInstA_Done NextInstB_Jumpk;

* JUMPX, JUMPXX;
Label_DoJmp 
		EUop_+ Tag_Int RD2addr_PC RD1addr_IBufData W2addr_PCD1 
			Misc_Oplength=0&SetInitialRefill NextInstA_Dojmp1;

* TJUMP;
Label_TJump 
		EUop_nop Raddr_Tos Tos'_Tos-1 NewTos_Tos' Rd2addr_Nil
			Condcode_D1=D2 NextInstA_Done NextInstB_DoJmp;

* FJUMP;
Label_FJump 
		EUop_nop Raddr_Tos Tos'_Tos-1 NewTos_Tos' Rd2addr_Nil
			Condcode_D1#D2 NextInstA_Done NextInstB_DoJmp;

* NTJUMP;
Label_NTJump
		 EUop_nop Raddr_Tos Tos'_Tos-1 NewTos_Tos' Rd2addr_Nil
			Condcode_D1=D2 CWrite NextInstA_Done NextInstB_DoJmp;

* NFJUMP;
Label_NFJump 
		EUop_nop Raddr_Tos  Rd2addr_Nil Tos'_Tos-1 NewTos_Tos' 
			Condcode_D1#D2  Cwrite NextInstA_Done NextInstB_DoJmp;

* NJUMPX, NJUMPXX;
Label_Njumpx
		EUop_D1 Tag_Int RD2addr_PC RD1addr_IBufData Waddr_K WCxt_K K_Rtmp1 W2addr_MarD2 
			Misc_Oplength=0&SetInitialRefill;
		EUop_Diff2s Tag_Int Dswap Raddr_K RCxt_K K_Rtmp1 RD1addr_Mar W2addr_PCD1 NextInstA_Dojmp1;


* ------------------------------------------------------;


End;




OpNbr_00Q ModStartAddr
	Opname_-X-			Start_Ufn-0
	Opname_STOP		Start_Stop
	Opname_INTEGERP		Start_Integerp
	Opname_FLOATP		Start_Floatp
	Opname_POINTERP		Start_Pointerp
	Opname_XTYPEP		Start_Xtypep
	Opname_CONSP		Start_Consp
	Opname_GETTYPEBITS	Start_Typebits
	Opname_GETPTRBITS	Start_Ptrbits
	Opname_SETSUBTYPE 	Start_SetSubType 
	Opname_EQ 			Start_Eq 
	Opname_EQL			Start_Eql
	Opname_EQP			Start_Eqp
	Opname_CAR			Start_Car 
	Opname_CDR			Start_Cdr
	Opname_SETF-CAR		Start_Setf-Car
   Length_1;

OpNbr_20Q ModStartAddr
	Opname_LOGAND		Start_And
	Opname_LOGOR		Start_Or 
	Opname_LOGXOR		Start_Xor
	Opname_POP			Start_Pop 
	Opname_COPY		Start_Copy
	Opname_SWAP		Start_Swap
	Opname_'NIL 		Start_'Nil
	Opname_'T			Start_'T 
	Opname_'UNBOUND		Start_'Unbound
	Opname_'0			Start_'0
	Opname_'1			Start_'1
	Opname_DISINT		Start_DisInt
	Opname_ENBINT		Start_EnbInt
	Opname_ADDBASE		Start_Addbase
	Opname_ASH			Start_Ash
	Opname_NEG			Start_Neg
   Length_1;

OpNbr_40Q ModStartAddr
	Opname_GETBASEPTR.N	Start_Getptr 
	Opname_PUTBASEPTR.N	Start_Putptr
	Opname_RPLPTR.N		Start_Rplptr
	Opname_SETTYPE.N	Start_SetType
	Opname_IREGX		Start_IReg.X
 	Opname_IREGX_		Start_IReg.x_
	Opname_VARX		Start_VarX 
	Opname_VARX_		Start_VarX_
	Opname_FVARX		Start_FVarX
	Opname_FVARX_		Start_FVarX_ 
	Opname_FVARM		Start_Fvarm
	Opname_FVARM_		Start_Fvarm_
	Opname_SUBTYPEP.N	Start_SubTypep
	Opname_FLAGTYPEP.N	Start_FlagTypep
	Opname_LLSH.N  		Start_Llsh.N
	Opname_LRSH.N  		Start_Lrsh.N
   Length_2;

OpNbr_60Q ModStartAddr
	Opname_MOVETOS		Start_MoveTos 
	Opname_SETTOS		Start_SetTos
	Opname_JUMPX		Start_DoJmp 
 	Opname_NJUMPX		Start_Njumpx
	Opname_TJUMPX		Start_TJump
	Opname_FJUMPX		Start_FJump 
	Opname_NTJUMPX		Start_NTjump
	Opname_NFJUMPX		Start_NFjump
   Length_2;

OpNbr_70Q ModStartAddr
	Opname_GVAR		Start_GVar
	Opname_GVAR_		Start_Gvar_
   Length_4;
OpNbr_72Q	Opname_ACONST 		Start_SymbConst	Length_4;
OpNbr_73Q	Opname_SETF-CDR	Start_Setf-Cdr		Length_1;
OpNbr_74Q	Opname_RESET-VMM	Start_Reset-Vmm	Length_1;
OpNbr_75Q	Opname_SICX  		Start_IntConst  	Length_2;
OpNbr_76Q	Opname_SICXX		Start_IntConst 	Length_3;
OpNbr_77Q	Opname_PUTBASEBYTE	Start_Ufn-3		Length_1;


OpNbr_100Q ModStartAddr
	Opname_OVAR.N.X		Start_Ufn-0d
	Opname_OVAR.N.X_		Start_Ufn-1d
   Length_3;

OpNbr_102Q 
	Opname_GREATERP
	Opname_IGREATERP
   Length_1	Start_Greater;

OpNbr_104Q	
	Opname_PLUS
	Opname_IPLUS
   Length_1	Start_Plus;

OpNbr_106Q
	Opname_DIFFERENCE
	Opname_IDIFFERENCE
   Length_1	Start_Diff;

OpNbr_110Q 
	Opname_EQUAL
	Opname_CEQUAL
   Length_1	Start_Eqp;

OpNbr_112Q	Opname_JUMPXX	Start_DoJmp 		Length_3;
OpNbr_113Q	Opname_NJUMPXX	Start_Njumpx		Length_3;



OpNbr_114Q ModStartAddr
	Opname_SETOUTPUTINT	Start_SetOutputInt
	Opname_CLROUTPUTINT	Start_ClrOutputInt
	Opname_SETMEMLOCK	Start_SetMemLock
	Opname_CLRMEMLOCK	Start_ClrMemLock
   Length_1;

OpNbr_120Q
	Opname_CONTEXTSWITCH
	Opname_GETTYPEINDEX
	Opname_UDF0-1
	Opname_UDF1-1
	Opname_UDF2-1
	Opname_UDF3-1
	Opname_UDF4-1
	Opname_UDF5-1
   Length_1	Start_Ufn-1;



OpNbr_130Q 
	Opname_UDF0-1d3
	Opname_UDF1-1d3
	Opname_UDF2-1d3
	Opname_UDF3-1d3
	Opname_UDF4-1d3
	Opname_UDF5-1d3
	Opname_UDF6-1d3
	Opname_DTEST.O
   Length_4	Start_Ufn-1d;


	
OpNbr_140Q
	Opname_TIMES	
	Opname_ITIMES
	Opname_QUOTIENT	
	Opname_IQUOTIENT
	Opname_IREMAINDER
	Opname_GETBASEBYTE
	Opname_CONS	
	Opname_RPLCONS
	Opname_UDF0-2
	Opname_UDF1-2 
	Opname_UDF2-2
	Opname_UDF3-2 
	Opname_UDF4-2
	Opname_UDF5-2
	Opname_UDF6-2
	Opname_UDF7-2
   Length_1 	Start_Ufn-2;



OpNbr_160Q	OpCnt_8 	Precond_NotFramesFull
	Opname_FN0 		Opname_FN1
	Opname_FN2 		Opname_FN3 
	Opname_FN4 		Opname_FN5
	Opname_FN6 		Opname_FN7 
   Length_4 Start_Fncall;
Opnbr_160Q OpCnt_8 Precond_FramesFull Length_0 Start_DumpFrame;


Opnbr_170Q ModStartAddr	Precond_NotFramesEmpty
	Opname_RETURN 		Start_Ret 
	Opname_RETEI		Start_Retei
   Length_1;
Opnbr_170Q	OpCnt_2		Start_LoadFrame	Length_0	Precond_FramesEmpty;

OpNbr_172Q  ModStartAddr	PreCond_NotFramesEmpty
	Opname_OVAR1.X		Start_Ovar1.X 
	Opname_OVAR1.X_	Start_Ovar1.X_
   Length_2;
OpNbr_172Q	OpCnt_1		Start_Ufn-0d		Length_0	PreCond_FramesEmpty;
OpNbr_173Q	OpCnt_1		Start_Ufn-1d		Length_0	PreCond_FramesEmpty;

OpNbr_174Q	Opname_RETNP 	Start_Retnp		Length_1 	PreCond_NotFramesEmpty;
OpNbr_174Q	OpCnt_1		Start_LoadFrame	Length_0 	PreCond_FramesEmpty;

Opnbr_175Q 	Opname_APPLYFN	Start_ApplyFn		Length_1  	Precond_NotFramesFull;
Opnbr_175Q 	OpCnt_1 	Start_DumpFrame	Length_0	Precond_FramesFull;

Opnbr_176Q	
	Opname_UDF4-3
	Opname_UDF5-3
   Length_1	Start_Ufn-3;

OpNbr_200Q
	Opname_UDF8-2
	Opname_UDF9-2 
	Opname_UDF10-2
	Opname_UDF11-2 
   Length_1 	Start_Ufn-2;

OpNbr_204Q
	Opname_UDF0-0
	Opname_UDF1-0
	Opname_UDF2-0
	Opname_UDF3-0
   Length_1	Start_Ufn-0;


OpNbr_210Q
	Opname_VAR8_^	Opname_VAR9_^
	Opname_VAR10_^	Opname_VAR11_^
	Opname_VAR12_^	Opname_VAR13_^
	Opname_VAR14_^	Opname_VAR15_^
   Length_1 	Start_VarK_^;

OpNbr_220Q ModStartAddr
	Opname_PCONST		Start_PConst
	Opname_ICONST		Start_IntConst
	Opname_FCONST		Start_FConst
	Opname_XCONST		Start_XConst
   Length_5;

Opnbr_224Q ModStartAddr	Precond_FramesEmpty
	Opname_MYCLINK		Start_MyClink
	Opname_MYCLINK_	Start_MyClink_
   Length_1;
Opnbr_224Q	OpCnt_2 	Length_0	Start_DumpFrame	Precond_NotFramesEmpty;

OpNbr_226Q ModStartAddr
	Opname_WRITEOCTNIL.N		Start_WriteOctNil
	Opname_WRITEOCTUNBOUND.N	Start_WriteOctUnbound
   Length_2;

OpNbr_230Q
	Opname_UDF0-2d 	Opname_UDF1-2d
	Opname_UDF2-2d 	Opname_UDF3-2d
	Opname_UDF4-2d 	Opname_UDF5-2d
	Opname_UDF6-2d 	Opname_UDF7-2d
   Length_2 Start_Ufn-2d;


OpNbr_240Q
	Opname_UDF4-1d		Opname_UDF5-1d	
	Opname_UDF6-1d		Opname_UDF7-1d
	Opname_UDF8-1d		Opname_UDF9-1d
	Opname_UDF10-1d	Opname_UDF11-1d
	Opname_UDF12-1d	Opname_UDF13-1d	
	Opname_UDF14-1d	Opname_UDF14-1d
	Opname_UDF16-1d	Opname_UDF15-1d
	Opname_UDF17-1d	Opname_UDF18-1d
   Length_2 	Start_Ufn-1d;

OpNbr_260Q
	Opname_UDF0-0d
	Opname_UDF1-0d
	Opname_UDF2-0d
	Opname_UDF3-0d
	Opname_UDF4-0d
	Opname_UDF5-0d
	Opname_UDF6-0d
	Opname_UDF7-0d
   Length_2	Start_Ufn-0d;


OpNbr_270Q
	Opname_VAR8_		Opname_VAR9_
	Opname_VAR10_		Opname_VAR11_
	Opname_VAR12_		Opname_VAR13_
	Opname_VAR14_		Opname_VAR15_
   Length_1 	Start_VarK_;


OpNbr_300Q
	Opname_UDF0-3
	Opname_UDF1-3
	Opname_UDF2-3
	Opname_UDF3-3
   Length_1 Start_Ufn-3;

OpNbr_304Q
	Opname_UDF0-1d
	Opname_UDF1-1d
	Opname_UDF2-1d
	Opname_UDF3-1d
   Length_2	Start_Ufn-1d;


OpNbr_310Q
	Opname_VAR8 		Opname_VAR9
	Opname_VAR10		Opname_VAR11
	Opname_VAR12		Opname_VAR13
	Opname_VAR14		Opname_VAR15
   Length_1 	Start_VarK;

Opnbr_320Q
	Opname_FJUMP0		Opname_FJUMP1
	Opname_FJUMP2		Opname_FJUMP3
	Opname_FJUMP4		Opname_FJUMP5
	Opname_FJUMP6		Opname_FJUMP7
	Opname_FJUMP8		Opname_FJUMP9
	Opname_FJUMP10		Opname_FJUMP11
	Opname_FJUMP12		Opname_FJUMP13
	Opname_FJUMP14		Opname_FJUMP15
   Length_1	Start_Fjumpk;


Opnbr_340Q
	Opname_TJUMP0		Opname_TJUMP1
	Opname_TJUMP2		Opname_TJUMP3
	Opname_TJUMP4		Opname_TJUMP5
	Opname_TJUMP6		Opname_TJUMP7
	Opname_TJUMP8		Opname_TJUMP9
	Opname_TJUMP10		Opname_TJUMP11
	Opname_TJUMP12		Opname_TJUMP13
	Opname_TJUMP14		Opname_TJUMP15
   Length_1	Start_Tjumpk;

Opnbr_360Q Opname_NOP  Length_1 Start_DoJmp1;
Opnbr_361Q Opname_NOP1 Length_2 Start_DoJmp1;
Opnbr_362Q Opname_NOP2 Length_3 Start_DoJmp1;
Opnbr_363Q Opname_NOP3 Length_4 Start_DoJmp1;
Opnbr_364Q Opname_NOP4 Length_5 Start_DoJmp1;
Opnbr_365Q Opname_JUMP5 Length_1 Start_Jumpk;
OpNbr_366Q 
	Opname_JUMP6		Opname_JUMP7
   Length_1	Start_Jumpk;
OpNbr_370Q 
	Opname_JUMP8		Opname_JUMP9
	Opname_JUMP10		Opname_JUMP11
	Opname_JUMP12		Opname_JUMP13
	Opname_JUMP14		Opname_JUMP15
   Length_1	Start_Jumpk;



Opnbr_0 OpCnt_256 PreCond_Reset Length_0 Start_Reset ForceNewOp;


Opnbr_0 OpCnt_256
	PreCond_Refresh
	PreCond_NotReset
   Length_0 Start_Refresh;




Opnbr_0 OpCnt_256
	PreCond_RefCount
	PreCond_NotReset
	PreCond_NotRefresh
	PreCond_NotFramesFull
   Length_0 Start_RefCount;

Opnbr_0 OpCnt_256 
 	PreCond_RefCount 
	PreCond_NotReset
	PreCond_NotRefresh
	PreCond_FramesFull
   Length_0 Start_DumpFrame;


Opnbr_0 OpCnt_256
	PreCond_StackRefill
	PreCond_NotReset
	PreCond_NotRefresh
	PreCond_NotRefCount
	PreCond_NotFramesFull
   Length_0 Start_AdjustFrames;

Opnbr_0 OpCnt_256
	PreCond_StackRefill
	PreCond_NotReset
	PreCond_NotRefresh
	PreCond_NotRefCount
	PreCond_FramesFull
   Length_0 Start_DumpFrame;



Opnbr_0 OpCnt_256 
 	PreCond_Interrupt 
	PreCond_NotReset
	PreCond_NotRefresh
	PreCond_NotRefCount
	PreCond_NotStackRefill
	PreCond_NotFramesFull
   Length_0 Start_Interrupt;

Opnbr_0 OpCnt_256 
 	PreCond_Interrupt 
	PreCond_NotReset
	PreCond_NotRefresh
	PreCond_NotRefCount
	PreCond_NotStackRefill
	PreCond_FramesFull
   Length_0 Start_DumpFrame;

Opnbr_0 OpCnt_256  
	PreCond_Refill
	PreCond_NotReset 	
	PreCond_NotRefresh
	PreCond_NotRefCount
	PreCond_NotStackRefill
	PreCond_NotInterrupt
   Length_0 Start_LoadIbuf;


End;

GACHA™
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