(FILECREATED "18-May-87 10:32:58" {ERIS}<TAMARIN>UCODE>TAMARINEMULATOR.;214 62119
changes to: (FNS DoRegMux ClockRdMux DoTest InitEmulator CxtOp LoadIBufByte)
(VARS TAMARINEMULATORCOMS VarsList)
previous date: "17-Dec-86 16:59:35" {ERIS}<TAMARIN>UCODE>TAMARINEMULATOR.;209)
(* Copyright (c) 1985, 1986, 1987 by Xerox Corporation. All rights reserved.)
(PRETTYCOMPRINT TAMARINEMULATORCOMS)
(RPAQQ TAMARINEMULATORCOMS ((* * Top Level - Abbreviations - $ = OP - # = Micro - * = Pre - @ =
Clock)
(FNS DoCycle SetClocks GateClocks DoCombLogic DoPhiPrecharge DoCombLogicPrecharge
DoPhiClockRW DoPhiClockUOp)
(* * Clock Pla)
(FNS DoClock ClockClock PrechargeClock MakeClockPla2)
(* * Register Mux)
(FNS DoRegMux CxtOp DoRegMuxB ClockRdMux)
(* * Register Access)
(FNS DecodeRegAddr ReadRegister WriteRegister PrechargeRegister ClockReadRegister
ClockWriteRegister)
(* * Special Register Read Access)
(FNS ReadRD1 ReadRD2 ReadPc ClockReadSpecial)
(* * Special Register Write Access)
(FNS PrepareWrite WriteSpecial WriteIBufWord PrechargeWriteSpecial ClockWriteSpecial)
(* * Virtual Memory)
(FNS PrepareDecode DoVMM DoRCMux ResetVMM Write-VMM ClockVMM)
(* * Memory Access)
(FNS ClockMemRead ClockMemWrite DoMemory ClockMemAddr ClockD10MemAddr ClockD35MemAddr
PrechargeMem)
(* * Execution Units)
(FNS NormalCycle CombTagD2 PrechargeEU ClockEUR ClockEUW)
(* * Condition Code in Data Path)
(FNS CheckCondA MakeCondCodeArray)
(* * Next Opcode Functions)
(FNS DoIBuf SelectIBufByte LoadIBufByte IBufData ClockIBuf)
(* * Micro Control)
(FNS ClockSNI SelNextInst OpPla GetUCode DoCCode1 DoCCode2 DoCCode3 CheckCondB CheckCondC)
(* * Misc Actions)
(FNS DoMisc ClockMisc MakeMiscPla PrechargeSync ClockSync)
(* * Config)
(FNS TamRep TamTagRep)
(* * INIT)
(FNS DoTest InitEmulator ActOnMem)
(* * UCode fields)
(PROP uField addr label newbotcxt rcxt rd1addr rd2addr wcxt cycle euop tag w2addr dswap raddr
waddr newarg newarg2 newtopcxt newtos arg' tos' k condcode muxrdsel cwrite nextinsta
nextinstb misc)
(* * OpPla Fields)
(PROP uField2 forcenewop length modstartaddr opcnt opname opnbr precond start)
(RECORDS MI OpD CondCode)
(VARS InitVarLst fulltagmsk tagmsk fulltag&flagmsk VarsList MapConst)))
(* * Top Level - Abbreviations - $ = OP - # = Micro - * = Pre - @ = Clock)
(DEFINEQ
(DoCycle
[LAMBDA (log) (* edited: "10-Sep-86 12:30")
(PROG NIL
(if log
then (SETQ SimLog (OPENFILE log (QUOTE OUTPUT)))
else (SETQ SimLog NIL)) (* SETQ #ClockState 0)
(SETQ #MIR (create MI))
(SETQ $MIR #MIR)
(SETQ &MIR #MIR)
(SETQ oldX 100)
(SETQ FnCount 0)
(if DoTransSim
then (SetupTransSim))
(SetClocks 0 0)
(StartDrawClocks)
(CycleSetup)
L1 (CycleCheck)
(DoCombLogic)
(ClockClock)
(if DoTransSim
then (SetSimClocks)
(CompTransSim))
(SetClocks 0 0)
(if DoTransSim
then (SetSimClocks))
(SetClocks 1 0)
(SETQ ClkD35 0)
(SETQ ClkD10 0)
(ActOnMem)
(DoPhiPrecharge)
(DoCombLogicPrecharge)
(if DoTransSim
then (SetSimClocks))
(SetClocks 0 0)
(if DoTransSim
then (SetSimClocks))
(SetClocks 0 1 T)
(ClockMemAddr)
(ActOnMem)
(if DoTransSim
then (SetSimClocks))
(MonitorState)
(SETQ ClkD10 1)
(ClockD10MemAddr)
(DoRCMux)
(if DoTransSim
then (SetSimClocks))
(MonitorState)
(SETQ ClkD35 1)
(DoMemory)
(if DoTransSim
then (SetSimClocks))
(MonitorState)
(DoPhiClockRW) (* if (AND DoTransSim (FASSOC
(QUOTE ppClock) compsectionclocks)) then
(SetSymClocks) (CompTransSim
(QUOTE ppClock)))
(DoPhiClockUOp)
(PrintInstStart)
(if (TF Reset)
then (SETQ ResetCycle Cycles))
(SETQ Reset 0)
(GO L1])
(SetClocks
[LAMBDA (pre clock flg) (* rtk "21-Jul-86 14:52")
(MonitorState flg)
(SETQ pPre pre)
(SETQ pClock clock)
(GateClocks])
(GateClocks
[LAMBDA NIL (* edited: " 2-Sep-86 19:14")
[SETQ *Clock (LOGOR pClock (LOGAND *Clock (LNOT pPre]
[SETQ *Pre (LOGOR pPre (LOGAND *Pre (LNOT pClock]
(SETQ pMicro (LOGAND pClock *Micro))
(SETQ pMicro&WriteOk (LOGAND pMicro $WriteOk))
(SETQ pMicro&NewOp (LOGAND pMicro $NewOp))
(SETQ pOp (LOGAND pClock *Op))
(SETQ pRead (LOGAND pClock *Read))
(SETQ pWrite (LOGAND pClock *Write))
(SETQ pMemRead (LOGAND pClock *MemRead))
(SETQ pMemWrite (LOGAND pClock *MemWrite))
(SETQ pFirstCy (LOGAND pClock *FirstCy))
(SETQ pSecondCy (LOGAND pClock *SecondCy))
(DoRCMux)
(DoMemory])
(DoCombLogic
[LAMBDA NIL (* edited: "10-Sep-86 11:09")
(DoClock)
(DoRegMux)
(DoRegMuxB)
(DecodeRegAddr)
(DoMisc)
(DoIBuf)
(DoCCode1)
(DoCCode2)
(DoCCode3)
(SelNextInst)
(PrepareDecode)
(DoVMM)
(DoRCMux)
(DoMemory) (* These happen after phiMicro)
(IBufData)
(GetUCode)
(OpPla])
(DoPhiPrecharge
[LAMBDA NIL (* agb: "12-Jun-86 22:08")
(PrechargeSync)
(PrechargeClock)
(PrechargeRegister)
(PrechargeEU)
(PrechargeMem)
(PrechargeWriteSpecial])
(DoCombLogicPrecharge
[LAMBDA NIL (* rtk " 8-Jul-86 18:08")
(DoMemory)
(WriteSpecial)
(OpPla])
(DoPhiClockRW
[LAMBDA NIL (* rtk "30-Jul-86 15:59")
(ClockReadRegister)
(ClockReadSpecial)
(ClockMemRead)
(ClockEUR)
(CheckCondA)
(PrepareWrite)
(DoCCode1)
(DoCCode2)
(SelNextInst)
(DoRegMuxB)
(NormalCycle)
(ClockMemWrite)
(ClockVMM)
(ClockWriteRegister)
(ClockWriteSpecial)
(ClockEUW])
(DoPhiClockUOp
[LAMBDA NIL (* rtk " 8-Jul-86 18:19")
(ClockMemAddr)
(ClockRdMux)
(ClockSNI)
(ClockIBuf)
(ClockMisc)
(ClockSync)
(ClockClock])
)
(* * Clock Pla)
(DEFINEQ
(DoClock
[LAMBDA NIL (* rtk "25-Jul-86 12:20")
(* PRINTOUT T "State " @ClockState " Cycle " Cycle
" @#Fault " @#Fault " @#VMRefill " @#VMRefill
" @MemDir " @MemDir " @MemWrite " @MemWrite T)
(EvaluatePLA ClockPlaSpec (QUOTE ClockPla)) (* PRINTOUT T "Newc " @NClockState " Cycle " Cycle
" @#Fault " @#Fault " @#VMRefill " @#VMRefill
" @MemDir " @MemDir " @MemWrite " @MemWrite T)
(DoMemory])
(ClockClock
[LAMBDA NIL (* edited: "10-Sep-86 11:07")
(ExecuteClock (QUOTE (((T)
(*NClockState @ClockState)
(*HoldA @#HoldA)
(#VMRefill @#VMRefill)
($Hold #$Hold))
((*Op)
(#NewOp $NewOp)
(#WriteOk $WriteOk))
((*Micro)
($NewOp #$NewOp))
((*Read)
(*Fault @#Fault])
(PrechargeClock
[LAMBDA NIL (* edited: "10-Sep-86 11:06")
(ExecuteClock (QUOTE (((T)
(@NClockState *NClockState)
(@Quad *Quad)
(@Op *Op)
(@Micro *Micro)
(@Read *Read)
(@Write *Write)
(@MemRead *MemRead)
(@MemWrite *MemWrite)
(@FirstCy *FirstCy)
(@SecondCy *SecondCy)
(@MemDir *MemDir)
(@MemCy *MemCy)
(@DoReset *DoReset)
(@Write-VMM *Write-VMM)
(@HoldA *HoldA)
(@CasH *CasH)
(#Fault *Fault])
(MakeClockPla2
[LAMBDA NIL (* edited: "11-Sep-86 19:33")
(SETQ ClockPlaSpec
(MakePlaSpec (QUOTE ((@ClockState 2 2 2)
(@ClockState 0 2 0)
(@Reset 11Q 1 0)
(#$Hold 12Q 1 0)
(Cycle 4 3 0)
(@#Fault 7 1 0)
(@#VMRefill 10Q 1 0)))
(QUOTE ((@NClockState 0 4 0)
(@Op 4 1 0)
(@Micro 5 1 0)
(@Read 6 1 0)
(@Write 7 1 0)
(@MemRead 10Q 1 0)
(@MemWrite 11Q 1 0)
(@MemCycle 12Q 1 0)
(@Quad 13Q 2 0)
(@DoReset 15Q 1 0)
(@FirstCy 16Q 1 0)
(@SecondCy 17Q 1 0)
(@MemDir 20Q 1 0)
(@MemCy 21Q 1 0)
(@Write-VMM 22Q 1 0)
(@HoldA 23Q 1 0)
(@CasH 24Q 1 0)))
(QUOTE ((X X 1 X X X X - 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 reset)
(0 1 0 X X X X - 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0)
(0 0 0 0 0 X X - 2 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 normal)
(0 2 0 X X X X - 0 0 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0)
(0 0 0 0 2 X X - 10Q 0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 1 r4)
(10Q 0 0 X X 0 0 - 3 0 0 0 1 1 0 1 0 0 0 1 0 1 0 0 0)
(0 3 0 X X X X - 4 0 0 0 1 1 0 1 1 0 0 0 0 1 0 0 0)
(4 0 0 X X X X - 5 1 0 0 1 1 0 1 2 0 0 0 0 1 0 0 0)
(4 1 0 X X X X - 0 0 1 0 1 1 0 1 3 0 0 0 0 0 0 0 0)
(0 0 0 0 4 X X - 11Q 0 0 1 0 0 0 1 0 0 1 0 1 1 0 0 1 w4)
(10Q 1 0 X X 0 0 - 6 0 0 1 0 0 1 1 1 0 0 1 1 1 0 0 0)
(4 2 0 X X X X - 7 0 0 1 0 0 1 1 2 0 0 0 1 1 0 0 0)
(4 3 0 X X X X - 14Q 1 0 1 0 0 1 1 3 0 0 0 1 1 0 0 0)
(14Q 0 0 X X X X - 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0)
(0 0 0 0 1 X X - 12Q 1 0 1 0 0 0 1 0 0 1 0 0 1 0 0 1 r1)
(10Q 2 0 X X 0 0 - 0 0 1 0 1 1 0 1 0 0 0 1 0 0 0 0 0)
(0 0 0 0 3 X X - 13Q 1 0 1 0 0 0 1 0 0 1 0 1 1 0 0 1 w1)
(10Q 3 0 X X 0 0 - 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0 0 0)
(10Q X 0 X X X 1 - 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 0 refill)
(10Q X 0 X X 1 0 - 15Q 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 fault1)
(14Q 1 0 X X X X - 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 fault2)
(0 0 0 1 X X X - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 hold])
)
(* * Register Mux)
(DEFINEQ
(DoRegMux
[LAMBDA NIL (* edited: "14-May-87 15:47")
[SETQ #Tos' (LOGAND 63 (PLUS #Tos (Mux-1 (fetch (MI Tos') of #MIR)
-1 1]
[SETQ #Arg' (LOGAND 63 (PLUS #Arg (Mux-2 (fetch (MI Arg') of #MIR)
-1 1 -4 4]
(SETQ #Top+1Cxt (CxtOp #TopCxt 1))
(SETQ #Top-1Cxt (CxtOp #TopCxt -1))
(SETQ #Bot+1Cxt (CxtOp #BotCxt 1))
(SETQ #Bot-1Cxt (CxtOp #BotCxt -1))
(SETQ #uK (fetch (MI K) of #MIR))
(SETQ #FramesEmpty (LEQV #TopCxt #BotCxt))
(SETQ #FramesFull (LEQV #Top+1Cxt #BotCxt))
[RegMux (QUOTE @RegAddr~)
(QUOTE (Mux-1 @Write (fetch (MI Raddr) of #MIR)
(PLUS 8 (fetch (MI Waddr) of #MIR]
(RegMux (QUOTE @MuxRdSel~)
(QUOTE (fetch (MI MuxRdSel)
of #MIR)))
[RegMux (QUOTE @RegCxt~)
(QUOTE (Mux-1 @Write (fetch (MI RCxt) of #MIR)
(PLUS 8 (fetch (MI WCxt) of #MIR]
(RegMux (QUOTE #NewTopCxt~)
(QUOTE (fetch (MI NewTopCxt)
of #MIR)))
(RegMux (QUOTE #NewBotCxt~)
(QUOTE (fetch (MI NewBotCxt)
of #MIR)))
(SETQ @RdMuxSel (OZ (EQ (fetch (MI RD2addr) of #MIR)
7])
(CxtOp
[LAMBDA (cxt dir) (* edited: "15-May-87 13:58")
(if (EQ dir 1)
then (SELECTQ cxt
(3 5)
(7 0)
(PLUS cxt 1))
else (SELECTQ cxt
(0 7)
(5 3)
(DIFFERENCE cxt 1])
(DoRegMuxB
[LAMBDA NIL (* agb: "10-Jun-86 19:12")
(RegMux (QUOTE #NewArg~)
(QUOTE (fetch (MI NewArg)
of #MIR)))
(RegMux (QUOTE #NewArg2~)
(QUOTE (fetch (MI NewArg2)
of #MIR)))
(RegMux (QUOTE #NewTos~)
(QUOTE (fetch (MI NewTos)
of #MIR])
(ClockRdMux
[LAMBDA NIL (* edited: "14-May-87 14:15")
(SETQ $NewArg (LOGAND 255 (LOGNOT $NewArg~)))
(SETQ $NewArg2 (LOGAND 63 (LOGNOT $NewArg2~)))
(SETQ $NewTos (LOGAND 63 (LOGNOT $NewTos~)))
(SETQ $NewTopCxt (LOGAND 7 (LOGNOT $NewTopCxt~)))
(SETQ $NewBotCxt (LOGAND 7 (LOGNOT $NewBotCxt~)))
[ExecuteClock (QUOTE (((*Op)
(#NewArg~ $NewArg~)
(#NewArg2~ $NewArg2~)
(#NewTos~ $NewTos~)
(#NewTopCxt~ $NewTopCxt~)
(#NewBotCxt~ $NewBotCxt~)
(#Opcode $Opcode))
((*Micro $WriteOk)
($NewTos #Tos))
((*Micro)
($NewArg #Arg)
($NewArg2 #Arg2)
($NewTopCxt #TopCxt)
($NewBotCxt #BotCxt))
((*Micro $NewOp)
($Opcode #$Opcode]
(SETQ #Arg=0 (OZ (EQ #Arg 0)))
(SETQ #Arg=Arg2 (OZ (EQ #Arg #Arg2])
)
(* * Register Access)
(DEFINEQ
(DecodeRegAddr
[LAMBDA NIL (* rtk "17-Sep-86 10:34")
(PROG (BaseAddr OddAddr raddr0) (* PRINTOUT T "CXT,ADDR= " @RegCxt~ , @RegAddr~ T)
[SETQ BaseAddr (LOGAND 377Q (LOGNOT (ConcatBits (QUOTE ((@RegCxt~ 5 3 0)
(@RegAddr~ 0 5 1]
(SETQ raddr0 (LOGAND 1 (LOGNOT @RegAddr~)))
(* PRINTOUT T "BaseAddr= " BaseAddr , raddr0 T)
(* if (NEQ 7 @RegCxt~) then
(BREAK1 NIL T (DecodeRegAddr) NIL))
[SETQ @RswapFlg (LNOT (LEQV raddr0 (fetch (MI Dswap) of #MIR]
(SETQ OddAddr (if (TF raddr0)
then BaseAddr
elseif (EQ BaseAddr 220Q)
then (PLUS BaseAddr 3)
elseif (EQ BaseAddr 0)
then 0
else (SUB1 BaseAddr)))
(SETQ @WtEven (LAND (OZ (NEQ 0 (fetch (MI Waddr) of #MIR)))
(LNOT raddr0)))
(SETQ @WtOdd (LAND (OZ (NEQ 0 (fetch (MI Waddr) of #MIR)))
(LOR raddr0 @WriteOctal)))
(SETQ @EvenWordLines (if (AND (TF @WriteOctal)
(TF @Write))
then (LIST BaseAddr (LOR BaseAddr 3))
else (LIST BaseAddr BaseAddr)))
(SETQ @OddWordLines (if (AND (TF @WriteOctal)
(TF @Write))
then (LIST (DIFFERENCE BaseAddr 1)
(LOR BaseAddr 2))
else (LIST OddAddr OddAddr])
(ReadRegister
[LAMBDA NIL (* agb: "18-May-86 21:26")
(SETQ eDat (ELT EvenRegFile (CAR *EvenWordLines)))
(SETQ oDat (ELT OddRegFile (CAR *OddWordLines)))
(if (EQ 0 (fetch (MI RD1addr) of #MIR))
then (SETQ D1 (Mux-1 *RswapFlg eDat oDat)))
(if (EQ 0 (fetch (MI RD2addr) of #MIR))
then (SETQ D2 (Mux-1 *RswapFlg oDat eDat])
(WriteRegister
[LAMBDA NIL (* rtk " 2-Jun-86 11:20")
(PROG (val j)
(SETQ val (Mux-1 *MemRead D1 D2))
(if (TF *WtEven)
then (for i from (CAR *EvenWordLines) to (CADR *EvenWordLines)
do (SETQ j (TIMES 2 i))
(if DoSimLog
then (PRINTOUT SimLog "Writing Reg " j " with " # (PrintData
val)
T))
(SETA EvenRegFile i val)
(TS.PUTFRAMEPROP (ELT STACKFRAMES (LRSH i 5))
(LOGAND 63 j)
val)))
(if (TF *WtOdd)
then (for i from (CAR *OddWordLines) to (CADR *OddWordLines)
do (SETQ j (ADD1 (TIMES i 2)))
(if DoSimLog
then (PRINTOUT SimLog "Writing Reg " j " with " # (PrintData
val)
T))
(SETA OddRegFile i val)
(TS.PUTFRAMEPROP (ELT STACKFRAMES (LRSH i 5))
(LOGAND 63 j)
val])
(PrechargeRegister
[LAMBDA NIL (* edited: " 2-Sep-86 19:01")
(ExecuteClock (QUOTE (((T)
(37777777777Q D1)
(37777777777Q D2)
(37777777777Q eDat)
(37777777777Q oDat)
(@EvenWordLines *EvenWordLines)
(@OddWordLines *OddWordLines)
(@WtEven *WtEven)
(@WtOdd *WtOdd)
(@RswapFlg *RswapFlg)
(@RegAddr *RegAddr])
(ClockReadRegister
[LAMBDA NIL (* agb: "18-May-86 13:17")
(ExecuteClock (QUOTE (((*Read)
((Eval (ReadRegister])
(ClockWriteRegister
[LAMBDA NIL (* agb: "17-May-86 11:06")
(ExecuteClock (QUOTE (((*Write $WriteOk)
((Eval (WriteRegister])
)
(* * Special Register Read Access)
(DEFINEQ
(ReadRD1
[LAMBDA NIL (* edited: "18-Sep-86 16:43")
(SELECTQ (fetch (MI RD1addr) of #MIR)
(0 NIL)
(1 (SETQ D1 #PCHiN))
(2 (SETQ D1 #IBufData))
(3 (if (TF *FirstCy)
then (SETQ D1 @Mar)))
(HELP])
(ReadRD2
[LAMBDA NIL (* rtk "17-Jul-86 10:09")
(SELECTQ (fetch (MI RD2addr) of #MIR)
(0 NIL)
(1 (SETQ D2 (ReadPc)))
(2 (SETQ D2 @Tmp1))
[3 (SETQ D2 (TamRep (QUOTE NIL]
[4 (SETQ D2 (TamRep (QUOTE T]
[5 (SETQ D2 (TamRep (QUOTE Unbound]
[7 (SETQ D2 (LOGAND (LOGNOT @MuxRdSel~)
(MASK.1'S 0 8]
(HELP])
(ReadPc
[LAMBDA NIL (* agb: "16-May-86 08:11")
(LOR #NCurPc (Mux-1 [ConcatBits (QUOTE ((#NCurPc 0 1 4]
#PCHiE #PCHiO])
(ClockReadSpecial
[LAMBDA NIL (* agb: "18-May-86 13:18")
(ExecuteClock (QUOTE (((*Read)
((Eval (ReadRD1)))
((Eval (ReadRD2])
)
(* * Special Register Write Access)
(DEFINEQ
(PrepareWrite
[LAMBDA NIL (* agb: "24-May-86 14:04")
[SETQ $XCurPc (ConcatBits (QUOTE ((D1 0 5 0]
(SETQ $XPcHi (ConcatBits (QUOTE ((D1 4 28 4])
(WriteSpecial
[LAMBDA NIL (* rtk " 9-Jun-86 17:03")
(Decoder *W2Addr 1 (QUOTE (none $W2-WriteIBufWord $W2-WriteMarD1 $W2-WriteMarD2 $W2-WritePC
$W2-WriteTmpD1 $W2-WriteMarMem])
(WriteIBufWord
[LAMBDA NIL (* edited: "22-Aug-86 17:30")
(PROG (reg)
[SETQ reg (ConcatBits (QUOTE ((#OEFlg 2 1 0)
(*Quad 0 2 0]
(if DoSimLog
then (PRINTOUT SimLog "Writing IBuf word " reg " with " D2 " Lnot "
(LOGXOR D2 4294967295)
T))
(SETA IBufReg reg (LOGXOR D2 4294967295])
(PrechargeWriteSpecial
[LAMBDA NIL (* agb: "24-May-86 12:34")
(ExecuteClock (QUOTE (((T)
((Rec #MIR - W2addr)
*W2Addr])
(ClockWriteSpecial
[LAMBDA NIL (* rtk "13-Jun-86 15:33")
(ExecuteClock (QUOTE (((*SecondCy $W2-WriteMarD1)
(D1 @Mar))
((*SecondCy $W2-WriteTmpD1)
(D1 @Tmp1))
((*FirstCy $W2-WriteMarD2)
(D2 @Mar))
((*MemRead *SecondCy $W2-WriteMarMem)
(D2 @Mar))
((*Write $W2-WritePC)
($XCurPc #CurPc)
($XPcHi #PCHiE)
($XPcHi #PCHiO)
($XPcHi #PCHiN))
[(*Write $W2-WriteIBufWord)
((Eval (WriteIBufWord]
((*SecondCy $W2-WriteIBufWord)
($XPcHi #PCHiN))
((*FirstCy $W2-WriteIBufWord #OEFlg)
($XPcHi #PCHiO))
((*FirstCy $W2-WriteIBufWord (Not #OEFlg))
($XPcHi #PCHiE))
((*Micro)
((Concat ((#PCHiN 0 1 4)))
#OEFlg])
)
(* * Virtual Memory)
(DEFINEQ
(PrepareDecode
[LAMBDA NIL (* agb: "24-May-86 13:14")
(SETQ @VirAddr (Mux-1 #$NewOp @Mar (RSH #PCHiN 2])
(DoVMM
[LAMBDA NIL (* edited: "27-Aug-86 18:01")
(PROG (cmpAddr i)
[SETQ @RealMatch (OZ (EQ 0 (LOADBYTE @VirAddr 21 3]
(SETQ cmpAddr (LOADBYTE @VirAddr 10 15))
[SETQ i (for i from 0 to 7 thereis (EQ cmpAddr (ELT VMCmpArray i]
(if i
then (SETQ @VirMatch 1)
(SETQ @VirData (ELT VMResArray i))
else (SETQ @VirMatch 0)
(SETQ @VirData -1))
(if (TF (LAND @RealMatch @VirMatch))
then (HELP))
(SETQ #VMRefill (LNOT (LOR @RealMatch @VirMatch)))
[SETQ #Fault (LAND @VirMatch (LOR (LNOT (LOADBYTE @VirData 0 1))
(LAND @MemDir (LNOT (LOADBYTE @VirData 1 1]
(* PRINTOUT T "#VMRefill " #VMRefill " #Fault " #Fault
" @VirData " @VirData T)
])
(DoRCMux
[LAMBDA NIL (* rtk "16-Aug-86 12:32")
(PROG NIL
(SETQ vmmRC (LAND @RealMatch (LNOT @Ras-Cas~)))
(SETQ vmmRR (LAND @RealMatch @Ras-Cas~))
(SETQ vmmVC (LAND @VirMatch (LNOT @Ras-Cas~)))
(SETQ vmmVR (LAND @VirMatch @Ras-Cas~))
(SETQ vmmMC (LAND #VMRefill (LNOT @Ras-Cas~)))
(SETQ vmmMR (LAND #VMRefill @Ras-Cas~))
(SETQ vmmVRR (LOR vmmVR vmmRR))
(SETQ vmmVRC (LOR vmmVC vmmRC))
[SETQ @RAddr (LOGOR [Mux-1 vmmRC 0 (ConcatBits (QUOTE ((@VirAddr 1 11Q 13Q]
[Mux-1 vmmVC 0 (ConcatBits (QUOTE ((@VirData 10Q 2 31Q)
(@VirData 1 7 3)
(@VirAddr 0 1 1]
[Mux-1 vmmMC 0 (ConcatBits (QUOTE ((3 12Q 2 0)
(MapConst 5 5 0)
(@VirAddr 1 4 25Q)
(@VirAddr 0 1 13Q]
[Mux-1 vmmVRC 0 (ConcatBits (QUOTE ((3 12Q 2 0)
(@VirAddr 0 1 1]
[Mux-1 vmmRR 0 (ConcatBits (QUOTE ((@VirAddr 12Q 2 24Q)
(@VirAddr 11Q 1 12Q]
[Mux-1 vmmVR 0 (ConcatBits (QUOTE ((@VirData 12Q 2 33Q)
(@VirData 11Q 1 2]
[Mux-1 vmmMR 0 (ConcatBits (QUOTE ((MapConst 12Q 2 5)
(@VirAddr 1 11Q 14Q)
(@VirAddr 0 1 12Q]
(Mux-1 vmmVRR 0 (ConcatBits (QUOTE ((@VirAddr 1 10Q 2)
(@VirAddr 0 1 0]
(* PRINTOUT T "DoRCMux @Ras-Cas~ " @Ras-Cas~ " RAS' "
RAS' " CAS' " CAS' " @RAddr: " @RAddr " VirAddr "
@VirAddr T)
])
(ResetVMM
[LAMBDA NIL (* agb: "20-May-86 15:46")
(for i from 0 to 7 do (SETA VMCmpArray i 37777777777Q))
(SETQ @NewVMMPtr 0])
(Write-VMM
[LAMBDA NIL (* agb: "20-Jul-86 15:47")
(SETA VMResArray @NewVMMPtr D2)
(SETA VMCmpArray @NewVMMPtr (LOADBYTE @VirAddr 10 15))
(SETQ @NewVMMPtr (Mod8 (ADD1 @NewVMMPtr])
(ClockVMM
[LAMBDA NIL (* agb: "23-Jul-86 12:44")
(ExecuteClock (QUOTE ([(*FirstCy @Reset-VMM)
((Eval (ResetVMM]
((*Write-VMM)
((Eval (Write-VMM])
)
(* * Memory Access)
(DEFINEQ
(ClockMemRead
[LAMBDA NIL (* agb: "18-May-86 17:16")
(ExecuteClock (QUOTE (((*MemRead)
(*Din D2])
(ClockMemWrite
[LAMBDA NIL (* edited: "11-Sep-86 19:53")
(ExecuteClock (QUOTE (((*Read)
(D2 RD])
(DoMemory
[LAMBDA NIL (* rtk "21-Aug-86 17:17")
(* SETQ ClkD35 0)
(SETQ RA10 (LOADBYTE @Raddr 10 1))
(SETQ RA11 (LOADBYTE @Raddr 11 1))
(SETQ *Ras (LAND *MemCy (LNOT #Fault)))
(SETQ *Ras' (LNOT *Ras))
[SETQ *Ras-0~ (LNOT (LAND *Ras (LAND (LNOT RA10)
(LNOT RA11]
[SETQ *Ras-1~ (LNOT (LAND *Ras (LAND RA10 (LNOT RA11]
[SETQ *Ras-2~ (LNOT (LAND *Ras (LAND (LNOT RA10)
RA11]
[SETQ *Ras-3~ (LNOT (LAND *Ras (LAND RA10 RA11]
[SETQ *We~ (LNOT (LAND *MemDir (LNOT #VMRefill]
(SETQ @Cas (LOR @MemRead @MemWrite))
(SETQ CAS~ (LNOT (LOR (LAND pPre @Cas)
(LAND ClkD35 $CasH))) (* PRINTOUT T "DoMem Ras0-3 " *Ras-0~ *Ras-1~ *Ras-2~
*Ras-3~ " *Ras " *Ras " @Cas " @Cas " CAS~ " CAS~ T)
)
(SETQ ECAS~ CAS~])
(ClockMemAddr
[LAMBDA NIL (* rtk "19-Aug-86 17:45")
(DoMemory)
[ExecuteClock (QUOTE ((($MemCy~)
(*Ras-0~ RAS-0~)
(*Ras-1~ RAS-1~)
(*Ras-2~ RAS-2~)
(*Ras-3~ RAS-3~)
(*We~ WE~))
((T)
((Not *MemCy)
$MemCy~)
(*CasH $CasH))
(($MemCy~)
(*Ras-0~ RAS-0~)
(*Ras-1~ RAS-1~)
(*Ras-2~ RAS-2~)
(*Ras-3~ RAS-3~)
(*We~ WE~]
(SETQ RPADENB~ @#HoldA)
(SETQ DPADENB~ (LOR RPADENB~ WE~])
(ClockD10MemAddr
[LAMBDA NIL (* rtk "16-Aug-86 09:19")
(ExecuteClock (QUOTE (((T)
($MemCy~ @Ras-Cas~])
(ClockD35MemAddr
[LAMBDA NIL (* agb: "20-Jul-86 17:24")
(ExecuteClock (QUOTE (((T)
(*Ras' @Ras-Cas~])
(PrechargeMem
[LAMBDA NIL (* edited: "11-Sep-86 12:21")
(ExecuteClock (QUOTE (((T)
(RD *Din])
)
(* * Execution Units)
(DEFINEQ
(NormalCycle
[LAMBDA NIL (* edited: "11-Sep-86 12:18")
(PROG (DD1 DD2 TD2)
[SETQ DD1 (ConcatBits (QUOTE ((D1 0 30 0]
[SETQ DD2 (ConcatBits (QUOTE ((D2 0 30 0]
(SETQ @V (SELECTQ (fetch (MI EUop) of #MIR)
(0 1073741823)
(44 D1)
(42 D2)
[60 (ConcatBits (QUOTE ((D1 30 2 30)
(D1 1 29 0]
[61 (ConcatBits (QUOTE ((D1 30 2 30)
(D1 0 29 1]
[63 (ConcatBits (QUOTE ((D2 24 8 0)
(D1 0 24 0]
[56 (ConcatBits (QUOTE ((IntPtr 30 2 30)
(D1 0 8 24]
[62 (ConcatBits (QUOTE ((D2 0 8 0)
(D1 8 24 8]
[44 (ConcatBits (QUOTE ((D2 30 2 6)
(D1 0 30 0]
[53 (ConcatBits (QUOTE ((D1 29 3 29)
(D1 0 29 1]
(18 (CombTagD2 (IPLUS 4 DD1)))
(16 (CombTagD2 (IPLUS DD1 DD2)))
(21 (CombTagD2 (IPLUS DD1 (IPLUS (LOGXOR DD2 1073741823)
1))
T))
(20 (CombTagD2 (IPLUS DD1 (LOGXOR DD2 1073741823))
T))
(22 (CombTagD2 (IPLUS 16 DD1)))
(40 (CombTagD2 (LOGAND DD1 DD2)))
(46 (CombTagD2 (LOGOR DD1 DD2)))
(38 (CombTagD2 (LOGXOR DD1 DD2)))
(Emulator.Error)))
(SETQ @V (LOGOR (LOGAND @V 1073741823)
(SELECTQ (fetch (MI Tag) of #MIR)
(0 (TamRep (QUOTE Int)))
(1 (LSH (LOGAND D2 192)
24))
(2 (LOGAND D1 3221225472))
(3 (LOGAND D2 3221225472))
(HELP])
(CombTagD2
[LAMBDA (d inverted) (* rtk "24-Jun-86 11:34")
(PROG ((LD2 (LOADBYTE (if inverted
then (LOGXOR D2 (MASK.1'S 0 30))
else D2)
29 1)))
(SETQ @carry (LOADBYTE d 30 1))
[SETQ @overflow (LAND (LEQV (LOADBYTE D1 29 1)
LD2)
(LNOT (LEQV (LOADBYTE d 29 1)
LD2]
(SETQ @greaterp (if (EQP (LOADBYTE D1 29 1)
(LOADBYTE D2 29 1))
then @carry
else (LEQV (LOADBYTE D1 29 1)
0))) (* ConcatBits (QUOTE ((D2 30 2 30)
(d 0 30 0))))
(RETURN d])
(PrechargeEU
[LAMBDA NIL (* agb: "17-May-86 11:41")
(ExecuteClock (QUOTE (((T)
(@V *V])
(ClockEUR
[LAMBDA NIL (* agb: "23-May-86 22:30")
(ExecuteClock (QUOTE (((*SecondCy)
(*V D1])
(ClockEUW
[LAMBDA NIL (* agb: "24-May-86 12:59")
(ExecuteClock (QUOTE (((*FirstCy)
(@carry @@carry)
(@overflow @@overflow)
(@greaterp @@greaterp])
)
(* * Condition Code in Data Path)
(DEFINEQ
(CheckCondA
[LAMBDA NIL (* edited: "11-Sep-86 12:16")
(PROG (r)
(SETQ r (ELT CondAArray (LOADBYTE (fetch (MI CondCode) of #MIR)
0 5)))
(SETQ #CondA (OZ (if (NEQ r (QUOTE condc))
then [EQ 0 (LOGOR (LOGAND D1 (fetch (CondCode D1)
of r))
(LOGAND D2 (fetch (CondCode D2)
of r))
(LOGAND (LOGNOT D1)
(fetch (CondCode nD1)
of r))
(LOGAND (LOGNOT D2)
(fetch (CondCode nD2)
of r))
(LOGAND (LOGXOR D1 D2)
(fetch (CondCode D1xorD2)
of r]
else (SELECTQ (LOADBYTE (fetch (MI CondCode) of #MIR)
0 3)
(0 T)
(1 (EQ @@overflow 1))
(2 (EQ @@carry 1))
(3 (EQ @@greaterp 1))
0])
(MakeCondCodeArray
[LAMBDA NIL (* rtk "14-Jul-86 13:43")
(SETQ CondAArray (ARRAY 32 (QUOTE POINTER)
(QUOTE noop)
0))
[MakeCondALst (QUOTE ((true condc)
(overflow condc)
(carry condc)
(greaterp condc)
(integerp tagD1 Int)
(floatp tagD1 Float)
(pointerp tagD1 Ptr)
(xtypep tagD1 Xtype)
(ccodep fulltagD1 Code)
(consp fulltagD1 List)
(posintegerp tagD1 Int notbitD1 SignBit)
(traponexit bitD1 TrapOnExit)
(traponreturntod2 bitD2 TrapOnReturnTo)
(unbound fulltagD1 Unbound)
(ccodep&~nlambdastarp fulltag&flagD1 Code)
(flagbitd2 bitD2 Tag)
(pointerpd2 tagD2 Ptr)
(integerd1d2 tagD1 Int tagD2 Int)
(integerpd1&pointerpd2 tagD1 Int tagD2 Ptr)
(numberpd1d2 fulltag&flagD1 Number fulltag&flagD2 Number)
(d2=int<8&d1=atom tagD2 Int valD2<2:28> 0 fulltagD1 Atm)
(d2=int<8&d1=ccodep tagD2 Int valD2<2:28> 0 fulltagD1 Code)
(d1=d2 wordEq 4294967295)
(d1<7x>=d2<7x> wordEq 254)
(d1<8>=d2<8> wordEq 255)
(stackp fulltag&flagD1 Stack)
(minintd2 D2Eq 536870912]
(SETQ CondALst (for i from 0 to (DIFFERENCE (ARRAYSIZE CondAArray)
1)
collect (ELT CondAArray i])
)
(* * Next Opcode Functions)
(DEFINEQ
(DoIBuf
[LAMBDA NIL (* rtk " 7-Aug-86 12:11")
(SETQ &Opcode #Opcode) (* for simulator)
(PROG (selO selE)
(SETQ #NCurPc (LOADBYTE (PLUS #CurPc #$OpLength)
0 5))
(SETQ #NCurPc<30:31> (LOADBYTE #NCurPc 0 2))
(SETQ #NCurPc<29:31> (LOADBYTE #NCurPc 0 3))
(SETQ #NCurPc<27:29> (LOADBYTE #NCurPc 2 3))
(SETQ selO (LOGOR #NCurPc<27:29> 1))
(SETQ selE (if (ODDP #NCurPc<27:29>)
then (Mod8 (ADD1 #NCurPc<27:29>))
else #NCurPc<27:29>))
(SETQ #IBufWE (ELT IBufReg selE))
(SETQ #IBufWO (ELT IBufReg selO))
(SETQ #Opcode (SelectIBufByte 0))
(SETQ #IBufSData (LOGOR (LLSH (SelectIBufByte 1)
0)
(LLSH (SelectIBufByte 2)
10Q)
(LLSH (SelectIBufByte 3)
20Q)
(LLSH (SelectIBufByte 4)
30Q)))
(SETQ #ContRefill (LAND (LNOT (LEQV (LOADBYTE #PCHiN 4 1)
(LOADBYTE #CurPc 4 1)))
(LCMP (LOADBYTE #NCurPc 0 4)
3])
(SelectIBufByte
[LAMBDA (index) (* edited: "22-Aug-86 16:26")
(PROG (offset)
(SETQ offset (Mod8 (PLUS index #NCurPc<29:31>)))
(if DoIBufSwap
then [if (ILESSP offset 4)
then (RETURN (LoadIBufByte #IBufWE (DIFFERENCE 3 offset)))
else (RETURN (LoadIBufByte #IBufWO (DIFFERENCE 3 (DIFFERENCE
offset 4]
else (if (ILESSP offset 4)
then (RETURN (LOADBYTE #IBufWE (TIMES 8 (DIFFERENCE 3 offset))
8))
else (RETURN (LOADBYTE #IBufWO (TIMES 8 (DIFFERENCE 7 offset))
8])
(LoadIBufByte
[LAMBDA (IBufWord Offset) (* rtk "30-Jul-86 12:22")
(PROG ((val (RSH IBufWord Offset)))
(RETURN (for i from 0 to 7 sum (if (EQ (LOGAND val (ELT IBufMask i))
0)
then 0
else (LLSH 1 i])
(IBufData
[LAMBDA NIL (* rtk "14-May-86 12:44")
[SETQ $IBufData (LOGAND $IBufSData (SELECTQ $OpLength
(0 0)
(1 0)
(2 255)
(3 65535)
(4 16777215)
(5 -1)
(HELP]
(SETQ $IBufN (LOGAND $IBufSData 255])
(ClockIBuf
[LAMBDA NIL (* edited: "11-Sep-86 12:22")
(ExecuteClock (QUOTE (((*Op)
(#IBufSData $IBufSData)
(#NCurPc $NCurPc))
((*Micro $NewOp)
($IBufN #IBufN)
($IBufData #IBufData)
($NCurPc #CurPc)
($OpLength #$OpLength])
)
(* * Micro Control)
(DEFINEQ
(ClockSNI
[LAMBDA NIL (* rtk " 7-Aug-86 12:14")
(SETQ &MIR #MIR) (* For simulation compares)
[ExecuteClock (QUOTE (((*Op)
(#uPC $uPC)
(#OpLength $OpLength))
((*Micro)
($MIR #MIR)
($uPC #$uPC]
(SETQ Cycle (fetch (MI Cycle) of #MIR])
(SelNextInst
[LAMBDA NIL (* agb: " 6-Jul-86 11:37")
(SETQ #uPC (if (TF #SelNextInstA)
then (fetch (MI NextInstA) of #MIR)
elseif (TF #SelNextInstB)
then (fetch (MI NextInstB) of #MIR)
elseif (TF #NewOp)
then (Mux-1 #ModStartAddr #StartAddr (LOR (LAND #StartAddr 360Q)
(LAND #Opcode 17Q)))
else (HELP])
(OpPla
[LAMBDA NIL (* agb: "23-May-86 21:36")
(* * This uses #Opcode #Reset #Interrupt #RefillRq #FramesFull #FramesEmpty. It sets #OpLength #StartAddr
#ModStartAddr #ForceNewOp.)
(EvaluatePLA OpPlaSpec (QUOTE OpPla])
(GetUCode
[LAMBDA NIL (* rtk "27-May-86 19:26")
(SETQ $MIR (ELT UCodeRom $uPC])
(DoCCode1
[LAMBDA NIL (* rtk " 8-Aug-86 19:44")
(SETQ #CondB (SELECTQ (LOADBYTE (fetch (MI CondCode) of #MIR)
0 6)
(40Q #FramesFull)
(41Q @#Fault)
(42Q #Arg=0)
(43Q #Arg=Arg2)
0])
(DoCCode2
[LAMBDA NIL (* rtk "12-Aug-86 20:40")
(SETQ #CondX (Mux-2 (LOADBYTE (fetch (MI CondCode) of #MIR)
5 1)
#CondA #CondB)) (* SETQ #RefillRq (LOR @InitialRefill #ContRefill))
(SETQ #ConditionResult (LNOT (LEQV (LOADBYTE (fetch (MI CondCode) of #MIR)
6 1)
#CondX)))
[SETQ #SelNextInstA (LNOT (LOR (LOADBYTE (fetch (MI NextInstA) of #MIR)
8 1)
(LOR (LNOT #ConditionResult)
#ForceNewOp]
[SETQ #SelNextInstB (LNOT (LOR (LOADBYTE (fetch (MI NextInstB) of #MIR)
8 1)
(LOR #ConditionResult #ForceNewOp]
(SETQ #NewOp (LAND (LNOT #SelNextInstA)
(LNOT #SelNextInstB)))
(SETQ #WriteOk (LOR #ConditionResult (LNOT (fetch (MI CWrite) of #MIR])
(DoCCode3
[LAMBDA NIL (* rtk "12-Aug-86 20:38")
(SETQ #RefillRq (LOR @InitialRefill #ContRefill])
(CheckCondB
[LAMBDA NIL (* agb: " 5-Jul-86 13:27")
(SETQ #CondB (SELECTQ (LOADBYTE (fetch (MI CondCode) of #MIR)
0 3)
(0 1)
(3 #Arg=0)
(4 #Arg=Arg2)
0])
(CheckCondC
[LAMBDA NIL (* agb: "23-May-86 21:35")
(SETQ #CondC (OZ (SELECTQ (LOADBYTE (fetch (MI CondCode) of #MIR)
0 3)
(0 T)
(1 (EQ @@carry 0))
(2 (TF #FramesFull))
(3 (TF @#Fault))
(4 (EQ @@overflow 0))
(5 (EQ @@greaterp 1))
0])
)
(* * Misc Actions)
(DEFINEQ
(DoMisc
[LAMBDA NIL (* rtk " 7-Jul-86 17:05")
(if (EQ 31 (fetch (MI Misc) of #MIR))
then (if (AND (NOT JustReset)
(GREATERP Cycles 2))
then (PRINT "Emulator stopped")
(TS.MAINMENUSELECTEDFN (QUOTE Exit)
(WINDOWPROP TS.MAINWINDOW (QUOTE DEBUGMENU))
(QUOTE LEFT)))
else (SETQ JustReset NIL))
(EvaluatePLA MiscPlaSpec (QUOTE MiscPla))
(SETQ @InitialRefill (LAND $InitialRefill @ResetInitialRefill~])
(ClockMisc
[LAMBDA NIL (* agb: " 5-Jul-86 13:58")
(ExecuteClock (QUOTE (((*Op)
(@SetOutputInt~ $SetOutputInt~)
(@ResetOutputInt~ $ResetOutputInt~)
(@SetInitialRefill~ $SetInitialRefill~)
(@ResetInitialRefill~ $ResetInitialRefill~)
(@SetStackRefill~ $SetStackRefill~)
(@ResetStackRefill~ $ResetStackRefill~)
(@SetInterruptEnable~ $SetInterruptEnable~)
(@ResetInterruptEnable~ $ResetInterruptEnable~)
(@SetMemLock~ $SetMemLock~)
(@ResetMemLock~ $ResetMemLock~)
(@SetRefCnt~ $SetRefCnt~)
(@ResetRefCnt~ $ResetRefCnt~)
(@OpLength=0 $OpLength=0)
(@ResetRefresh $ResetRefresh)
(@ResetInterrupt $ResetInterrupt))
(((Not @SetOutputInt~))
(1 $OutputInt))
(((Not @ResetOutputInt~))
(0 $OutputInt))
(((Not @SetInitialRefill~))
(1 $InitialRefill))
(((Not @ResetInitialRefill~))
(0 $InitialRefill))
(((Not @SetStackRefill~))
(1 $StackRefill))
(((Not @ResetStackRefill~))
(0 $StackRefill))
(((Not @SetInterruptEnable~))
(1 $InterruptEnable))
(((Not @ResetInterruptEnable~))
(0 $InterruptEnable))
(((Not @SetMemLock~))
(1 $MemLock))
(((Not @ResetMemLock~))
(0 $MemLock))
(((Not @SetRefCnt~))
(1 $RefCnt))
(((Not @ResetRefCnt~))
(0 $RefCnt))
((*Micro)
($StackRefill #$StackRefill)
($OutputInt #$OutputInt)
($StackRefill #$StackRefill)
($InterruptEnable #$InterruptEnable)
($MemLock #$MemLock)
($RefCnt #$RefCnt)
($ResetRefresh #$ResetRefresh)
($OpLength=0 #OpLength=0)
($ResetInterrupt #$ResetInterrupt))
((*Micro $OpLength=0)
(0 #$OpLength])
(MakeMiscPla
[LAMBDA NIL (* rtk "16-Jun-86 10:56")
(SETQ MiscPlaSpec
(MakePlaSpec (QUOTE (((#MIR Misc)
0 5 0)))
(QUOTE ((@SetOutputInt~ 1 1 0)
(@ResetOutputInt~ 2 1 0)
(@SetInitialRefill~ 3 1 0)
(@ResetInitialRefill~ 4 1 0)
(@SetStackRefill~ 5 1 0)
(@ResetStackRefill~ 6 1 0)
(@SetInterruptEnable~ 7 1 0)
(@ResetInterruptEnable~ 8 1 0)
(@SetMemLock~ 9 1 0)
(@ResetMemLock~ 10 1 0)
(@SetRefCnt~ 11 1 0)
(@ResetRefCnt~ 12 1 0)
(@ResetRefresh 13 1 0)
(@ResetInterrupt 14 1 0)
(@OpLength=0 15 1 0)
(@WriteOctal 16 1 0)
(@Reset-VMM 17 1 0)))
(QUOTE ((0 - 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0)
(1 - 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 setoutputint)
(2 - 1 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 resetoutputint)
(3 - 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 setinitialrefill)
(4 - 1 1 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 resetinitialrefill)
(5 - 1 1 1 1 0 1 1 1 1 1 1 1 0 0 0 0 0 setstackrefill)
(6 - 1 1 1 1 1 0 1 1 1 1 1 1 0 0 0 0 0 resetstackrefill)
(7 - 1 1 1 1 1 1 0 1 1 1 1 1 0 0 0 0 0 setinterruptenable)
(8 - 1 1 1 1 1 1 1 0 1 1 1 1 0 0 0 0 0 resetinterruptenable)
(9 - 1 1 1 1 1 1 1 1 0 1 1 1 0 0 0 0 0 setmemlock)
(10 - 1 1 1 1 1 1 1 1 1 0 1 1 0 0 0 0 0 resetmemlock)
(11 - 1 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 setrefcnt)
(12 - 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 resetrefcnt)
(13 - 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 resetrefresh)
(14 - 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 0 resetinterrupt)
(15 - 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0 0 oplength=0)
(16 - 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 0 writeoctal)
(17 - 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 reset-vmm)
(18 - 1 0 0 1 1 0 1 0 1 0 1 0 1 1 0 0 1 reset)
(19 - 1 1 0 1 1 1 1 1 1 1 1 1 0 0 1 0 0 oplength=0&setinitialrefill)
(31 - 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 stop])
(PrechargeSync
[LAMBDA NIL (* rtk " 7-Aug-86 12:05")
(ExecuteClock (QUOTE (((T)
(Reset pReset)
(Hold pHold)
(Refresh pRefresh)
(upRefresh pupRefresh)
(Interrupt pInterrupt)
(upInterrupt pupInterrupt)
(SHold *SHold)
(#$MemLock *#$MemLock])
(ClockSync
[LAMBDA NIL (* rtk "12-Aug-86 19:15")
[ExecuteClock (QUOTE (((T)
(pReset @Reset)
(pHold SHold))
((*Micro)
(pRefresh upRefresh)
(pupRefresh upupRefresh)
(pInterrupt upInterrupt)
(pupInterrupt upupInterrupt]
(SETQ $Hold (LAND *SHold (LNOT *#$MemLock)))
(SETQ #SetRefresh (LAND upRefresh (LNOT upupRefresh)))
(SETQ #SetInterrupt (LAND upInterrupt (LNOT upupInterrupt)))
[ExecuteClock (QUOTE (((#SetRefresh)
(1 #Refresh))
((#$ResetRefresh)
(0 #Refresh))
((#SetInterrupt)
(1 #InterruptLatch))
((#$ResetInterrupt)
(0 #InterruptLatch]
(SETQ #Interrupt (LAND #InterruptLatch #$InterruptEnable))
(SETQ #$Refresh #Refresh])
)
(* * Config)
(DEFINEQ
(TamRep
[LAMBDA (itm offset) (* rtk "30-Jul-86 11:44")
(* Some of these values are wrong)
(PLUS (LOGAND (OR offset 0)
(MASK.1'S 0 30))
(SELECTQ itm
(SignBit (MASK.1'S 29 1))
(TrapOnExit (MASK.1'S 29 1))
(TrapOnReturnTo (MASK.1'S 28 1))
(Tag (MASK.1'S 24 1))
(NIL (TamRep (QUOTE Atm)
3584))
(T (TamRep (QUOTE Atm)
3600))
(COND
[(NUMBERP itm)
(TamRep (QUOTE Int)
(LOGAND itm (MASK.1'S 0 30]
(T (LLSH (TamTagRep itm)
24])
(TamTagRep
[LAMBDA (itm offset) (* rtk "16-May-86 14:52")
(PLUS (OR offset 0)
(SELECTQ itm
(Ptr 0)
(Int 64)
(Float 128)
(Object 2)
(List 4)
(Code 6)
(Atm 8)
(Frame 10)
(Number 3)
(Unbound 32)
(Xtype 192)
(Stack 1)
(Emulator.Error])
)
(* * INIT)
(DEFINEQ
(DoTest
[LAMBDA NIL (* edited: "15-May-87 11:51")
(ERSETQ (DoCycle (QUOTE {DSK19}SIMLOG)))
(CLOSEF (QUOTE {DSK19}SIMLOG))
(LISTFILES {DSK19}SIMLOG])
(InitEmulator
[LAMBDA (ReInitial) (* edited: "14-May-87 13:59")
[for i in InitVarLst
do (SET i 0)
(if (AND (NEQ i (QUOTE X))
(NOT (MEMB i GLOBALVARS)))
then (SETQ GLOBALVARS (CONS i GLOBALVARS]
[SETQ @EvenWordLines (SETQ @OddWordLines (QUOTE (0 0]
[SETQ *EvenWordLines (SETQ *OddWordLines (QUOTE (0 0]
(for i in (QUOTE (+ - * $ # @ < > :)) do (CLDISABLE i))
(SETQ IBufReg (ARRAY 8 (QUOTE POINTER)
0 0))
(SETQ EvenRegFile (ARRAY 320 (QUOTE POINTER)
0 0))
(SETQ OddRegFile (ARRAY 320 (QUOTE POINTER)
0 0))
(SETQ MemoryArray (ARRAY 32768 (QUOTE SMALLP)
0 0))
(SETQ VMCmpArray (ARRAY 8 (QUOTE POINTER)
0 0))
(SETQ VMResArray (ARRAY 8 (QUOTE POINTER)
0 0))
(SETQ IBufMask (ARRAY 8 (QUOTE FIXP)
0 0))
(for i from 0 as j in (QUOTE (1 16 256 4096 65536 1048576 16777216 268435456))
do (SETA IBufMask i j))
(SETQ DoIBufSwap T)
(MakeClockPla2)
(MakeRegMuxSpec)
(MakeMiscPla)
[SETQ sigList (COPY (QUOTE (PHIPRE PHIPRE7 PHICLOCK PHIOP PHIMICRO PHIMICRO&NEWOP
PHIFIRSTCY PHISECONDCY +READ +WRITE]
(SETQ BREAKONUMC NIL)
(SETQ BREAKONCYCLE NIL)
(SETQ IntPtr (TamRep (QUOTE Int)))
(SETQ RAS' 1)
(SETQ CAS' 1)
(SETQ LastRas' 1)
(SETQ LastCas' 1)
(SETQ SimLog NIL)
(SETQ RefreshAfter 500)
(SETQ DoTransSim NIL)
(SETQ MakeTestVectors NIL)
(ClearMemoryArray)
(* if (OR (NOT (BOUNDP (QUOTE logWindow))) (NOT (WINDOWP logWindow))) then (printout T "Create logWindow" T)
(SETQ logWindow (CREATEW NIL "Tamarin Emulator Log")))
(MakeCondCodeArray)
(if (NOT ReInitial)
then (InitEmulatorWindow])
(ActOnMem
[LAMBDA NIL (* edited: "11-Sep-86 12:21")
(* PRINTOUT T "Act: Last0-3~ " LastRas-0~ LastRas-1~
LastRas-2~ LastRas-3~ " RAS0-3~ " RAS-0~ RAS-1~ RAS-2~
RAS-3~ " CAS~ " CAS~ " @Ras-Cas~ " @Ras-Cas~ T)
(if (AND (TF LastRas-0~)
(NOT (TF RAS-0~)))
then (SETQ RasAddr @RAddr)
(SETQ sel 0)
(SETQ noCas T))
(if (AND (TF LastRas-1~)
(NOT (TF RAS-1~)))
then (SETQ RasAddr @RAddr)
(SETQ sel 1)
(SETQ noCas T))
(if (AND (TF LastRas-2~)
(NOT (TF RAS-2~)))
then (SETQ RasAddr @RAddr)
(SETQ sel 2)
(SETQ noCas T))
(if (AND (TF LastRas-3~)
(NOT (TF RAS-3~)))
then (SETQ RasAddr @RAddr)
(SETQ sel 3)
(SETQ noCas T))
[if (AND (NOT (AND (TF RAS-0~)
(TF RAS-1~)
(TF RAS-2~)
(TF RAS-3~)))
(TF LastCas~)
(NOT (TF CAS~)))
then [if noCas
then (SETQ cas @RAddr)
(SETQ RamAddr (ConcatBits (QUOTE ((sel 20 2 0)
(cas 11 9 1)
(RasAddr 2 9 1)
(cas 1 1 0)
(RasAddr 0 1 0]
(if (TF WE~)
then (SETQ RD (MemoryAccess RamAddr))
else (MemoryAccess RamAddr RD))
(SETQ noCas NIL)
(SETQ RamAddr (LOGOR (LOGAND 1073741820 RamAddr)
(LOGAND 3 (ADD1 RamAddr]
(SETQ LastCas~ CAS~)
(SETQ LastRas-0~ RAS-0~)
(SETQ LastRas-1~ RAS-1~)
(SETQ LastRas-2~ RAS-2~)
(SETQ LastRas-3~ RAS-3~])
)
(* * UCode fields)
(PUTPROPS addr uField val)
(PUTPROPS label uField atom)
(PUTPROPS newbotcxt uField ((cur 0)
(bot=in 1)
(bot=out 2)
(k 3)))
(PUTPROPS rcxt uField ((cur 0)
(next 1)
(prev 2)
(last 3)
(k 4)))
(PUTPROPS rd1addr uField ((pcaddr 1)
(ibufdata 2)
(mar 3)))
(PUTPROPS rd2addr uField ((raddr-1 0)
(pc 1)
(tmp1 2)
(nil 3)
(t 4)
(unbound 5)
(muxrdsel 7)))
(PUTPROPS wcxt uField ((cur 0)
(next 1)
(prev 2)
(last 3)
(k 4)))
(PUTPROPS cycle uField ((norm 0)
(r1 1)
(r4 2)
(w1 3)
(w4 4)))
(PUTPROPS euop uField ((nop 0)
(d1 44)
(d2 42)
(lshft1 60)
(rshft1 61)
(d2<8>shl24/d1<24> 63)
(d1<8>shr24 56)
(d1<24>/d2<8> 62)
(d2<2>shl24/d1<30> 44)
(arsh1 53)
(4 18)
(+ 16)
(diff2s 21)
(diff1s 20)
(16 22)
(and 40)
(or 46)
(xor 38)))
(PUTPROPS tag uField ((int 0)
(d2<8:7> 1)
(d1 2)
(d2 3)))
(PUTPROPS w2addr uField ((nowrite 0)
(ibufd2pcd1 1)
(mard1 2)
(mard2 3)
(pcd1 4)
(tmp1d1 5)
(marmem 6)))
(PUTPROPS dswap uField Flag)
(PUTPROPS raddr uField ((tos 0)
(ibufn 1)
(arg 2)
(k 3)
(arg<6>/qw<2> 4)
(0<4>/opcode<4> 5)))
(PUTPROPS waddr uField ((nowrite 0)
(tos 1)
(ibufn 2)
(arg 3)
(tos' 4)
(k 5)
(arg<6>/qw<2> 6)
(0<4>/opcode<4> 7)))
(PUTPROPS newarg uField ((arg 0)
(arg' 1)
(k 2)
(ibufn 3)
(d2 4)
(0<4>/opcode<4> 5)
(arg2 6)))
(PUTPROPS newarg2 uField ((arg2 0)
(d2<6>/0<2> 1)
(k 2)
(arg 3)))
(PUTPROPS newtopcxt uField ((cur 0)
(next 1)
(prev 2)
(k 3)))
(PUTPROPS newtos uField ((tos 0)
(tos' 1)
(k 2)
(ibufn 3)
(d2 4)))
(PUTPROPS arg' uField ((arg-1 0)
(arg+1 1)
(arg-4 2)
(arg+4 3)))
(PUTPROPS tos' uField ((tos-1 0)
(tos+1 1)))
(PUTPROPS k uField ((0 0)
(fx 13)
(stkhdr 0)
(pc 1)
(clink 5)
(ivar 8)
(ivar-1 7)
(pvar 16)
(valuecelloffset 1)
(defcelloffset 2)
(nextlink 3)
(inttypebits (TamTagRep (QUOTE Int)))
(symbtypebits (TamTagRep (QUOTE Atm)))
(floattypebits (TamTagRep (QUOTE Float)))
(ptrtypebits (TamTagRep (QUOTE Ptr)))
(xtypebits (TamTagRep (QUOTE Xtype)))
(unboundbits (TamTagRep (QUOTE Unbound)))
(ufnbase 256)
(undeffn 257)
(pfcode 258)
(intcode 259)
(frameflagcode 260)
(rtmp1 261)
(irqcount 262)
(decref 263)
(incref 264)
(refcountcode 265)
(quadwrap 288)))
(PUTPROPS condcode uField ((unbound 4)
(boundp 68)
(stackp 5)
(integerp 6)
(~integerp 70)
(floatp 8)
(~floatp 72)
(xtypep 9)
(~xtypep 73)
(pointerp 10)
(~pointerp 74)
(integerd1d2 11)
(numberpd1d2 12)
(~numberpd1d2 76)
(consp 13)
(~consp 77)
(d1=d2 14)
(d1#d2 78)
(ccodep 16)
(d2=int<8&d1=ccodep 17)
(d2=int<8&d1=atom 18)
(ccodep&~nlambdastarp 19)
(flagbitd2 20)
(noflagbitd2 84)
(d1<7x>=d2<7x> 21)
(d1<8>=d2<8> 22)
(minintd2 24)
(~minintd2 88)
(pointerpd2 25)
(integerpd1&pointerpd2 26)
(traponreturntod2 27)
(~traponreturntod2 91)
(traponexit 28)
(posintegerp 29)
(~posintegerp 93)
(true 0)
(overflow 1)
(nooverflow 65)
(carry 2)
(greaterp 3)
(notgreaterp 67)
(arg=arg2 35)
(arg=0 34)
(arg#0 98)
(nofault 97)
(framesfull 32)
(framesavail 96)))
(PUTPROPS muxrdsel uField ((k 1)
(arg 2)
(ibufn 3)
(opcode 4)
(tos 5)))
(PUTPROPS cwrite uField Flag)
(PUTPROPS nextinsta uField Label)
(PUTPROPS nextinstb uField Label)
(PUTPROPS misc uField ((setoutputint 1)
(resetoutputint 2)
(setinitialrefill 3)
(resetinitialrefill 4)
(setstackrefill 5)
(resetstackrefill 6)
(setinterruptenable 7)
(resetinterruptenable 8)
(setmemlock 9)
(resetmemlock 10)
(setrefcount 11)
(resetrefcount 12)
(resetrefresh 13)
(resetinterrupt 14)
(oplength=0 15)
(writeoctal 16)
(reset-vmm 17)
(reset 18)
(oplength=0&setinitialrefill 19)
(stop 31)))
(* * OpPla Fields)
(PUTPROPS forcenewop uField2 Flag)
(PUTPROPS length uField2 val)
(PUTPROPS modstartaddr uField2 Flag)
(PUTPROPS opcnt uField2 val)
(PUTPROPS opname uField2 atom)
(PUTPROPS opnbr uField2 val)
(PUTPROPS precond uField2 ((reset (256 256))
(notreset (0 256))
(interrupt (512 512))
(notinterrupt (0 512))
(refill (1024 1024))
(notrefill (0 1024))
(framesempty (2048 2048))
(notframesempty (0 2048))
(framesfull (4096 4096))
(notframesfull (0 4096))
(refcount (8192 8192))
(notrefcount (0 8192))
(refresh (16384 16384))
(notrefresh (0 16384))
(stackrefill (32768 32768))
(notstackrefill (0 32768))))
(PUTPROPS start uField2 Label)
[DECLARE: EVAL@COMPILE
(DATATYPE MI ((Addr POINTER)
(Ucode POINTER)
(Label POINTER)
(RCxt BITS 3)
(WCxt BITS 3)
(NewTopCxt BITS 2)
(NewBotCxt BITS 2)
(Cycle BITS 4)
(EUop BITS 7)
(Tag BITS 2)
(RD1addr BITS 2)
(RD2addr BITS 3)
(W2addr BITS 3)
(Dswap BITS 1)
(Raddr BITS 3)
(Waddr BITS 3)
(NewArg BITS 3)
(NewArg2 BITS 2)
(NewTos BITS 3)
(MuxRdSel BITS 3)
(Tos' BITS 1)
(Arg' BITS 2)
(K BITS 9)
(CondCode BITS 7)
(CWrite BITS 1)
(NextInstA BITS 9)
(NextInstB BITS 9)
(Misc BITS 5)))
(DATATYPE OpD ((OpName POINTER)
(OpNbr POINTER)
(Val BITS 16)
(Mask BITS 16)
(Start BITS 10)
(ModStartAddr BITS 1)
(Length BITS 3)
(Precond BITS 3)
(NSel BITS 1)
(Const BITS 4)
(ForceNewOp BITS 1)))
(DATATYPE CondCode ((D1 POINTER)
(nD1 POINTER)
(D2 POINTER)
(nD2 POINTER)
(D1xorD2 POINTER)))
]
(/DECLAREDATATYPE (QUOTE MI)
(QUOTE (POINTER POINTER POINTER (BITS 3)
(BITS 3)
(BITS 2)
(BITS 2)
(BITS 4)
(BITS 7)
(BITS 2)
(BITS 2)
(BITS 3)
(BITS 3)
(BITS 1)
(BITS 3)
(BITS 3)
(BITS 3)
(BITS 2)
(BITS 3)
(BITS 3)
(BITS 1)
(BITS 2)
(BITS 9)
(BITS 7)
(BITS 1)
(BITS 9)
(BITS 9)
(BITS 5)))
[QUOTE ((MI 0 POINTER)
(MI 2 POINTER)
(MI 4 POINTER)
(MI 4 (BITS . 2))
(MI 4 (BITS . 50))
(MI 4 (BITS . 97))
(MI 2 (BITS . 1))
(MI 2 (BITS . 35))
(MI 0 (BITS . 6))
(MI 2 (BITS . 97))
(MI 6 (BITS . 1))
(MI 6 (BITS . 34))
(MI 6 (BITS . 82))
(MI 0 (BITS . 112))
(MI 6 (BITS . 130))
(MI 6 (BITS . 178))
(MI 7 (BITS . 2))
(MI 6 (BITS . 225))
(MI 7 (BITS . 50))
(MI 7 (BITS . 98))
(MI 7 (BITS . 144))
(MI 7 (BITS . 161))
(MI 8 (BITS . 8))
(MI 8 (BITS . 150))
(MI 7 (BITS . 192))
(MI 9 (BITS . 8))
(MI 10 (BITS . 8))
(MI 9 (BITS . 148]
(QUOTE 12))
(/DECLAREDATATYPE (QUOTE OpD)
(QUOTE (POINTER POINTER (BITS 16)
(BITS 16)
(BITS 10)
(BITS 1)
(BITS 3)
(BITS 3)
(BITS 1)
(BITS 4)
(BITS 1)))
[QUOTE ((OpD 0 POINTER)
(OpD 2 POINTER)
(OpD 4 (BITS . 15))
(OpD 5 (BITS . 15))
(OpD 6 (BITS . 9))
(OpD 2 (BITS . 0))
(OpD 2 (BITS . 18))
(OpD 2 (BITS . 66))
(OpD 2 (BITS . 112))
(OpD 0 (BITS . 3))
(OpD 0 (BITS . 64]
(QUOTE 8))
(/DECLAREDATATYPE (QUOTE CondCode)
(QUOTE (POINTER POINTER POINTER POINTER POINTER))
(QUOTE ((CondCode 0 POINTER)
(CondCode 2 POINTER)
(CondCode 4 POINTER)
(CondCode 6 POINTER)
(CondCode 8 POINTER)))
(QUOTE 10))
(RPAQQ InitVarLst (#$NewOp #$OpLength #$Opcode #$uPC #Arg #Arg2 #Bot+1Cxt #Bot-1Cxt #BotCxt #CCodeA
#CCodeB #CCodeC #CurPc #Fault #FramesEmpty #FramesFull #IBufN #IBufSData
#InitialRefill #InitialRefill' #Interrupt #Misc-Reset #NCurPc #NewOp
#PCHiE #PCHiN #PCHiO #RefCnt #RefillRq #Refresh #StackRefill #Top+1Cxt
#Top-1Cxt #TopCxt #Tos #VMMRefill $ConditionResult $ExternalInterrupt
$IBufData $IBufN $IBufSData $Misc-DisableInts $Misc-EnableInts
$Misc-Reset $NewBotCxt $NewIntEnb $NewTopCxt $OpLength $Opcode $uPC *Din
*MemCy *MemDir *MemRead *MemWrite *Micro *Op *Quad *Ras *Read *W2Addr
*We *Write *Write *Write-VMM *WtEven *WtOdd @#Fault @#VMRefill @CAS @Cas
@ClockState @FirstCy @Mar @MemRead @MemWrite @NewVMMPtr @PhyAddr @Quad
@RegAddr @SecondCy @V @VirAddr @Write @carry @greaterp @nocarry
@nooverflow @overflow BREAK CAS Cycle D1 D2 Din Hold LastCas' RAS' WE' X
eDat lastaddr oDat pClock pMemRead pMemWrite pMicro pOp pRead pWrite s2
s3 s4 #StackRefill $StackRefill @Tmp1 NOBIND DoSimLog DoOpcodeTrace
DoEmulatorVars DoEmulatorLog #ContRefill #VMRefill @RegCxt @WriteOctal
#NewTopCxt #NewBotCxt #NewArg #NewArg2 #NewTos $TopCxt $Top+1Cxt
$Top-1Cxt $BotCxt $Bot+1Cxt $Bot-1Cxt $FramesEmpty $FramesFull
$InitialRefill $NewTopCxt~ $NewBotCxt~ $NewArg~ $NewArg2~ $NewTos~
@RegCxt~ @RegAddr~ $XCurPc $XPcHi #$Hold @Reset #$RefCnt #RefCnt
#$StackRefill @Resetinterrupt $OutputInt $InterruptEnable~ $MemLock
$RefCnt Refresh #Refresh #$Refresh #$ResetRefresh pRefresh upRefresh
pupRefresh Interrupt $Interrupt pInterrupt upInterrupt pupInterrupt
#InterruptLatch #$InterruptEnable~ #$ResetInterrupt #$MemLock
RefreshCount RefreshAfter RefreshEnable Eval DoTransSim @@overflow
@RdMuxSel lastclock<>0 DoTransSim ResetCycle CondX Cycles @VirData
LastRas-0~ LastRas-1~ RAS-0~ RAS-1~ LastRas-2~ RAS-2~ LastRas-3~ RAS-3~
CAS~ WE~ LastCas~ IBufMask DoIBufSwap #Opcode lastwrd @RealMatch
@Ras-Cas~ @VirMatch *CasH #ForceNewOp SHold $#MemLock *#$MemLock
upupRefresh upupInterrupt #$InterruptEnable $InterruptEnable RA10 RA11
@Raddr MISC.MISCLOGIC.SYNCS.HOLDFF.#$MEMLOCK~
$MISC.MISCLOGIC.FFS.$INITIALREFILL~ pMicro&WriteOk pMicro&NewOp &Opcode
$NewOp $WriteOk *Clock *Pre #Tos' #Arg' #NewArg2~ #NewArg~ #NewTos~
@MuxRdSel~ #NewBotCxt~ #NewTopCxt~ #OpLength #StartAddr #uPC *DoReset
@InitialRefill #OpLength=0 #$OutputInt $Hold @Reset-VMM @OpLength=0
@ResetInterruptEnable~ @ResetMemLock~ @ResetOutputInt~ @ResetRefCnt~
@ResetStackRefill~ @SetInitialRefill~ @SetInterruptEnable~ @SetMemLock~
@SetOutputInt~ @SetRefCnt~ @SetStackRefill~ #CondA #ModStartAddr
#SelNextInstA #SelNextInstB #WriteOk @INITIALREFILL #CONTREFILL
#REFILLRQ $CasH *MemCy~ ClkD10 DPADENB~ ECAS~ *FirstCy *SecondCy *HoldA
@#HoldA BreakOnAll D1-0 RE RO PC PHIPRE #$OPLENGTH=0 PHIPRE7 PHICLOCK
PHIOP PHIMICRO PHIMICRO&NEWOP PHIFIRSTCY PHISECONDCY +READ +WRITE
#UW2ADDR-0 #UW2ADDR-1 #UW2ADDR-2 D1-1 D1-2 D1-3
DATAPATH.RESTOFDP.#NCURPC-0 DATAPATH.RESTOFDP.#NCURPC-1
DATAPATH.RESTOFDP.#NCURPC-2 DATAPATH.RESTOFDP.#NCURPC-3 ClkD35
*NClockState RD $MemCy~))
(RPAQQ fulltagmsk 4261412864)
(RPAQQ tagmsk 3221225472)
(RPAQQ fulltag&flagmsk 4278190080)
(RPAQQ VarsList (Cycles IBufLoads FnCount FrameDumps FrameLoads #TopCxt ErrorCycles ErrorCount
RefreshCount RefreshAfter Refreshes))
(RPAQQ MapConst 0)
(PUTPROPS TAMARINEMULATOR COPYRIGHT ("Xerox Corporation" 1985 1986 1987))
(DECLARE: DONTCOPY
(FILEMAP (NIL (2376 6998 (DoCycle 2386 . 4283) (SetClocks 4285 . 4491) (GateClocks 4493 . 5303) (
DoCombLogic 5305 . 5822) (DoPhiPrecharge 5824 . 6090) (DoCombLogicPrecharge 6092 . 6267) (DoPhiClockRW
6269 . 6740) (DoPhiClockUOp 6742 . 6996)) (7021 10610 (DoClock 7031 . 7644) (ClockClock 7646 . 8039)
(PrechargeClock 8041 . 8569) (MakeClockPla2 8571 . 10608)) (10636 13630 (DoRegMux 10646 . 12036) (
CxtOp 12038 . 12319) (DoRegMuxB 12321 . 12710) (ClockRdMux 12712 . 13628)) (13659 17695 (DecodeRegAddr
13669 . 15342) (ReadRegister 15344 . 15818) (WriteRegister 15820 . 16888) (PrechargeRegister 16890 .
17301) (ClockReadRegister 17303 . 17491) (ClockWriteRegister 17493 . 17693)) (17737 19011 (ReadRD1
17747 . 18088) (ReadRD2 18090 . 18594) (ReadPc 18596 . 18798) (ClockReadSpecial 18800 . 19009)) (19054
20973 (PrepareWrite 19064 . 19296) (WriteSpecial 19298 . 19549) (WriteIBufWord 19551 . 19959) (
PrechargeWriteSpecial 19961 . 20158) (ClockWriteSpecial 20160 . 20971)) (21001 24685 (PrepareDecode
21011 . 21188) (DoVMM 21190 . 22184) (DoRCMux 22186 . 23952) (ResetVMM 23954 . 24168) (Write-VMM 24170
. 24441) (ClockVMM 24443 . 24683)) (24712 27203 (ClockMemRead 24722 . 24892) (ClockMemWrite 24894 .
25063) (DoMemory 25065 . 26141) (ClockMemAddr 26143 . 26680) (ClockD10MemAddr 26682 . 26857) (
ClockD35MemAddr 26859 . 27033) (PrechargeMem 27035 . 27201)) (27232 30226 (NormalCycle 27242 . 28947)
(CombTagD2 28949 . 29666) (PrechargeEU 29668 . 29828) (ClockEUR 29830 . 29995) (ClockEUW 29997 . 30224
)) (30267 32753 (CheckCondA 30277 . 31302) (MakeCondCodeArray 31304 . 32751)) (32788 35739 (DoIBuf
32798 . 33991) (SelectIBufByte 33993 . 34704) (LoadIBufByte 34706 . 35041) (IBufData 35043 . 35412) (
ClockIBuf 35414 . 35737)) (35766 39243 (ClockSNI 35776 . 36168) (SelNextInst 36170 . 36661) (OpPla
36663 . 36974) (GetUCode 36976 . 37124) (DoCCode1 37126 . 37438) (DoCCode2 37440 . 38394) (DoCCode3
38396 . 38562) (CheckCondB 38564 . 38840) (CheckCondC 38842 . 39241)) (39269 44786 (DoMisc 39279 .
39874) (ClockMisc 39876 . 41659) (MakeMiscPla 41661 . 43588) (PrechargeSync 43590 . 43929) (ClockSync
43931 . 44784)) (44806 45957 (TamRep 44816 . 45536) (TamTagRep 45538 . 45955)) (45975 50123 (DoTest
45985 . 46226) (InitEmulator 46228 . 48283) (ActOnMem 48285 . 50121)))))
STOP