*pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 26 #$Opcode 26 #NCurPc: 3
D1: -- D2: -- Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 26 #$Opcode 26 #NCurPc: 3
D1: -- D2: -- Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 26 #$Opcode 26 #NCurPc: 3
D1: -- D2: -- Tos: 18 RegAddr: 0
New Opcode: 26 Length: 1 Data: Object/0 N: 26 PC: 3 OldOpLength: 0
Executing uInst: reset:0
#MIR: (Label←Reset Misc←Reset EUop←D2 Tag←Int RD2addr←MuxRdSel MuxRdSel←K K←0 NewArg←K W2addr←PcD1 
NewBotCxt←K NewtopCxt←K)
****************** Errors ******************
#IBUFN-7: 1 ← 0
#IBUFN-6: 1 ← 0
#IBUFN-5: 1 ← 0
#IBUFN-2: 1 ← 0
#IBUFN-0: 1 ← 0
VAD'-2: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 26 #$Opcode 26 #NCurPc: 3
D1: -- D2: Object/0 Tos: 18 RegAddr: 0
****************** Errors ******************
#IBUFN-7: 1 ← 0
#IBUFN-6: 1 ← 0
#IBUFN-5: 1 ← 0
#IBUFN-2: 1 ← 0
#IBUFN-0: 1 ← 0
VAD'-2: 1 ← 0
****************** Errors ******************
#OPCODE-7: 1 ← 0
#OPCODE-6: 1 ← 0
#OPCODE-5: 1 ← 0
#OPCODE-2: 1 ← 0
#OPCODE-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 26 #$Opcode 26 #NCurPc: 3
D1: Int/0 D2: -- Tos: 18 RegAddr: 0
Executing uInst: LAB0083:157
#MIR: (EUop←D2 Tag←Int RD2addr←MuxRdSel MuxRdSel←Arg Waddr←K WCxt←K K←IrqCount)
****************** Errors ******************
#IBUFN-7: 1 ← 0
#IBUFN-6: 1 ← 0
#IBUFN-5: 1 ← 0
#IBUFN-2: 1 ← 0
#IBUFN-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 26 #$Opcode 26 #NCurPc: 0
D1: -- D2: Object/0 Tos: 18 RegAddr: 0
****************** Errors ******************
#IBUFN-7: 1 ← 0
#IBUFN-6: 1 ← 0
#IBUFN-5: 1 ← 0
#IBUFN-2: 1 ← 0
#IBUFN-0: 1 ← 0
****************** Errors ******************
#OPCODE-7: 1 ← 0
#OPCODE-6: 1 ← 0
#OPCODE-5: 1 ← 0
#OPCODE-2: 1 ← 0
#OPCODE-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 26 #$Opcode 26 #NCurPc: 0
D1: Int/0 D2: -- Tos: 18 RegAddr: 0
Executing uInst: LAB0084:158
#MIR: (K←Pvar NewTos←K NextInstA←Done)
****************** Errors ******************
#IBUFN-7: 1 ← 0
#IBUFN-6: 1 ← 0
#IBUFN-5: 1 ← 0
#IBUFN-2: 1 ← 0
#IBUFN-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 26 #$Opcode 26 #NCurPc: 0
D1: -- D2: -- Tos: 18 RegAddr: 0
****************** Errors ******************
#IBUFN-7: 1 ← 0
#IBUFN-6: 1 ← 0
#IBUFN-5: 1 ← 0
#IBUFN-2: 1 ← 0
#IBUFN-0: 1 ← 0
****************** Errors ******************
#OPCODE-7: 1 ← 0
#OPCODE-6: 1 ← 0
#OPCODE-5: 1 ← 0
#OPCODE-2: 1 ← 0
#OPCODE-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 26 #$Opcode 26 #NCurPc: 0
D1: Int/1073741823 D2: -- Tos: 16 RegAddr: 0
New Opcode: 26 Length: 0 Data: Object/0 N: 26 PC: 0 OldOpLength: 0
Executing uInst: loadibuf:209
#MIR: (Label←LoadIBuf Cycle←R4 RD1addr←PcAddr W2addr←IBufD2PcD1 EUop←+16 Tag←Int 
Misc←ResetInitialRefill CondCode←NoFault NextInstA←Done NextInstB←IBufPageFault)
****************** Errors ******************
#IBUFN-7: 1 ← 0
#IBUFN-6: 1 ← 0
#IBUFN-5: 1 ← 0
#IBUFN-2: 1 ← 0
#IBUFN-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010010 $Opcode: 26 #$Opcode 26 #NCurPc: 0
D1: Int/0 D2: -- Tos: 16 RegAddr: 0
****************** Errors ******************
#IBUFN-7: 1 ← 0
#IBUFN-6: 1 ← 0
#IBUFN-5: 1 ← 0
#IBUFN-2: 1 ← 0
#IBUFN-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010001 $Opcode: 26 #$Opcode 26 #NCurPc: 0
D1: Int/16 D2: Ptr-63/133693439 Tos: 16 RegAddr: 0
****************** Errors ******************
#IBUFN-7: 1 ← 0
#IBUFN-6: 1 ← 0
#IBUFN-5: 1 ← 0
#IBUFN-2: 1 ← 0
#IBUFN-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 26 #$Opcode 26 #NCurPc: 0
D1: -- D2: XType/801043291 Tos: 16 RegAddr: 0
****************** Errors ******************
#IBUFN-7: 1 ← 0
#IBUFN-6: 1 ← 0
#IBUFN-5: 1 ← 0
#IBUFN-2: 1 ← 0
#IBUFN-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 144 #$Opcode 26 #NCurPc: 0
D1: -- D2: XType/939523823 Tos: 16 RegAddr: 0
****************** Errors ******************
#IBUFN-7: 1 ← 0
#IBUFN-6: 1 ← 0
#IBUFN-5: 1 ← 0
#IBUFN-2: 1 ← 0
#IBUFN-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 144 #$Opcode 144 #NCurPc: 0
D1: -- D2: XType/1046321139 Tos: 16 RegAddr: 0
New Opcode: 144 Length: 5 Data: Code/100663424 N: 128 PC: 0 OldOpLength: 5
Executing uInst: pconst:80
#MIR: (Label←PConst EUop←D2<2>Shl24/D1<30> Tag←D2<8:7> RD2addr←MuxRdSel MuxRdSel←K K←PtrTypeBits 
RD1addr←IBufData Waddr←TOS' TOS'←TOS+1 NewTos←Tos' NextInstA←Done)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 37 #$Opcode 144 #NCurPc: 5
D1: Code/100663424 D2: Object/0 Tos: 16 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 37 #$Opcode 37 #NCurPc: 5
D1: Code/100663424 D2: -- Tos: 17 RegAddr: 0
New Opcode: 37 Length: 0 Data: Object/0 N: 2 PC: 5 OldOpLength: 0
Executing uInst: loadibuf:209
#MIR: (Label←LoadIBuf Cycle←R4 RD1addr←PcAddr W2addr←IBufD2PcD1 EUop←+16 Tag←Int 
Misc←ResetInitialRefill CondCode←NoFault NextInstA←Done NextInstB←IBufPageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010010 $Opcode: 37 #$Opcode 37 #NCurPc: 5
D1: Int/16 D2: -- Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010001 $Opcode: 37 #$Opcode 37 #NCurPc: 5
D1: Int/32 D2: XType/1052630751 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 37 #$Opcode 37 #NCurPc: 5
D1: -- D2: XType/996638711 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 37 #$Opcode 37 #NCurPc: 5
D1: -- D2: Int/1072168443 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 37 #$Opcode 37 #NCurPc: 5
D1: -- D2: XType/1054604287 Tos: 17 RegAddr: 0
New Opcode: 37 Length: 2 Data: Object/2 N: 2 PC: 5 OldOpLength: 2
Executing uInst: ireg.x←:37
#MIR: (Label←IReg.X← EUop←D1 Tag←D1 Raddr←Tos Waddr←IBufN WCxt←K K←256 NextInstA←Done)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 144 #$Opcode 37 #NCurPc: 7
D1: Code/100663424 D2: -- Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 144 #$Opcode 144 #NCurPc: 7
D1: Code/100663424 D2: -- Tos: 17 RegAddr: 0
New Opcode: 144 Length: 5 Data: Code/100663360 N: 64 PC: 7 OldOpLength: 5
Executing uInst: pconst:80
#MIR: (Label←PConst EUop←D2<2>Shl24/D1<30> Tag←D2<8:7> RD2addr←MuxRdSel MuxRdSel←K K←PtrTypeBits 
RD1addr←IBufData Waddr←TOS' TOS'←TOS+1 NewTos←Tos' NextInstA←Done)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 37 #$Opcode 144 #NCurPc: 12
D1: Code/100663360 D2: Object/0 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 37 #$Opcode 37 #NCurPc: 12
D1: Code/100663360 D2: -- Tos: 18 RegAddr: 0
New Opcode: 37 Length: 2 Data: Object/9 N: 9 PC: 12 OldOpLength: 2
Executing uInst: ireg.x←:37
#MIR: (Label←IReg.X← EUop←D1 Tag←D1 Raddr←Tos Waddr←IBufN WCxt←K K←256 NextInstA←Done)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 56 #$Opcode 37 #NCurPc: 14
D1: Code/100663360 D2: Code/100663424 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 56 #$Opcode 56 #NCurPc: 14
D1: Code/100663360 D2: -- Tos: 18 RegAddr: 0
New Opcode: 56 Length: 4 Data: Object/2097216 N: 64 PC: 14 OldOpLength: 4
Executing uInst: gvar:56
#MIR: (Label←GVar EUop←+ Tag←Int RD1addr←IBufData RD2addr←MuxRdSel MuxRdSel←K K←ValueCellOffset 
W2addr←MarD1)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 26 #$Opcode 56 #NCurPc: 18
D1: Object/2097216 D2: Object/1 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 26 #$Opcode 56 #NCurPc: 18
D1: Int/2097217 D2: -- Tos: 18 RegAddr: 0
Executing uInst: LAB0002:60
#MIR: (Cycle←R1 W2addr←MarMem CondCode←NoFault NextInstB←PageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 26 #$Opcode 56 #NCurPc: 18
D1: Code/100663360 D2: Code/100663424 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 26 #$Opcode 56 #NCurPc: 18
D1: -- D2: Int/16 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 26 #$Opcode 56 #NCurPc: 18
D1: Code/100663360 D2: Code/100663424 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 26 #$Opcode 56 #NCurPc: 18
D1: -- D2: -- Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 26 #$Opcode 56 #NCurPc: 18
D1: -- D2: -- Tos: 18 RegAddr: 0
Executing uInst: pagefault:212
#MIR: (Label←PageFault EUop←D1 Tag←Int RD1addr←Mar Waddr←Tos' Tos'←Tos+1 NewTos←Tos' NewArg←K K←1 
Misc←OpLength=0 CondCode←FramesAvail Cwrite NextInstB←DumpFrame)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 26 #$Opcode 56 #NCurPc: 18
D1: Int/2097217 D2: Code/100663424 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 26 #$Opcode 56 #NCurPc: 18
D1: Int/2097217 D2: -- Tos: 19 RegAddr: 0
Executing uInst: LAB0072:146
#MIR: (EUop←D1 Tag←D1 Raddr←K K←PFCode RCxt←K W2addr←MarD1 NextInstA←Fn1)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 56 #$Opcode 56 #NCurPc: 14
D1: Code/100663424 D2: -- Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 56 #$Opcode 56 #NCurPc: 14
D1: Code/100663424 D2: -- Tos: 19 RegAddr: 0
Executing uInst: fn1:197
#MIR: (Label←Fn1 EUop←+4 Tag←D1 RD1addr←Mar W2addr←MarD1 NewArg2←Arg NewArg←K K←StkHdr CondCode←CCodeP
 NextInstB←Fn5)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 56 #$Opcode 56 #NCurPc: 14
D1: Code/100663424 D2: Code/100663360 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 56 #$Opcode 56 #NCurPc: 14
D1: Code/100663428 D2: -- Tos: 19 RegAddr: 0
Executing uInst: LAB0041:115
#MIR: (Cycle←R4 WCxt←Next Waddr←Arg<6>/QW<2> EUop←+4 Tag←D1 RD1addr←Mar W2addr←MarD1 CondCode←NoFault 
NextInstB←PageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010010 $Opcode: 56 #$Opcode 56 #NCurPc: 14
D1: Code/100663428 D2: Code/100663360 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010001 $Opcode: 56 #$Opcode 56 #NCurPc: 14
D1: Code/100663432 D2: Int/16 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 56 #$Opcode 56 #NCurPc: 14
D1: -- D2: Int/0 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 56 #$Opcode 56 #NCurPc: 14
D1: -- D2: Code/100663424 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 56 #$Opcode 56 #NCurPc: 14
D1: -- D2: Code/100663424 Tos: 19 RegAddr: 0
Executing uInst: LAB0042:116
#MIR: (EUop←D2 Tag←D2 RD2addr←Unbound Waddr←K K←PVar WCxt←Next Misc←WriteOctal NewArg←Arg2)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 56 #$Opcode 56 #NCurPc: 14
D1: Int/2097217 D2: Ptr-32/0 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 56 #$Opcode 56 #NCurPc: 14
D1: Ptr-32/0 D2: -- Tos: 19 RegAddr: 0
Executing uInst: fn2:198
#MIR: (Label←Fn2 EUop←D2 Tag←D2 RD2addr←Nil Waddr←K K←IVar WCxt←Next Misc←WriteOctal)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 56 #$Opcode 56 #NCurPc: 14
D1: Int/2097217 D2: Atm/3584 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 56 #$Opcode 56 #NCurPc: 14
D1: Atm/3584 D2: -- Tos: 19 RegAddr: 0
Executing uInst: LAB0043:117
#MIR: (EUop←D2 Tag←Int RD2addr←PC Waddr←K K←Pc Misc←Oplength=0&SetInitialRefill)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 56 #$Opcode 56 #NCurPc: 14
D1: Int/2097217 D2: Int/14 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 56 #$Opcode 56 #NCurPc: 14
D1: Int/14 D2: -- Tos: 19 RegAddr: 0
Executing uInst: LAB0044:118
#MIR: (EUop←+ Tag←Int RD1addr←Mar RD2addr←MuxRdSel MuxRdSel←Arg W2Addr←MarD1)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 56 #$Opcode 56 #NCurPc: 14
D1: Code/100663432 D2: Object/1 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 56 #$Opcode 56 #NCurPc: 14
D1: Int/100663433 D2: -- Tos: 19 RegAddr: 0
Executing uInst: LAB0045:119
#MIR: (Cycle←R1 Waddr←K WCxt←Next K←Pc)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 56 #$Opcode 56 #NCurPc: 14
D1: Int/2097217 D2: Code/100663360 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 56 #$Opcode 56 #NCurPc: 14
D1: Int/1073741823 D2: Int/560 Tos: 19 RegAddr: 0
Executing uInst: LAB0046:120
#MIR: (EUop←D1 Tag←Int Raddr←K RCxt←Next K←PC W2addr←PCD1)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 56 #$Opcode 56 #NCurPc: 14
D1: Int/560 D2: Int/16 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 56 #$Opcode 56 #NCurPc: 14
D1: Int/560 D2: -- Tos: 19 RegAddr: 0
Executing uInst: LAB0047:121
#MIR: (EUop←D2 Tag←Int RD2addr←MuxRdSel MuxRdSel←K K←Ivar NewArg2←K W2addr←MarD1 NewArg←Arg' 
Arg'←Arg-1 CondCode←Arg#0 NextInstB←Fn3)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 0 #$Opcode 56 #NCurPc: 16
D1: Int/2097217 D2: Object/8 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 0 #$Opcode 56 #NCurPc: 16
D1: Int/8 D2: -- Tos: 19 RegAddr: 0
Executing uInst: LAB0048:122
#MIR: (EUop←+ Tag←Int RD1addr←Mar RD2addr←MuxRdSel MuxRdSel←Arg W2addr←Tmp1D1)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 0 #$Opcode 56 #NCurPc: 16
D1: Int/8 D2: Object/0 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 0 #$Opcode 56 #NCurPc: 16
D1: Int/8 D2: -- Tos: 19 RegAddr: 0
Executing uInst: LAB0049:123
#MIR: (RD2addr←Tmp1 NewArg←D2)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 0 #$Opcode 56 #NCurPc: 16
D1: Int/2097217 D2: Int/8 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 0 #$Opcode 56 #NCurPc: 16
D1: Int/1073741823 D2: -- Tos: 19 RegAddr: 0
Executing uInst: LAB0050:124
#MIR: (EUop←D1 Tag←D1 Raddr←Tos WCxt←Next Waddr←Arg NewTos←Tos' Tos'←Tos-1 NewArg←Arg' Arg'←Arg-1 
CondCode←Arg=Arg2 NextInstB←Rpt)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 0 #$Opcode 56 #NCurPc: 16
D1: Int/2097217 D2: Code/100663360 Tos: 19 RegAddr: 0
****************** Errors ******************
#CONDA: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 0 #$Opcode 56 #NCurPc: 16
D1: Int/2097217 D2: -- Tos: 18 RegAddr: 0
Executing uInst: fn3:199
#MIR: (Label←Fn3 EUop←D1<24>/D2<8> Tag←D1 RD2addr←MuxRdSel MuxRdSel←Tos Raddr←K Waddr←K K←StkHdr)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 0 #$Opcode 56 #NCurPc: 16
D1: -- D2: Object/18 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 0 #$Opcode 56 #NCurPc: 16
D1: XType/1073741586 D2: -- Tos: 18 RegAddr: 0
Executing uInst: LAB0051:125
#MIR: (EUop←D2 Tag←D2 Dswap Raddr←K K←StkHdr RCxt←Next WCxt←Next NewTos←D2 NewTopCxt←Next 
NextInstA←Done)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 0 #$Opcode 56 #NCurPc: 16
D1: -- D2: Int/16 Tos: 18 RegAddr: 0
****************** Errors ******************
D1-31: 0 ← 1
D1-29: 0 ← 1
D1-28: 0 ← 1
D1-27: 0 ← 1
D1-26: 0 ← 1
D1-25: 0 ← 1
D1-24: 0 ← 1
D1-23: 0 ← 1
D1-22: 0 ← 1
D1-21: 0 ← 1
D1-20: 0 ← 1
D1-19: 0 ← 1
D1-18: 0 ← 1
D1-17: 0 ← 1
D1-16: 0 ← 1
D1-15: 0 ← 1
D1-14: 0 ← 1
D1-13: 0 ← 1
D1-12: 0 ← 1
D1-11: 0 ← 1
D1-10: 0 ← 1
D1-9: 0 ← 1
D1-8: 0 ← 1
D1-7: 0 ← 1
D1-6: 0 ← 1
D1-5: 0 ← 1
D1-3: 0 ← 1
D1-2: 0 ← 1
D1-1: 0 ← 1
D1-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 0 #$Opcode 0 #NCurPc: 16
D1: Int/16 D2: -- Tos: 16 RegAddr: 0
New Opcode: 0 Length: 0 Data: Object/0 N: 32 PC: 16 OldOpLength: 0
Executing uInst: loadibuf:209
#MIR: (Label←LoadIBuf Cycle←R4 RD1addr←PcAddr W2addr←IBufD2PcD1 EUop←+16 Tag←Int 
Misc←ResetInitialRefill CondCode←NoFault NextInstA←Done NextInstB←IBufPageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010010 $Opcode: 0 #$Opcode 0 #NCurPc: 16
D1: Int/560 D2: Atm/3584 Tos: 16 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010001 $Opcode: 0 #$Opcode 0 #NCurPc: 16
D1: Int/576 D2: List/80235720 Tos: 16 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 0 #$Opcode 0 #NCurPc: 16
D1: -- D2: Int/862283366 Tos: 16 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 200 #$Opcode 0 #NCurPc: 16
D1: -- D2: XType/1069448763 Tos: 16 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 200 #$Opcode 200 #NCurPc: 16
D1: -- D2: XType/526176237 Tos: 16 RegAddr: 0
New Opcode: 200 Length: 1 Data: Object/0 N: 145 PC: 16 OldOpLength: 1
Executing uInst: vark:233
#MIR: (Label←Vark EUop←D1 Tag←D1 Raddr←0<4>/OpCode<4> Waddr←Tos' Tos'←Tos+1 NewTos←Tos' NextInstA←Done
)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 145 #$Opcode 200 #NCurPc: 17
D1: Int/2097217 D2: -- Tos: 16 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 145 #$Opcode 145 #NCurPc: 17
D1: Int/2097217 D2: -- Tos: 17 RegAddr: 0
New Opcode: 145 Length: 5 Data: Int/16777215 N: 255 PC: 17 OldOpLength: 5
Executing uInst: intconst:81
#MIR: (Label←IntConst EUop←D1 Tag←Int RD1addr←IBufData Waddr←TOS' TOS'←TOS+1 NewTos←Tos' 
NextInstA←Done)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 16 #$Opcode 145 #NCurPc: 22
D1: Int/16777215 D2: Ptr-32/0 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 16 #$Opcode 16 #NCurPc: 22
D1: Int/16777215 D2: -- Tos: 18 RegAddr: 0
New Opcode: 16 Length: 0 Data: Object/0 N: 47 PC: 22 OldOpLength: 0
Executing uInst: loadibuf:209
#MIR: (Label←LoadIBuf Cycle←R4 RD1addr←PcAddr W2addr←IBufD2PcD1 EUop←+16 Tag←Int 
Misc←ResetInitialRefill CondCode←NoFault NextInstA←Done NextInstB←IBufPageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010010 $Opcode: 16 #$Opcode 16 #NCurPc: 22
D1: Int/576 D2: Int/2097217 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010001 $Opcode: 16 #$Opcode 16 #NCurPc: 22
D1: Int/592 D2: XType/1071816350 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 16 #$Opcode 16 #NCurPc: 22
D1: -- D2: Float/1073477457 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 16 #$Opcode 16 #NCurPc: 22
D1: -- D2: XType/1004404446 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 16 #$Opcode 16 #NCurPc: 22
D1: -- D2: Int/1073217523 Tos: 18 RegAddr: 0
New Opcode: 16 Length: 1 Data: Object/0 N: 47 PC: 22 OldOpLength: 1
Executing uInst: and:16
#MIR: (Label←And EUop←And Tag←Int Raddr←Tos RD2addr←Raddr-1 Waddr←Tos' Tos'←Tos-1 NewTos←Tos' 
CondCode←IntegerD1D2 CWrite NextInstA←Done NextInstB←Ufn-2)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 47 #$Opcode 16 #NCurPc: 23
D1: Int/16777215 D2: Int/2097217 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 47 #$Opcode 47 #NCurPc: 23
D1: Int/2097217 D2: -- Tos: 17 RegAddr: 0
New Opcode: 47 Length: 2 Data: Object/10 N: 10 PC: 23 OldOpLength: 2
Executing uInst: lrsh.n:228
#MIR: (Label←Lrsh.N EUop←D1 Tag←Int Raddr←Tos W2addr←MarD1 NewArg←IBufN CondCode←Integerp 
NextInstB←Ufn-1d)
****************** Errors ******************
D1-23: 1 ← 0
D1-22: 1 ← 0
D1-20: 1 ← 0
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/2097217 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-23: 1 ← 0
D1-22: 1 ← 0
D1-20: 1 ← 0
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/2097217 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0031:105
#MIR: (Arg'←Arg-1 NewArg←Arg' CondCode←Arg=0 NextInstA←Done)
****************** Errors ******************
D1-23: 1 ← 0
D1-22: 1 ← 0
D1-20: 1 ← 0
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/2097217 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-23: 1 ← 0
D1-22: 1 ← 0
D1-20: 1 ← 0
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/1073741823 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/2097217 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-23: 1 ← 0
D1-22: 1 ← 0
D1-20: 1 ← 0
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/1048608 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-22: 1 ← 0
D1-21: 1 ← 0
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/1048608 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-22: 1 ← 0
D1-21: 1 ← 0
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/524304 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-21: 1 ← 0
D1-20: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/524304 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-21: 1 ← 0
D1-20: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/262152 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-20: 1 ← 0
D1-19: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/262152 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-20: 1 ← 0
D1-19: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/131076 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/131076 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/65538 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/65538 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/32769 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/32769 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/16384 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/16384 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/8192 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/8192 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/4096 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/4096 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 35 #NCurPc: 25
D1: Int/2048 D2: -- Tos: 17 RegAddr: 0
New Opcode: 35 Length: 2 Data: Object/0 N: 0 PC: 25 OldOpLength: 2
Executing uInst: settype:35
#MIR: (Label←SetType EUop←D2<2>Shl24/D1<30> Tag←D2<8:7> Raddr←Tos RD2addr←MuxRdSel MuxRdSel←IBufN 
Waddr←Tos NextInstA←Done)
****************** Errors ******************
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 20 #$Opcode 35 #NCurPc: 27
D1: Int/2048 D2: Object/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 20 #$Opcode 20 #NCurPc: 27
D1: Object/2048 D2: -- Tos: 17 RegAddr: 0
New Opcode: 20 Length: 1 Data: Object/0 N: 32 PC: 27 OldOpLength: 1
Executing uInst: copy:20
#MIR: (Label←Copy EUop←D1 Tag←D1 Raddr←Tos Waddr←Tos' Tos'←Tos+1 NewTos←Tos' NextInstA←Done)
****************** Errors ******************
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 32 #$Opcode 20 #NCurPc: 28
D1: Object/2048 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 32 #$Opcode 32 #NCurPc: 28
D1: Object/2048 D2: -- Tos: 18 RegAddr: 0
New Opcode: 32 Length: 2 Data: Object/0 N: 0 PC: 28 OldOpLength: 2
Executing uInst: getptr:32
#MIR: (Label←Getptr EUop←+ Tag←D2 Dswap Raddr←Tos RD1addr←IBufData W2addr←MarD1 Condcode←PointerpD2 
NextInstB←Ufn-1d)
****************** Errors ******************
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 185 #$Opcode 32 #NCurPc: 30
D1: Object/0 D2: Object/2048 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 185 #$Opcode 32 #NCurPc: 30
D1: Object/2048 D2: -- Tos: 18 RegAddr: 0
Executing uInst: LAB0033:65
#MIR: (Cycle←R1 Waddr←Tos CondCode←NoFault Cwrite NextInstA←Done NextInstB←PageFault)
****************** Errors ******************
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-6: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
VAD'-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 185 #$Opcode 32 #NCurPc: 30
D1: Object/2048 D2: Object/2048 Tos: 18 RegAddr: 0
****************** Errors ******************
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-6: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
VAD'-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 185 #$Opcode 185 #NCurPc: 30
D1: Int/1073741823 D2: Int/16 Tos: 18 RegAddr: 0
New Opcode: 185 Length: 1 Data: Object/0 N: 26 PC: 30 OldOpLength: 1
Executing uInst: vark←:234
#MIR: (Label←Vark← EUop←D1 Tag←D1 Raddr←Tos Waddr←0<4>/OpCode<4> NextInstA←Done)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 26 #$Opcode 185 #NCurPc: 31
D1: Int/16 D2: Object/2048 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 26 #$Opcode 26 #NCurPc: 31
D1: Int/16 D2: -- Tos: 18 RegAddr: 0
New Opcode: 26 Length: 1 Data: Object/0 N: 16 PC: 31 OldOpLength: 1
Executing uInst: '1:26
#MIR: (Label←'1 EUop←D2 Tag←Int RD2addr←MuxRdSel MuxRdSel←K K←1 Waddr←Tos' Tos'←Tos+1 NewTos←Tos' 
NextInstA←Done)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 16 #$Opcode 26 #NCurPc: 0
D1: Int/16 D2: Object/1 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 16 #$Opcode 16 #NCurPc: 0
D1: Int/1 D2: -- Tos: 19 RegAddr: 0
New Opcode: 16 Length: 1 Data: Object/0 N: 26 PC: 0 OldOpLength: 1
Executing uInst: and:16
#MIR: (Label←And EUop←And Tag←Int Raddr←Tos RD2addr←Raddr-1 Waddr←Tos' Tos'←Tos-1 NewTos←Tos' 
CondCode←IntegerD1D2 CWrite NextInstA←Done NextInstB←Ufn-2)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 26 #$Opcode 16 #NCurPc: 1
D1: Int/1 D2: Int/16 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 26 #$Opcode 26 #NCurPc: 1
D1: Int/0 D2: -- Tos: 18 RegAddr: 0
New Opcode: 26 Length: 1 Data: Object/0 N: 10 PC: 1 OldOpLength: 1
Executing uInst: '1:228
#MIR: (Label←'1 EUop←D2 Tag←Int RD2addr←MuxRdSel MuxRdSel←K K←1 Waddr←Tos' Tos'←Tos+1 NewTos←Tos' 
NextInstA←Done)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 10 #$Opcode 26 #NCurPc: 2
D1: Int/0 D2: Object/1 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 10 #$Opcode 10 #NCurPc: 2
D1: Int/1 D2: -- Tos: 19 RegAddr: 0
New Opcode: 10 Length: 1 Data: Object/0 N: 53 PC: 2 OldOpLength: 1
Executing uInst: eq:10
#MIR: (Label←Eq Raddr←Tos RD2addr←Raddr-1 Tos'←Tos-1 NewTos←Tos' CondCode←D1=D2 NextInstA←SetT 
NextInstB←SetNil)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 53 #$Opcode 10 #NCurPc: 3
D1: Int/1 D2: Int/0 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 53 #$Opcode 10 #NCurPc: 3
D1: Int/1073741823 D2: -- Tos: 18 RegAddr: 0
Executing uInst: setnil:222
#MIR: (Label←SetNil EUop←D2 Tag←D2 RD2addr←Nil Waddr←Tos NextInstA←Done)
****************** Errors ******************
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-6: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
VAD'-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 53 #$Opcode 10 #NCurPc: 3
D1: Int/0 D2: Atm/3584 Tos: 18 RegAddr: 0
****************** Errors ******************
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-6: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
VAD'-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 53 #$Opcode 53 #NCurPc: 3
D1: Atm/3584 D2: -- Tos: 18 RegAddr: 0
New Opcode: 53 Length: 2 Data: Object/7 N: 7 PC: 3 OldOpLength: 2
Executing uInst: fjump:53
#MIR: (Label←FJump EUop←nop Raddr←Tos Tos'←Tos-1 NewTos←Tos' Rd2addr←Nil Condcode←D1#D2 NextInstA←Done
 NextInstB←DoJmp)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 145 #$Opcode 53 #NCurPc: 5
D1: Atm/3584 D2: Atm/3584 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 145 #$Opcode 53 #NCurPc: 5
D1: Int/1073741823 D2: -- Tos: 17 RegAddr: 0
Executing uInst: dojmp:209
#MIR: (Label←DoJmp EUop←+ Tag←Int RD2addr←PC RD1addr←IBufData W2addr←PCD1 
Misc←Oplength=0&SetInitialRefill NextInstA←Dojmp1)
****************** Errors ******************
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-6: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
VAD'-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 145 #$Opcode 53 #NCurPc: 5
D1: Object/7 D2: Int/581 Tos: 17 RegAddr: 0
****************** Errors ******************
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-6: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
VAD'-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 145 #$Opcode 53 #NCurPc: 5
D1: Int/588 D2: -- Tos: 17 RegAddr: 0
Executing uInst: dojmp1:193
#MIR: (Label←DoJmp1 NextInstA←Done)
****************** Errors ******************
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-6: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
VAD'-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 145 #$Opcode 53 #NCurPc: 12
D1: Object/2048 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-30: 1 ← 0
D1-11: 0 ← 1
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-6: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
VAD'-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 145 #$Opcode 145 #NCurPc: 12
D1: Int/1073741823 D2: -- Tos: 17 RegAddr: 0
New Opcode: 145 Length: 0 Data: Object/0 N: 1 PC: 12 OldOpLength: 0
Executing uInst: loadibuf:209
#MIR: (Label←LoadIBuf Cycle←R4 RD1addr←PcAddr W2addr←IBufD2PcD1 EUop←+16 Tag←Int 
Misc←ResetInitialRefill CondCode←NoFault NextInstA←Done NextInstB←IBufPageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010010 $Opcode: 145 #$Opcode 145 #NCurPc: 12
D1: Int/576 D2: Ptr-32/0 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010001 $Opcode: 145 #$Opcode 145 #NCurPc: 12
D1: Int/592 D2: XType/1071816350 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 145 #$Opcode 145 #NCurPc: 12
D1: -- D2: Float/1073477457 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 145 #$Opcode 145 #NCurPc: 12
D1: -- D2: XType/1004404446 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 145 #$Opcode 145 #NCurPc: 12
D1: -- D2: Int/1073217523 Tos: 17 RegAddr: 0
New Opcode: 145 Length: 0 Data: Object/0 N: 1 PC: 12 OldOpLength: 0
Executing uInst: loadibuf:209
#MIR: (Label←LoadIBuf Cycle←R4 RD1addr←PcAddr W2addr←IBufD2PcD1 EUop←+16 Tag←Int 
Misc←ResetInitialRefill CondCode←NoFault NextInstA←Done NextInstB←IBufPageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010010 $Opcode: 145 #$Opcode 145 #NCurPc: 12
D1: Int/592 D2: Ptr-32/0 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010001 $Opcode: 145 #$Opcode 145 #NCurPc: 12
D1: Int/608 D2: Float/871219192 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 145 #$Opcode 145 #NCurPc: 12
D1: -- D2: XType/747145454 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 145 #$Opcode 145 #NCurPc: 12
D1: -- D2: Object/0 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 145 #$Opcode 145 #NCurPc: 12
D1: -- D2: Object/0 Tos: 17 RegAddr: 0
New Opcode: 145 Length: 5 Data: Int/1 N: 1 PC: 12 OldOpLength: 5
Executing uInst: intconst:81
#MIR: (Label←IntConst EUop←D1 Tag←Int RD1addr←IBufData Waddr←TOS' TOS'←TOS+1 NewTos←Tos' 
NextInstA←Done)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 201 #$Opcode 145 #NCurPc: 17
D1: Int/1 D2: Ptr-32/0 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 201 #$Opcode 201 #NCurPc: 17
D1: Int/1 D2: -- Tos: 18 RegAddr: 0
New Opcode: 201 Length: 1 Data: Object/0 N: 17 PC: 17 OldOpLength: 1
Executing uInst: vark:233
#MIR: (Label←Vark EUop←D1 Tag←D1 Raddr←0<4>/OpCode<4> Waddr←Tos' Tos'←Tos+1 NewTos←Tos' NextInstA←Done
)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 17 #$Opcode 201 #NCurPc: 18
D1: Int/16 D2: Int/2097217 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 17 #$Opcode 17 #NCurPc: 18
D1: Int/16 D2: -- Tos: 19 RegAddr: 0
New Opcode: 17 Length: 1 Data: Object/0 N: 33 PC: 18 OldOpLength: 1
Executing uInst: or:17
#MIR: (Label←Or EUop←Or Tag←Int Raddr←Tos RD2addr←Raddr-1 Waddr←Tos' Tos'←Tos-1 NewTos←Tos' 
CondCode←IntegerD1D2 CWrite NextInstA←Done NextInstB←Ufn-2)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 33 #$Opcode 17 #NCurPc: 19
D1: Int/16 D2: Int/1 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 33 #$Opcode 33 #NCurPc: 19
D1: Int/17 D2: -- Tos: 18 RegAddr: 0
New Opcode: 33 Length: 2 Data: Object/0 N: 0 PC: 19 OldOpLength: 2
Executing uInst: putptr:228
#MIR: (Label←Putptr EUop←D2 Tag←D2 Raddr←Tos RD2addr←Raddr-1 W2addr←MarD1 Condcode←PointerpD2 
NextInstB←Ufn-2d)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 60 #$Opcode 33 #NCurPc: 21
D1: Int/17 D2: Object/2048 Tos: 18 RegAddr: 0
****************** Errors ******************
#CONDA: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 60 #$Opcode 33 #NCurPc: 21
D1: Object/2048 D2: -- Tos: 18 RegAddr: 0
Executing uInst: LAB0034:229
#MIR: (EUop←+ Tag←D1 RD1addr←Mar RD2addr←MuxRdSel MuxRdSel←IBufN W2addr←MarD1)
****************** Errors ******************
D1-30: 1 ← 0
D1-11: 0 ← 1
D1-4: 1 ← 0
D1-0: 1 ← 0
VAD-11: 0 ← 1
VAD'-11: 1 ← 0
VAD'-4: 0 ← 1
VAD'-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 60 #$Opcode 33 #NCurPc: 21
D1: Object/2048 D2: Object/0 Tos: 18 RegAddr: 0
****************** Errors ******************
D1-30: 1 ← 0
D1-11: 0 ← 1
D1-4: 1 ← 0
D1-0: 1 ← 0
VAD-11: 0 ← 1
VAD'-11: 1 ← 0
VAD'-4: 0 ← 1
VAD'-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 60 #$Opcode 33 #NCurPc: 21
D1: Object/2048 D2: -- Tos: 18 RegAddr: 0
Executing uInst: LAB0035:109
#MIR: (Cycle←W1 Dswap Raddr←Tos Tos'←Tos-1 NewTos←Tos' CondCode←NoFault CWrite NextInstA←Done 
NextInstB←PageFault)
****************** Errors ******************
D1-30: 1 ← 0
D1-11: 0 ← 1
D1-4: 1 ← 0
D1-0: 1 ← 0
VAD-11: 0 ← 1
VAD'-11: 1 ← 0
VAD'-4: 0 ← 1
VAD'-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 60 #$Opcode 33 #NCurPc: 21
D1: Object/2048 D2: Int/17 Tos: 18 RegAddr: 0
****************** Errors ******************
D1-30: 1 ← 0
D1-11: 0 ← 1
D1-4: 1 ← 0
D1-0: 1 ← 0
VAD-11: 0 ← 1
VAD'-11: 1 ← 0
VAD'-4: 0 ← 1
VAD'-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 60 #$Opcode 60 #NCurPc: 21
D1: Int/1073741823 D2: -- Tos: 17 RegAddr: 0
New Opcode: 60 Length: 0 Data: Object/0 N: 124 PC: 21 OldOpLength: 0
Executing uInst: loadibuf:209
#MIR: (Label←LoadIBuf Cycle←R4 RD1addr←PcAddr W2addr←IBufD2PcD1 EUop←+16 Tag←Int 
Misc←ResetInitialRefill CondCode←NoFault NextInstA←Done NextInstB←IBufPageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010010 $Opcode: 60 #$Opcode 60 #NCurPc: 21
D1: Int/608 D2: Ptr-32/0 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010001 $Opcode: 60 #$Opcode 60 #NCurPc: 21
D1: Int/624 D2: Object/0 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 60 #$Opcode 60 #NCurPc: 21
D1: -- D2: Object/0 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 60 #$Opcode 60 #NCurPc: 21
D1: -- D2: Object/0 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 60 #$Opcode 60 #NCurPc: 21
D1: -- D2: Object/0 Tos: 17 RegAddr: 0
New Opcode: 60 Length: 1 Data: Object/0 N: 124 PC: 21 OldOpLength: 1
Executing uInst: reset-vmm:219
#MIR: (Label←Reset-Vmm Misc←Reset-Vmm NextInstA←Done)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 124 #$Opcode 60 #NCurPc: 22
D1: Object/2048 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-30: 1 ← 0
D1-11: 0 ← 1
D1-4: 1 ← 0
D1-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 124 #$Opcode 124 #NCurPc: 22
D1: Int/1073741823 D2: -- Tos: 17 RegAddr: 0
New Opcode: 124 Length: 1 Data: Object/0 N: 255 PC: 22 OldOpLength: 1
Executing uInst: retnp:220
#MIR: (Label←Retnp EUop←D1 Tag←Int Raddr←K K←StkHdr CondCode←TrapOnExit NextInstA←Ufn-0)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 255 #$Opcode 124 #NCurPc: 23
D1: Int/16 D2: -- Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 255 #$Opcode 124 #NCurPc: 23
D1: Int/16 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0065:139
#MIR: (EUop←D1 Tag←Int RCxt←Prev Raddr←K K←Pc W2Addr←PcD1 NewTopCxt←Prev 
Misc←Oplength=0&SetInitialRefill)
****************** Errors ******************
VAD-11: 0 ← 1
VAD'-11: 1 ← 0
VAD'-4: 0 ← 1
VAD'-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 255 #$Opcode 124 #NCurPc: 23
D1: Int/14 D2: XType/1073741586 Tos: 17 RegAddr: 0
****************** Errors ******************
VAD-11: 0 ← 1
VAD'-11: 1 ← 0
VAD'-4: 0 ← 1
VAD'-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 255 #$Opcode 124 #NCurPc: 23
D1: Int/14 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0066:140
#MIR: (Dswap Raddr←K K←StkHdr NewTos←D2 NextInstA←Done)
****************** Errors ******************
VAD-11: 0 ← 1
VAD'-11: 1 ← 0
VAD'-4: 0 ← 1
VAD'-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 255 #$Opcode 124 #NCurPc: 14
D1: Int/14 D2: XType/1073741586 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-31: 1 ← 0
D1-29: 1 ← 0
D1-28: 1 ← 0
D1-27: 1 ← 0
D1-26: 1 ← 0
D1-25: 1 ← 0
D1-24: 1 ← 0
D1-23: 1 ← 0
D1-22: 1 ← 0
D1-21: 1 ← 0
D1-20: 1 ← 0
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-0: 1 ← 0
VAD-11: 0 ← 1
VAD'-11: 1 ← 0
VAD'-4: 0 ← 1
VAD'-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 255 #$Opcode 255 #NCurPc: 14
D1: Int/1073741823 D2: -- Tos: 18 RegAddr: 0
New Opcode: 255 Length: 0 Data: Object/0 N: 255 PC: 14 OldOpLength: 0
Executing uInst: loadibuf:209
#MIR: (Label←LoadIBuf Cycle←R4 RD1addr←PcAddr W2addr←IBufD2PcD1 EUop←+16 Tag←Int 
Misc←ResetInitialRefill CondCode←NoFault NextInstA←Done NextInstB←IBufPageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010010 $Opcode: 255 #$Opcode 255 #NCurPc: 14
D1: Int/0 D2: Code/100663424 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010001 $Opcode: 255 #$Opcode 255 #NCurPc: 14
D1: Int/16 D2: Ptr-63/133693439 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 255 #$Opcode 255 #NCurPc: 14
D1: -- D2: XType/801043291 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 255 #$Opcode 255 #NCurPc: 14
D1: -- D2: XType/939523823 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 255 #$Opcode 255 #NCurPc: 14
D1: -- D2: XType/1046321139 Tos: 18 RegAddr: 0
New Opcode: 255 Length: 0 Data: Object/0 N: 255 PC: 14 OldOpLength: 0
Executing uInst: loadibuf:209
#MIR: (Label←LoadIBuf Cycle←R4 RD1addr←PcAddr W2addr←IBufD2PcD1 EUop←+16 Tag←Int 
Misc←ResetInitialRefill CondCode←NoFault NextInstA←Done NextInstB←IBufPageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010010 $Opcode: 255 #$Opcode 255 #NCurPc: 14
D1: Int/16 D2: Code/100663424 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010001 $Opcode: 255 #$Opcode 255 #NCurPc: 14
D1: Int/32 D2: XType/1052630751 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 255 #$Opcode 255 #NCurPc: 14
D1: -- D2: XType/996638711 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 56 #$Opcode 255 #NCurPc: 14
D1: -- D2: Int/1072168443 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 56 #$Opcode 56 #NCurPc: 14
D1: -- D2: XType/1054604287 Tos: 18 RegAddr: 0
New Opcode: 56 Length: 4 Data: Object/2097216 N: 64 PC: 14 OldOpLength: 4
Executing uInst: gvar:56
#MIR: (Label←GVar EUop←+ Tag←Int RD1addr←IBufData RD2addr←MuxRdSel MuxRdSel←K K←ValueCellOffset 
W2addr←MarD1)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 26 #$Opcode 56 #NCurPc: 18
D1: Object/2097216 D2: Object/1 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 26 #$Opcode 56 #NCurPc: 18
D1: Int/2097217 D2: -- Tos: 18 RegAddr: 0
Executing uInst: LAB0002:60
#MIR: (Cycle←R1 W2addr←MarMem CondCode←NoFault NextInstB←PageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 26 #$Opcode 56 #NCurPc: 18
D1: Code/100663360 D2: Code/100663424 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 26 #$Opcode 56 #NCurPc: 18
D1: -- D2: Int/17 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 26 #$Opcode 56 #NCurPc: 18
D1: Code/100663360 D2: Code/100663424 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 26 #$Opcode 56 #NCurPc: 18
D1: Int/1073741823 D2: Int/5 Tos: 18 RegAddr: 0
Executing uInst: LAB0003:61
#MIR: (EUop←D1 Tag←D1 RD1addr←Mar Waddr←Tos' Tos'←Tos+1 NewTos←Tos' CondCode←Boundp Cwrite 
NextInstA←Done NextInstB←Ufn-0d)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 26 #$Opcode 56 #NCurPc: 18
D1: Int/5 D2: Code/100663424 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 26 #$Opcode 26 #NCurPc: 18
D1: Int/5 D2: -- Tos: 19 RegAddr: 0
New Opcode: 26 Length: 1 Data: Object/0 N: 68 PC: 18 OldOpLength: 1
Executing uInst: '1:26
#MIR: (Label←'1 EUop←D2 Tag←Int RD2addr←MuxRdSel MuxRdSel←K K←1 Waddr←Tos' Tos'←Tos+1 NewTos←Tos' 
NextInstA←Done)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 68 #$Opcode 26 #NCurPc: 19
D1: Int/5 D2: Object/1 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 68 #$Opcode 68 #NCurPc: 19
D1: Int/1 D2: -- Tos: 20 RegAddr: 0
New Opcode: 68 Length: 1 Data: Object/0 N: 57 PC: 19 OldOpLength: 1
Executing uInst: plus:213
#MIR: (Label←Plus EUop←+ Tag←Int Raddr←Tos RD2addr←Raddr-1 W2addr←Tmp1D1 CondCode←IntegerD1D2 
NextInstB←Ufn-2)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 57 #$Opcode 68 #NCurPc: 20
D1: Int/1 D2: Int/5 Tos: 20 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 57 #$Opcode 68 #NCurPc: 20
D1: Int/6 D2: -- Tos: 20 RegAddr: 0
Executing uInst: LAB0019:228
#MIR: (EUop←D2 Tag←Int RD2addr←Tmp1 Waddr←Tos' Tos'←Tos-1 NewTos←Tos' CondCode←NoOverflow CWrite 
NextInstA←Done NextInstB←Ufn-2)
****************** Errors ******************
D1-2: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 57 #$Opcode 68 #NCurPc: 20
D1: Int/1 D2: Int/6 Tos: 20 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 57 #$Opcode 57 #NCurPc: 20
D1: Int/6 D2: -- Tos: 19 RegAddr: 0
New Opcode: 57 Length: 0 Data: Object/0 N: 64 PC: 20 OldOpLength: 0
Executing uInst: loadibuf:209
#MIR: (Label←LoadIBuf Cycle←R4 RD1addr←PcAddr W2addr←IBufD2PcD1 EUop←+16 Tag←Int 
Misc←ResetInitialRefill CondCode←NoFault NextInstA←Done NextInstB←IBufPageFault)
****************** Errors ******************
D1-2: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010010 $Opcode: 57 #$Opcode 57 #NCurPc: 20
D1: Int/32 D2: Code/100663360 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010001 $Opcode: 57 #$Opcode 57 #NCurPc: 20
D1: Int/48 D2: XType/987200381 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 57 #$Opcode 57 #NCurPc: 20
D1: -- D2: Int/1072160763 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 57 #$Opcode 57 #NCurPc: 20
D1: -- D2: XType/1054604287 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 57 #$Opcode 57 #NCurPc: 20
D1: -- D2: XType/987200351 Tos: 19 RegAddr: 0
New Opcode: 57 Length: 4 Data: Object/2097216 N: 64 PC: 20 OldOpLength: 4
Executing uInst: gvar←:57
#MIR: (Label←GVar← EUop←+ Tag←Int RD1addr←IBufData RD2addr←MuxRdSel MuxRdSel←K K←ValueCellOffset 
W2addr←MarD1)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 144 #$Opcode 57 #NCurPc: 24
D1: Object/2097216 D2: Object/1 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 144 #$Opcode 57 #NCurPc: 24
D1: Int/2097217 D2: -- Tos: 19 RegAddr: 0
Executing uInst: refcountstore:215
#MIR: (Label←RefCountStore Cycle←R1 Waddr←K WCxt←K K←Decref CondCode←NoFault NextInstB←PageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 144 #$Opcode 57 #NCurPc: 24
D1: Int/6 D2: Code/100663360 Tos: 19 RegAddr: 0
****************** Errors ******************
D1-2: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 144 #$Opcode 57 #NCurPc: 24
D1: Int/1073741823 D2: Int/5 Tos: 19 RegAddr: 0
Executing uInst: LAB0004:62
#MIR: (Cycle←W1 Dswap Raddr←Tos CondCode←NoFault NextInstB←PageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 144 #$Opcode 57 #NCurPc: 24
D1: Code/100663360 D2: Int/6 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 144 #$Opcode 57 #NCurPc: 24
D1: -- D2: -- Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 144 #$Opcode 57 #NCurPc: 24
D1: -- D2: -- Tos: 19 RegAddr: 0
Executing uInst: pagefault:212
#MIR: (Label←PageFault EUop←D1 Tag←Int RD1addr←Mar Waddr←Tos' Tos'←Tos+1 NewTos←Tos' NewArg←K K←1 
Misc←OpLength=0 CondCode←FramesAvail Cwrite NextInstB←DumpFrame)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 144 #$Opcode 57 #NCurPc: 24
D1: Int/2097217 D2: Code/100663360 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 144 #$Opcode 57 #NCurPc: 24
D1: Int/2097217 D2: -- Tos: 20 RegAddr: 0
Executing uInst: LAB0072:146
#MIR: (EUop←D1 Tag←D1 Raddr←K K←PFCode RCxt←K W2addr←MarD1 NextInstA←Fn1)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 57 #$Opcode 57 #NCurPc: 20
D1: Code/100663424 D2: -- Tos: 20 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 57 #$Opcode 57 #NCurPc: 20
D1: Code/100663424 D2: -- Tos: 20 RegAddr: 0
Executing uInst: fn1:197
#MIR: (Label←Fn1 EUop←+4 Tag←D1 RD1addr←Mar W2addr←MarD1 NewArg2←Arg NewArg←K K←StkHdr CondCode←CCodeP
 NextInstB←Fn5)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 57 #$Opcode 57 #NCurPc: 20
D1: Code/100663424 D2: Int/6 Tos: 20 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 57 #$Opcode 57 #NCurPc: 20
D1: Code/100663428 D2: -- Tos: 20 RegAddr: 0
Executing uInst: LAB0041:115
#MIR: (Cycle←R4 WCxt←Next Waddr←Arg<6>/QW<2> EUop←+4 Tag←D1 RD1addr←Mar W2addr←MarD1 CondCode←NoFault 
NextInstB←PageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010010 $Opcode: 57 #$Opcode 57 #NCurPc: 20
D1: Code/100663428 D2: Int/6 Tos: 20 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010001 $Opcode: 57 #$Opcode 57 #NCurPc: 20
D1: Code/100663432 D2: Int/16 Tos: 20 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 57 #$Opcode 57 #NCurPc: 20
D1: -- D2: Int/0 Tos: 20 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 57 #$Opcode 57 #NCurPc: 20
D1: -- D2: Code/100663424 Tos: 20 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 57 #$Opcode 57 #NCurPc: 20
D1: -- D2: Code/100663424 Tos: 20 RegAddr: 0
Executing uInst: LAB0042:116
#MIR: (EUop←D2 Tag←D2 RD2addr←Unbound Waddr←K K←PVar WCxt←Next Misc←WriteOctal NewArg←Arg2)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 57 #$Opcode 57 #NCurPc: 20
D1: Int/2097217 D2: Ptr-32/0 Tos: 20 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 57 #$Opcode 57 #NCurPc: 20
D1: Ptr-32/0 D2: -- Tos: 20 RegAddr: 0
Executing uInst: fn2:198
#MIR: (Label←Fn2 EUop←D2 Tag←D2 RD2addr←Nil Waddr←K K←IVar WCxt←Next Misc←WriteOctal)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 57 #$Opcode 57 #NCurPc: 20
D1: Int/2097217 D2: Atm/3584 Tos: 20 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 57 #$Opcode 57 #NCurPc: 20
D1: Atm/3584 D2: -- Tos: 20 RegAddr: 0
Executing uInst: LAB0043:117
#MIR: (EUop←D2 Tag←Int RD2addr←PC Waddr←K K←Pc Misc←Oplength=0&SetInitialRefill)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 57 #$Opcode 57 #NCurPc: 20
D1: Int/2097217 D2: Int/20 Tos: 20 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 57 #$Opcode 57 #NCurPc: 20
D1: Int/20 D2: -- Tos: 20 RegAddr: 0
Executing uInst: LAB0044:118
#MIR: (EUop←+ Tag←Int RD1addr←Mar RD2addr←MuxRdSel MuxRdSel←Arg W2Addr←MarD1)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 57 #$Opcode 57 #NCurPc: 20
D1: Code/100663432 D2: Object/1 Tos: 20 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 57 #$Opcode 57 #NCurPc: 20
D1: Int/100663433 D2: -- Tos: 20 RegAddr: 0
Executing uInst: LAB0045:119
#MIR: (Cycle←R1 Waddr←K WCxt←Next K←Pc)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 57 #$Opcode 57 #NCurPc: 20
D1: Int/2097217 D2: Int/6 Tos: 20 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 57 #$Opcode 57 #NCurPc: 20
D1: Int/1073741823 D2: Int/560 Tos: 20 RegAddr: 0
Executing uInst: LAB0046:120
#MIR: (EUop←D1 Tag←Int Raddr←K RCxt←Next K←PC W2addr←PCD1)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 57 #$Opcode 57 #NCurPc: 20
D1: Int/560 D2: Int/16 Tos: 20 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 57 #$Opcode 57 #NCurPc: 20
D1: Int/560 D2: -- Tos: 20 RegAddr: 0
Executing uInst: LAB0047:121
#MIR: (EUop←D2 Tag←Int RD2addr←MuxRdSel MuxRdSel←K K←Ivar NewArg2←K W2addr←MarD1 NewArg←Arg' 
Arg'←Arg-1 CondCode←Arg#0 NextInstB←Fn3)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 0 #$Opcode 57 #NCurPc: 16
D1: Int/2097217 D2: Object/8 Tos: 20 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 0 #$Opcode 57 #NCurPc: 16
D1: Int/8 D2: -- Tos: 20 RegAddr: 0
Executing uInst: LAB0048:122
#MIR: (EUop←+ Tag←Int RD1addr←Mar RD2addr←MuxRdSel MuxRdSel←Arg W2addr←Tmp1D1)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 0 #$Opcode 57 #NCurPc: 16
D1: Int/8 D2: Object/0 Tos: 20 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 0 #$Opcode 57 #NCurPc: 16
D1: Int/8 D2: -- Tos: 20 RegAddr: 0
Executing uInst: LAB0049:123
#MIR: (RD2addr←Tmp1 NewArg←D2)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 0 #$Opcode 57 #NCurPc: 16
D1: Int/2097217 D2: Int/8 Tos: 20 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 0 #$Opcode 57 #NCurPc: 16
D1: Int/1073741823 D2: -- Tos: 20 RegAddr: 0
Executing uInst: LAB0050:124
#MIR: (EUop←D1 Tag←D1 Raddr←Tos WCxt←Next Waddr←Arg NewTos←Tos' Tos'←Tos-1 NewArg←Arg' Arg'←Arg-1 
CondCode←Arg=Arg2 NextInstB←Rpt)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 0 #$Opcode 57 #NCurPc: 16
D1: Int/2097217 D2: Int/6 Tos: 20 RegAddr: 0
****************** Errors ******************
#CONDA: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 0 #$Opcode 57 #NCurPc: 16
D1: Int/2097217 D2: -- Tos: 19 RegAddr: 0
Executing uInst: fn3:199
#MIR: (Label←Fn3 EUop←D1<24>/D2<8> Tag←D1 RD2addr←MuxRdSel MuxRdSel←Tos Raddr←K Waddr←K K←StkHdr)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 0 #$Opcode 57 #NCurPc: 16
D1: XType/1073741586 D2: Object/19 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 0 #$Opcode 57 #NCurPc: 16
D1: XType/1073741587 D2: -- Tos: 19 RegAddr: 0
Executing uInst: LAB0051:125
#MIR: (EUop←D2 Tag←D2 Dswap Raddr←K K←StkHdr RCxt←Next WCxt←Next NewTos←D2 NewTopCxt←Next 
NextInstA←Done)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 0 #$Opcode 57 #NCurPc: 16
D1: -- D2: Int/16 Tos: 19 RegAddr: 0
****************** Errors ******************
D1-31: 0 ← 1
D1-29: 0 ← 1
D1-28: 0 ← 1
D1-27: 0 ← 1
D1-26: 0 ← 1
D1-25: 0 ← 1
D1-24: 0 ← 1
D1-23: 0 ← 1
D1-22: 0 ← 1
D1-21: 0 ← 1
D1-20: 0 ← 1
D1-19: 0 ← 1
D1-18: 0 ← 1
D1-17: 0 ← 1
D1-16: 0 ← 1
D1-15: 0 ← 1
D1-14: 0 ← 1
D1-13: 0 ← 1
D1-12: 0 ← 1
D1-11: 0 ← 1
D1-10: 0 ← 1
D1-9: 0 ← 1
D1-8: 0 ← 1
D1-7: 0 ← 1
D1-6: 0 ← 1
D1-5: 0 ← 1
D1-3: 0 ← 1
D1-2: 0 ← 1
D1-1: 0 ← 1
D1-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 0 #$Opcode 0 #NCurPc: 16
D1: Int/16 D2: -- Tos: 16 RegAddr: 0
New Opcode: 0 Length: 0 Data: Object/0 N: 32 PC: 16 OldOpLength: 0
Executing uInst: loadibuf:209
#MIR: (Label←LoadIBuf Cycle←R4 RD1addr←PcAddr W2addr←IBufD2PcD1 EUop←+16 Tag←Int 
Misc←ResetInitialRefill CondCode←NoFault NextInstA←Done NextInstB←IBufPageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010010 $Opcode: 0 #$Opcode 0 #NCurPc: 16
D1: Int/560 D2: Atm/3584 Tos: 16 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010001 $Opcode: 0 #$Opcode 0 #NCurPc: 16
D1: Int/576 D2: List/80235720 Tos: 16 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 0 #$Opcode 0 #NCurPc: 16
D1: -- D2: Int/862283366 Tos: 16 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 200 #$Opcode 0 #NCurPc: 16
D1: -- D2: XType/1069448763 Tos: 16 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 200 #$Opcode 200 #NCurPc: 16
D1: -- D2: XType/526176237 Tos: 16 RegAddr: 0
New Opcode: 200 Length: 1 Data: Object/0 N: 145 PC: 16 OldOpLength: 1
Executing uInst: vark:233
#MIR: (Label←Vark EUop←D1 Tag←D1 Raddr←0<4>/OpCode<4> Waddr←Tos' Tos'←Tos+1 NewTos←Tos' NextInstA←Done
)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 145 #$Opcode 200 #NCurPc: 17
D1: Int/2097217 D2: -- Tos: 16 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 145 #$Opcode 145 #NCurPc: 17
D1: Int/2097217 D2: -- Tos: 17 RegAddr: 0
New Opcode: 145 Length: 5 Data: Int/16777215 N: 255 PC: 17 OldOpLength: 5
Executing uInst: intconst:81
#MIR: (Label←IntConst EUop←D1 Tag←Int RD1addr←IBufData Waddr←TOS' TOS'←TOS+1 NewTos←Tos' 
NextInstA←Done)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 16 #$Opcode 145 #NCurPc: 22
D1: Int/16777215 D2: Ptr-32/0 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 16 #$Opcode 16 #NCurPc: 22
D1: Int/16777215 D2: -- Tos: 18 RegAddr: 0
New Opcode: 16 Length: 0 Data: Object/0 N: 47 PC: 22 OldOpLength: 0
Executing uInst: loadibuf:209
#MIR: (Label←LoadIBuf Cycle←R4 RD1addr←PcAddr W2addr←IBufD2PcD1 EUop←+16 Tag←Int 
Misc←ResetInitialRefill CondCode←NoFault NextInstA←Done NextInstB←IBufPageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010010 $Opcode: 16 #$Opcode 16 #NCurPc: 22
D1: Int/576 D2: Int/2097217 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010001 $Opcode: 16 #$Opcode 16 #NCurPc: 22
D1: Int/592 D2: XType/1071816350 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 16 #$Opcode 16 #NCurPc: 22
D1: -- D2: Float/1073477457 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 16 #$Opcode 16 #NCurPc: 22
D1: -- D2: XType/1004404446 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 16 #$Opcode 16 #NCurPc: 22
D1: -- D2: Int/1073217523 Tos: 18 RegAddr: 0
New Opcode: 16 Length: 1 Data: Object/0 N: 47 PC: 22 OldOpLength: 1
Executing uInst: and:16
#MIR: (Label←And EUop←And Tag←Int Raddr←Tos RD2addr←Raddr-1 Waddr←Tos' Tos'←Tos-1 NewTos←Tos' 
CondCode←IntegerD1D2 CWrite NextInstA←Done NextInstB←Ufn-2)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 47 #$Opcode 16 #NCurPc: 23
D1: Int/16777215 D2: Int/2097217 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 47 #$Opcode 47 #NCurPc: 23
D1: Int/2097217 D2: -- Tos: 17 RegAddr: 0
New Opcode: 47 Length: 2 Data: Object/10 N: 10 PC: 23 OldOpLength: 2
Executing uInst: lrsh.n:228
#MIR: (Label←Lrsh.N EUop←D1 Tag←Int Raddr←Tos W2addr←MarD1 NewArg←IBufN CondCode←Integerp 
NextInstB←Ufn-1d)
****************** Errors ******************
D1-23: 1 ← 0
D1-22: 1 ← 0
D1-20: 1 ← 0
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/2097217 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-23: 1 ← 0
D1-22: 1 ← 0
D1-20: 1 ← 0
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/2097217 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0031:105
#MIR: (Arg'←Arg-1 NewArg←Arg' CondCode←Arg=0 NextInstA←Done)
****************** Errors ******************
D1-23: 1 ← 0
D1-22: 1 ← 0
D1-20: 1 ← 0
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/2097217 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-23: 1 ← 0
D1-22: 1 ← 0
D1-20: 1 ← 0
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/1073741823 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/2097217 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-23: 1 ← 0
D1-22: 1 ← 0
D1-20: 1 ← 0
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/1048608 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-22: 1 ← 0
D1-21: 1 ← 0
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/1048608 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-22: 1 ← 0
D1-21: 1 ← 0
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/524304 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-21: 1 ← 0
D1-20: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/524304 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-21: 1 ← 0
D1-20: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/262152 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-20: 1 ← 0
D1-19: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/262152 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-20: 1 ← 0
D1-19: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/131076 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/131076 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/65538 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/65538 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/32769 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/32769 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/16384 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/16384 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/8192 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/8192 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/4096 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/4096 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 35 #NCurPc: 25
D1: Int/2048 D2: -- Tos: 17 RegAddr: 0
New Opcode: 35 Length: 2 Data: Object/0 N: 0 PC: 25 OldOpLength: 2
Executing uInst: settype:35
#MIR: (Label←SetType EUop←D2<2>Shl24/D1<30> Tag←D2<8:7> Raddr←Tos RD2addr←MuxRdSel MuxRdSel←IBufN 
Waddr←Tos NextInstA←Done)
****************** Errors ******************
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 20 #$Opcode 35 #NCurPc: 27
D1: Int/2048 D2: Object/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 20 #$Opcode 20 #NCurPc: 27
D1: Object/2048 D2: -- Tos: 17 RegAddr: 0
New Opcode: 20 Length: 1 Data: Object/0 N: 32 PC: 27 OldOpLength: 1
Executing uInst: copy:20
#MIR: (Label←Copy EUop←D1 Tag←D1 Raddr←Tos Waddr←Tos' Tos'←Tos+1 NewTos←Tos' NextInstA←Done)
****************** Errors ******************
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 32 #$Opcode 20 #NCurPc: 28
D1: Object/2048 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 32 #$Opcode 32 #NCurPc: 28
D1: Object/2048 D2: -- Tos: 18 RegAddr: 0
New Opcode: 32 Length: 2 Data: Object/0 N: 0 PC: 28 OldOpLength: 2
Executing uInst: getptr:32
#MIR: (Label←Getptr EUop←+ Tag←D2 Dswap Raddr←Tos RD1addr←IBufData W2addr←MarD1 Condcode←PointerpD2 
NextInstB←Ufn-1d)
****************** Errors ******************
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 185 #$Opcode 32 #NCurPc: 30
D1: Object/0 D2: Object/2048 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 185 #$Opcode 32 #NCurPc: 30
D1: Object/2048 D2: -- Tos: 18 RegAddr: 0
Executing uInst: LAB0033:65
#MIR: (Cycle←R1 Waddr←Tos CondCode←NoFault Cwrite NextInstA←Done NextInstB←PageFault)
****************** Errors ******************
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-6: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
VAD'-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 185 #$Opcode 32 #NCurPc: 30
D1: Object/2048 D2: Object/2048 Tos: 18 RegAddr: 0
****************** Errors ******************
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-6: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
VAD'-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 185 #$Opcode 185 #NCurPc: 30
D1: Int/1073741823 D2: Int/17 Tos: 18 RegAddr: 0
New Opcode: 185 Length: 1 Data: Object/0 N: 26 PC: 30 OldOpLength: 1
Executing uInst: vark←:234
#MIR: (Label←Vark← EUop←D1 Tag←D1 Raddr←Tos Waddr←0<4>/OpCode<4> NextInstA←Done)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 26 #$Opcode 185 #NCurPc: 31
D1: Int/17 D2: Object/2048 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 26 #$Opcode 26 #NCurPc: 31
D1: Int/17 D2: -- Tos: 18 RegAddr: 0
New Opcode: 26 Length: 1 Data: Object/0 N: 16 PC: 31 OldOpLength: 1
Executing uInst: '1:26
#MIR: (Label←'1 EUop←D2 Tag←Int RD2addr←MuxRdSel MuxRdSel←K K←1 Waddr←Tos' Tos'←Tos+1 NewTos←Tos' 
NextInstA←Done)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 16 #$Opcode 26 #NCurPc: 0
D1: Int/17 D2: Object/1 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 16 #$Opcode 16 #NCurPc: 0
D1: Int/1 D2: -- Tos: 19 RegAddr: 0
New Opcode: 16 Length: 1 Data: Object/0 N: 26 PC: 0 OldOpLength: 1
Executing uInst: and:16
#MIR: (Label←And EUop←And Tag←Int Raddr←Tos RD2addr←Raddr-1 Waddr←Tos' Tos'←Tos-1 NewTos←Tos' 
CondCode←IntegerD1D2 CWrite NextInstA←Done NextInstB←Ufn-2)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 26 #$Opcode 16 #NCurPc: 1
D1: Int/1 D2: Int/17 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 26 #$Opcode 26 #NCurPc: 1
D1: Int/1 D2: -- Tos: 18 RegAddr: 0
New Opcode: 26 Length: 1 Data: Object/0 N: 10 PC: 1 OldOpLength: 1
Executing uInst: '1:228
#MIR: (Label←'1 EUop←D2 Tag←Int RD2addr←MuxRdSel MuxRdSel←K K←1 Waddr←Tos' Tos'←Tos+1 NewTos←Tos' 
NextInstA←Done)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 10 #$Opcode 26 #NCurPc: 2
D1: Int/1 D2: Object/1 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 10 #$Opcode 10 #NCurPc: 2
D1: Int/1 D2: -- Tos: 19 RegAddr: 0
New Opcode: 10 Length: 1 Data: Object/0 N: 53 PC: 2 OldOpLength: 1
Executing uInst: eq:10
#MIR: (Label←Eq Raddr←Tos RD2addr←Raddr-1 Tos'←Tos-1 NewTos←Tos' CondCode←D1=D2 NextInstA←SetT 
NextInstB←SetNil)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 53 #$Opcode 10 #NCurPc: 3
D1: Int/1 D2: Int/1 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 53 #$Opcode 10 #NCurPc: 3
D1: Int/1073741823 D2: -- Tos: 18 RegAddr: 0
Executing uInst: sett:222
#MIR: (Label←SetT EUop←D2 Tag←D2 RD2addr←T Waddr←Tos NextInstA←Done)
****************** Errors ******************
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-6: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
VAD'-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 53 #$Opcode 10 #NCurPc: 3
D1: Int/1 D2: Atm/3600 Tos: 18 RegAddr: 0
****************** Errors ******************
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-6: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
VAD'-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 53 #$Opcode 53 #NCurPc: 3
D1: Atm/3600 D2: -- Tos: 18 RegAddr: 0
New Opcode: 53 Length: 2 Data: Object/7 N: 7 PC: 3 OldOpLength: 2
Executing uInst: fjump:53
#MIR: (Label←FJump EUop←nop Raddr←Tos Tos'←Tos-1 NewTos←Tos' Rd2addr←Nil Condcode←D1#D2 NextInstA←Done
 NextInstB←DoJmp)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 145 #$Opcode 53 #NCurPc: 5
D1: Atm/3600 D2: Atm/3584 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 145 #$Opcode 145 #NCurPc: 5
D1: Int/1073741823 D2: -- Tos: 17 RegAddr: 0
New Opcode: 145 Length: 0 Data: Object/0 N: 3 PC: 5 OldOpLength: 0
Executing uInst: loadibuf:209
#MIR: (Label←LoadIBuf Cycle←R4 RD1addr←PcAddr W2addr←IBufD2PcD1 EUop←+16 Tag←Int 
Misc←ResetInitialRefill CondCode←NoFault NextInstA←Done NextInstB←IBufPageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010010 $Opcode: 145 #$Opcode 145 #NCurPc: 5
D1: Int/592 D2: Ptr-32/0 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010001 $Opcode: 145 #$Opcode 145 #NCurPc: 5
D1: Int/608 D2: Float/871219192 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 145 #$Opcode 145 #NCurPc: 5
D1: -- D2: XType/747145454 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 145 #$Opcode 145 #NCurPc: 5
D1: -- D2: Object/0 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 145 #$Opcode 145 #NCurPc: 5
D1: -- D2: Object/0 Tos: 17 RegAddr: 0
New Opcode: 145 Length: 5 Data: Int/3 N: 3 PC: 5 OldOpLength: 5
Executing uInst: intconst:81
#MIR: (Label←IntConst EUop←D1 Tag←Int RD1addr←IBufData Waddr←TOS' TOS'←TOS+1 NewTos←Tos' 
NextInstA←Done)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 50 #$Opcode 145 #NCurPc: 10
D1: Int/3 D2: Ptr-32/0 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 50 #$Opcode 50 #NCurPc: 10
D1: Int/3 D2: -- Tos: 18 RegAddr: 0
New Opcode: 50 Length: 2 Data: Object/5 N: 5 PC: 10 OldOpLength: 2
Executing uInst: dojmp:50
#MIR: (Label←DoJmp EUop←+ Tag←Int RD2addr←PC RD1addr←IBufData W2addr←PCD1 
Misc←Oplength=0&SetInitialRefill NextInstA←Dojmp1)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 145 #$Opcode 50 #NCurPc: 12
D1: Object/5 D2: Int/588 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 145 #$Opcode 50 #NCurPc: 12
D1: Int/593 D2: -- Tos: 18 RegAddr: 0
Executing uInst: dojmp1:193
#MIR: (Label←DoJmp1 NextInstA←Done)
****************** Errors ******************
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-6: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
VAD'-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 201 #$Opcode 50 #NCurPc: 17
D1: Int/3 D2: Object/2048 Tos: 18 RegAddr: 0
****************** Errors ******************
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-6: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
VAD'-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 201 #$Opcode 201 #NCurPc: 17
D1: Int/1073741823 D2: -- Tos: 18 RegAddr: 0
New Opcode: 201 Length: 0 Data: Object/0 N: 17 PC: 17 OldOpLength: 0
Executing uInst: loadibuf:209
#MIR: (Label←LoadIBuf Cycle←R4 RD1addr←PcAddr W2addr←IBufD2PcD1 EUop←+16 Tag←Int 
Misc←ResetInitialRefill CondCode←NoFault NextInstA←Done NextInstB←IBufPageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010010 $Opcode: 201 #$Opcode 201 #NCurPc: 17
D1: Int/592 D2: Object/2048 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010001 $Opcode: 201 #$Opcode 201 #NCurPc: 17
D1: Int/608 D2: Float/871219192 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 201 #$Opcode 201 #NCurPc: 17
D1: -- D2: XType/747145454 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 201 #$Opcode 201 #NCurPc: 17
D1: -- D2: Object/0 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 201 #$Opcode 201 #NCurPc: 17
D1: -- D2: Object/0 Tos: 18 RegAddr: 0
New Opcode: 201 Length: 1 Data: Object/0 N: 17 PC: 17 OldOpLength: 1
Executing uInst: vark:233
#MIR: (Label←Vark EUop←D1 Tag←D1 Raddr←0<4>/OpCode<4> Waddr←Tos' Tos'←Tos+1 NewTos←Tos' NextInstA←Done
)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 17 #$Opcode 201 #NCurPc: 18
D1: Int/17 D2: Int/2097217 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 17 #$Opcode 17 #NCurPc: 18
D1: Int/17 D2: -- Tos: 19 RegAddr: 0
New Opcode: 17 Length: 1 Data: Object/0 N: 33 PC: 18 OldOpLength: 1
Executing uInst: or:17
#MIR: (Label←Or EUop←Or Tag←Int Raddr←Tos RD2addr←Raddr-1 Waddr←Tos' Tos'←Tos-1 NewTos←Tos' 
CondCode←IntegerD1D2 CWrite NextInstA←Done NextInstB←Ufn-2)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 33 #$Opcode 17 #NCurPc: 19
D1: Int/17 D2: Int/3 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 33 #$Opcode 33 #NCurPc: 19
D1: Int/19 D2: -- Tos: 18 RegAddr: 0
New Opcode: 33 Length: 2 Data: Object/0 N: 0 PC: 19 OldOpLength: 2
Executing uInst: putptr:228
#MIR: (Label←Putptr EUop←D2 Tag←D2 Raddr←Tos RD2addr←Raddr-1 W2addr←MarD1 Condcode←PointerpD2 
NextInstB←Ufn-2d)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 60 #$Opcode 33 #NCurPc: 21
D1: Int/19 D2: Object/2048 Tos: 18 RegAddr: 0
****************** Errors ******************
#CONDA: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 60 #$Opcode 33 #NCurPc: 21
D1: Object/2048 D2: -- Tos: 18 RegAddr: 0
Executing uInst: LAB0034:229
#MIR: (EUop←+ Tag←D1 RD1addr←Mar RD2addr←MuxRdSel MuxRdSel←IBufN W2addr←MarD1)
****************** Errors ******************
D1-30: 1 ← 0
D1-11: 0 ← 1
D1-4: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-11: 0 ← 1
VAD'-11: 1 ← 0
VAD'-4: 0 ← 1
VAD'-1: 0 ← 1
VAD'-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 60 #$Opcode 33 #NCurPc: 21
D1: Object/2048 D2: Object/0 Tos: 18 RegAddr: 0
****************** Errors ******************
D1-30: 1 ← 0
D1-11: 0 ← 1
D1-4: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-11: 0 ← 1
VAD'-11: 1 ← 0
VAD'-4: 0 ← 1
VAD'-1: 0 ← 1
VAD'-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 60 #$Opcode 33 #NCurPc: 21
D1: Object/2048 D2: -- Tos: 18 RegAddr: 0
Executing uInst: LAB0035:109
#MIR: (Cycle←W1 Dswap Raddr←Tos Tos'←Tos-1 NewTos←Tos' CondCode←NoFault CWrite NextInstA←Done 
NextInstB←PageFault)
****************** Errors ******************
D1-30: 1 ← 0
D1-11: 0 ← 1
D1-4: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-11: 0 ← 1
VAD'-11: 1 ← 0
VAD'-4: 0 ← 1
VAD'-1: 0 ← 1
VAD'-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 60 #$Opcode 33 #NCurPc: 21
D1: Object/2048 D2: Int/19 Tos: 18 RegAddr: 0
****************** Errors ******************
D1-30: 1 ← 0
D1-11: 0 ← 1
D1-4: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-11: 0 ← 1
VAD'-11: 1 ← 0
VAD'-4: 0 ← 1
VAD'-1: 0 ← 1
VAD'-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 60 #$Opcode 60 #NCurPc: 21
D1: Int/1073741823 D2: -- Tos: 17 RegAddr: 0
New Opcode: 60 Length: 0 Data: Object/0 N: 124 PC: 21 OldOpLength: 0
Executing uInst: loadibuf:209
#MIR: (Label←LoadIBuf Cycle←R4 RD1addr←PcAddr W2addr←IBufD2PcD1 EUop←+16 Tag←Int 
Misc←ResetInitialRefill CondCode←NoFault NextInstA←Done NextInstB←IBufPageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010010 $Opcode: 60 #$Opcode 60 #NCurPc: 21
D1: Int/608 D2: Ptr-32/0 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010001 $Opcode: 60 #$Opcode 60 #NCurPc: 21
D1: Int/624 D2: Object/0 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 60 #$Opcode 60 #NCurPc: 21
D1: -- D2: Object/0 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 60 #$Opcode 60 #NCurPc: 21
D1: -- D2: Object/0 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 60 #$Opcode 60 #NCurPc: 21
D1: -- D2: Object/0 Tos: 17 RegAddr: 0
New Opcode: 60 Length: 1 Data: Object/0 N: 124 PC: 21 OldOpLength: 1
Executing uInst: reset-vmm:219
#MIR: (Label←Reset-Vmm Misc←Reset-Vmm NextInstA←Done)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 124 #$Opcode 60 #NCurPc: 22
D1: Object/2048 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-30: 1 ← 0
D1-11: 0 ← 1
D1-4: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 124 #$Opcode 124 #NCurPc: 22
D1: Int/1073741823 D2: -- Tos: 17 RegAddr: 0
New Opcode: 124 Length: 1 Data: Object/0 N: 255 PC: 22 OldOpLength: 1
Executing uInst: retnp:220
#MIR: (Label←Retnp EUop←D1 Tag←Int Raddr←K K←StkHdr CondCode←TrapOnExit NextInstA←Ufn-0)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 255 #$Opcode 124 #NCurPc: 23
D1: Int/16 D2: -- Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 255 #$Opcode 124 #NCurPc: 23
D1: Int/16 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0065:139
#MIR: (EUop←D1 Tag←Int RCxt←Prev Raddr←K K←Pc W2Addr←PcD1 NewTopCxt←Prev 
Misc←Oplength=0&SetInitialRefill)
****************** Errors ******************
VAD-11: 0 ← 1
VAD'-11: 1 ← 0
VAD'-4: 0 ← 1
VAD'-1: 0 ← 1
VAD'-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 255 #$Opcode 124 #NCurPc: 23
D1: Int/20 D2: XType/1073741587 Tos: 17 RegAddr: 0
****************** Errors ******************
VAD-11: 0 ← 1
VAD'-11: 1 ← 0
VAD'-4: 0 ← 1
VAD'-1: 0 ← 1
VAD'-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 255 #$Opcode 124 #NCurPc: 23
D1: Int/20 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0066:140
#MIR: (Dswap Raddr←K K←StkHdr NewTos←D2 NextInstA←Done)
****************** Errors ******************
VAD-11: 0 ← 1
VAD'-11: 1 ← 0
VAD'-4: 0 ← 1
VAD'-1: 0 ← 1
VAD'-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 0 #$Opcode 124 #NCurPc: 20
D1: Int/20 D2: XType/1073741587 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-31: 1 ← 0
D1-29: 1 ← 0
D1-28: 1 ← 0
D1-27: 1 ← 0
D1-26: 1 ← 0
D1-25: 1 ← 0
D1-24: 1 ← 0
D1-23: 1 ← 0
D1-22: 1 ← 0
D1-21: 1 ← 0
D1-20: 1 ← 0
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-3: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-11: 0 ← 1
VAD'-11: 1 ← 0
VAD'-4: 0 ← 1
VAD'-1: 0 ← 1
VAD'-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 0 #$Opcode 0 #NCurPc: 20
D1: Int/1073741823 D2: -- Tos: 19 RegAddr: 0
New Opcode: 0 Length: 0 Data: Object/0 N: 60 PC: 20 OldOpLength: 0
Executing uInst: loadibuf:209
#MIR: (Label←LoadIBuf Cycle←R4 RD1addr←PcAddr W2addr←IBufD2PcD1 EUop←+16 Tag←Int 
Misc←ResetInitialRefill CondCode←NoFault NextInstA←Done NextInstB←IBufPageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010010 $Opcode: 0 #$Opcode 0 #NCurPc: 20
D1: Int/16 D2: Code/100663360 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010001 $Opcode: 0 #$Opcode 0 #NCurPc: 20
D1: Int/32 D2: XType/1052630751 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 0 #$Opcode 0 #NCurPc: 20
D1: -- D2: XType/996638711 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 57 #$Opcode 0 #NCurPc: 20
D1: -- D2: Int/1072168443 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 57 #$Opcode 57 #NCurPc: 20
D1: -- D2: XType/1054604287 Tos: 19 RegAddr: 0
New Opcode: 57 Length: 0 Data: Object/0 N: 64 PC: 20 OldOpLength: 0
Executing uInst: loadibuf:209
#MIR: (Label←LoadIBuf Cycle←R4 RD1addr←PcAddr W2addr←IBufD2PcD1 EUop←+16 Tag←Int 
Misc←ResetInitialRefill CondCode←NoFault NextInstA←Done NextInstB←IBufPageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010010 $Opcode: 57 #$Opcode 57 #NCurPc: 20
D1: Int/32 D2: Code/100663360 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010001 $Opcode: 57 #$Opcode 57 #NCurPc: 20
D1: Int/48 D2: XType/987200381 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 57 #$Opcode 57 #NCurPc: 20
D1: -- D2: Int/1072160763 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 57 #$Opcode 57 #NCurPc: 20
D1: -- D2: XType/1054604287 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 57 #$Opcode 57 #NCurPc: 20
D1: -- D2: XType/987200351 Tos: 19 RegAddr: 0
New Opcode: 57 Length: 4 Data: Object/2097216 N: 64 PC: 20 OldOpLength: 4
Executing uInst: gvar←:57
#MIR: (Label←GVar← EUop←+ Tag←Int RD1addr←IBufData RD2addr←MuxRdSel MuxRdSel←K K←ValueCellOffset 
W2addr←MarD1)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 144 #$Opcode 57 #NCurPc: 24
D1: Object/2097216 D2: Object/1 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 144 #$Opcode 57 #NCurPc: 24
D1: Int/2097217 D2: -- Tos: 19 RegAddr: 0
Executing uInst: refcountstore:215
#MIR: (Label←RefCountStore Cycle←R1 Waddr←K WCxt←K K←Decref CondCode←NoFault NextInstB←PageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 144 #$Opcode 57 #NCurPc: 24
D1: Int/6 D2: Code/100663360 Tos: 19 RegAddr: 0
****************** Errors ******************
D1-21: 1 ← 0
D1-6: 1 ← 0
D1-2: 0 ← 1
D1-1: 0 ← 1
D1-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 144 #$Opcode 57 #NCurPc: 24
D1: -- D2: Int/19 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 144 #$Opcode 57 #NCurPc: 24
D1: Int/6 D2: Code/100663360 Tos: 19 RegAddr: 0
****************** Errors ******************
D1-21: 1 ← 0
D1-6: 1 ← 0
D1-2: 0 ← 1
D1-1: 0 ← 1
D1-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 144 #$Opcode 57 #NCurPc: 24
D1: Int/1073741823 D2: Int/5 Tos: 19 RegAddr: 0
Executing uInst: LAB0004:62
#MIR: (Cycle←W1 Dswap Raddr←Tos CondCode←NoFault NextInstB←PageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 144 #$Opcode 57 #NCurPc: 24
D1: Code/100663360 D2: Int/6 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 144 #$Opcode 57 #NCurPc: 24
D1: Int/1073741823 D2: -- Tos: 19 RegAddr: 0
Executing uInst: LAB0005:63
#MIR: (EUop←D1 Tag←D1 Raddr←Tos Waddr←K WCxt←K K←Incref Misc←SetRefCount NextInstA←DoJmp1)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 144 #$Opcode 57 #NCurPc: 24
D1: Int/6 D2: Code/100663360 Tos: 19 RegAddr: 0
****************** Errors ******************
D1-21: 1 ← 0
D1-6: 1 ← 0
D1-2: 0 ← 1
D1-1: 0 ← 1
D1-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 144 #$Opcode 57 #NCurPc: 24
D1: Int/6 D2: -- Tos: 19 RegAddr: 0
Executing uInst: dojmp1:193
#MIR: (Label←DoJmp1 NextInstA←Done)
****************** Errors ******************
D1-21: 1 ← 0
D1-6: 1 ← 0
D1-2: 0 ← 1
D1-1: 0 ← 1
D1-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 144 #$Opcode 57 #NCurPc: 24
D1: Int/6 D2: Code/100663360 Tos: 19 RegAddr: 0
****************** Errors ******************
D1-21: 1 ← 0
D1-6: 1 ← 0
D1-2: 0 ← 1
D1-1: 0 ← 1
D1-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 144 #$Opcode 144 #NCurPc: 24
D1: Int/1073741823 D2: -- Tos: 19 RegAddr: 0
New Opcode: 144 Length: 0 Data: Object/0 N: 1 PC: 24 OldOpLength: 0
Executing uInst: refcount:214
#MIR: (Label←RefCount EUop←D1 Tag←D1 Raddr←K K←RefCountCode RCxt←K W2addr←MarD1)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 144 #$Opcode 144 #NCurPc: 24
D1: Code/100663360 D2: Int/6 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 144 #$Opcode 144 #NCurPc: 24
D1: Code/100663360 D2: -- Tos: 19 RegAddr: 0
Executing uInst: LAB0088:162
#MIR: (EUop←D1 Tag←D1 Raddr←K RCxt←K K←Decref Waddr←Tos' Tos'←Tos+1 NewTos←Tos')
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 144 #$Opcode 144 #NCurPc: 24
D1: Int/5 D2: Int/0 Tos: 19 RegAddr: 0
****************** Errors ******************
D1-21: 1 ← 0
D1-6: 1 ← 0
D1-2: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 144 #$Opcode 144 #NCurPc: 24
D1: Int/5 D2: -- Tos: 20 RegAddr: 0
Executing uInst: LAB0089:163
#MIR: (EUop←D1 Tag←D1 Raddr←K RCxt←K K←Incref Waddr←Tos' Tos'←Tos+1 NewTos←Tos')
****************** Errors ******************
D1-21: 1 ← 0
D1-6: 1 ← 0
D1-2: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 144 #$Opcode 144 #NCurPc: 24
D1: Int/6 D2: Int/5 Tos: 20 RegAddr: 0
****************** Errors ******************
D1-21: 1 ← 0
D1-6: 1 ← 0
D1-2: 0 ← 1
D1-1: 0 ← 1
D1-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 144 #$Opcode 144 #NCurPc: 24
D1: Int/6 D2: -- Tos: 21 RegAddr: 0
Executing uInst: LAB0090:164
#MIR: (Misc←ResetRefcount NewArg←K K←2 NextInstA←Fn1)
****************** Errors ******************
D1-21: 1 ← 0
D1-6: 1 ← 0
D1-2: 0 ← 1
D1-1: 0 ← 1
D1-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 144 #$Opcode 144 #NCurPc: 24
D1: Int/6 D2: Int/5 Tos: 21 RegAddr: 0
****************** Errors ******************
D1-21: 1 ← 0
D1-6: 1 ← 0
D1-2: 0 ← 1
D1-1: 0 ← 1
D1-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 144 #$Opcode 144 #NCurPc: 24
D1: Int/1073741823 D2: -- Tos: 21 RegAddr: 0
Executing uInst: fn1:197
#MIR: (Label←Fn1 EUop←+4 Tag←D1 RD1addr←Mar W2addr←MarD1 NewArg2←Arg NewArg←K K←StkHdr CondCode←CCodeP
 NextInstB←Fn5)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 144 #$Opcode 144 #NCurPc: 24
D1: Code/100663360 D2: Int/5 Tos: 21 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 144 #$Opcode 144 #NCurPc: 24
D1: Code/100663364 D2: -- Tos: 21 RegAddr: 0
Executing uInst: LAB0041:115
#MIR: (Cycle←R4 WCxt←Next Waddr←Arg<6>/QW<2> EUop←+4 Tag←D1 RD1addr←Mar W2addr←MarD1 CondCode←NoFault 
NextInstB←PageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010010 $Opcode: 144 #$Opcode 144 #NCurPc: 24
D1: Code/100663364 D2: Int/5 Tos: 21 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010001 $Opcode: 144 #$Opcode 144 #NCurPc: 24
D1: Code/100663368 D2: Int/16 Tos: 21 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 144 #$Opcode 144 #NCurPc: 24
D1: -- D2: Int/0 Tos: 21 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 144 #$Opcode 144 #NCurPc: 24
D1: -- D2: Code/100663360 Tos: 21 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 144 #$Opcode 144 #NCurPc: 24
D1: -- D2: Code/100663360 Tos: 21 RegAddr: 0
Executing uInst: LAB0042:116
#MIR: (EUop←D2 Tag←D2 RD2addr←Unbound Waddr←K K←PVar WCxt←Next Misc←WriteOctal NewArg←Arg2)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 144 #$Opcode 144 #NCurPc: 24
D1: Int/6 D2: Ptr-32/0 Tos: 21 RegAddr: 0
****************** Errors ******************
D1-21: 1 ← 0
D1-6: 1 ← 0
D1-2: 0 ← 1
D1-1: 0 ← 1
D1-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 144 #$Opcode 144 #NCurPc: 24
D1: Ptr-32/0 D2: -- Tos: 21 RegAddr: 0
Executing uInst: fn2:198
#MIR: (Label←Fn2 EUop←D2 Tag←D2 RD2addr←Nil Waddr←K K←IVar WCxt←Next Misc←WriteOctal)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 144 #$Opcode 144 #NCurPc: 24
D1: Int/6 D2: Atm/3584 Tos: 21 RegAddr: 0
****************** Errors ******************
D1-21: 1 ← 0
D1-6: 1 ← 0
D1-2: 0 ← 1
D1-1: 0 ← 1
D1-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 144 #$Opcode 144 #NCurPc: 24
D1: Atm/3584 D2: -- Tos: 21 RegAddr: 0
Executing uInst: LAB0043:117
#MIR: (EUop←D2 Tag←Int RD2addr←PC Waddr←K K←Pc Misc←Oplength=0&SetInitialRefill)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 144 #$Opcode 144 #NCurPc: 24
D1: Int/6 D2: Int/24 Tos: 21 RegAddr: 0
****************** Errors ******************
D1-21: 1 ← 0
D1-6: 1 ← 0
D1-2: 0 ← 1
D1-1: 0 ← 1
D1-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 144 #$Opcode 144 #NCurPc: 24
D1: Int/24 D2: -- Tos: 21 RegAddr: 0
Executing uInst: LAB0044:118
#MIR: (EUop←+ Tag←Int RD1addr←Mar RD2addr←MuxRdSel MuxRdSel←Arg W2Addr←MarD1)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 144 #$Opcode 144 #NCurPc: 24
D1: Code/100663368 D2: Object/2 Tos: 21 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 144 #$Opcode 144 #NCurPc: 24
D1: Int/100663370 D2: -- Tos: 21 RegAddr: 0
Executing uInst: LAB0045:119
#MIR: (Cycle←R1 Waddr←K WCxt←Next K←Pc)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 144 #$Opcode 144 #NCurPc: 24
D1: Int/6 D2: Int/5 Tos: 21 RegAddr: 0
****************** Errors ******************
D1-21: 1 ← 0
D1-6: 1 ← 0
D1-2: 0 ← 1
D1-1: 0 ← 1
D1-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 144 #$Opcode 144 #NCurPc: 24
D1: Int/1073741823 D2: Int/304 Tos: 21 RegAddr: 0
Executing uInst: LAB0046:120
#MIR: (EUop←D1 Tag←Int Raddr←K RCxt←Next K←PC W2addr←PCD1)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 144 #$Opcode 144 #NCurPc: 24
D1: Int/304 D2: Int/16 Tos: 21 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 144 #$Opcode 144 #NCurPc: 24
D1: Int/304 D2: -- Tos: 21 RegAddr: 0
Executing uInst: LAB0047:121
#MIR: (EUop←D2 Tag←Int RD2addr←MuxRdSel MuxRdSel←K K←Ivar NewArg2←K W2addr←MarD1 NewArg←Arg' 
Arg'←Arg-1 CondCode←Arg#0 NextInstB←Fn3)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 0 #$Opcode 144 #NCurPc: 16
D1: Int/6 D2: Object/8 Tos: 21 RegAddr: 0
****************** Errors ******************
D1-21: 1 ← 0
D1-6: 1 ← 0
D1-2: 0 ← 1
D1-1: 0 ← 1
D1-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 0 #$Opcode 144 #NCurPc: 16
D1: Int/8 D2: -- Tos: 21 RegAddr: 0
Executing uInst: LAB0048:122
#MIR: (EUop←+ Tag←Int RD1addr←Mar RD2addr←MuxRdSel MuxRdSel←Arg W2addr←Tmp1D1)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 0 #$Opcode 144 #NCurPc: 16
D1: Int/8 D2: Object/1 Tos: 21 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 0 #$Opcode 144 #NCurPc: 16
D1: Int/9 D2: -- Tos: 21 RegAddr: 0
Executing uInst: LAB0049:123
#MIR: (RD2addr←Tmp1 NewArg←D2)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 0 #$Opcode 144 #NCurPc: 16
D1: Int/6 D2: Int/9 Tos: 21 RegAddr: 0
****************** Errors ******************
D1-21: 1 ← 0
D1-6: 1 ← 0
D1-2: 0 ← 1
D1-1: 0 ← 1
D1-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 0 #$Opcode 144 #NCurPc: 16
D1: Int/1073741823 D2: -- Tos: 21 RegAddr: 0
Executing uInst: LAB0050:124
#MIR: (EUop←D1 Tag←D1 Raddr←Tos WCxt←Next Waddr←Arg NewTos←Tos' Tos'←Tos-1 NewArg←Arg' Arg'←Arg-1 
CondCode←Arg=Arg2 NextInstB←Rpt)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 0 #$Opcode 144 #NCurPc: 16
D1: Int/6 D2: Int/5 Tos: 21 RegAddr: 0
****************** Errors ******************
D1-21: 1 ← 0
D1-6: 1 ← 0
D1-2: 0 ← 1
D1-1: 0 ← 1
D1-0: 1 ← 0
****************** Errors ******************
#CONDA: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 0 #$Opcode 144 #NCurPc: 16
D1: Int/6 D2: -- Tos: 20 RegAddr: 0
Executing uInst: LAB0050:124
#MIR: (EUop←D1 Tag←D1 Raddr←Tos WCxt←Next Waddr←Arg NewTos←Tos' Tos'←Tos-1 NewArg←Arg' Arg'←Arg-1 
CondCode←Arg=Arg2 NextInstB←Rpt)
****************** Errors ******************
D1-21: 1 ← 0
D1-6: 1 ← 0
D1-2: 0 ← 1
D1-1: 0 ← 1
D1-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 0 #$Opcode 144 #NCurPc: 16
D1: Int/5 D2: Int/6 Tos: 20 RegAddr: 0
****************** Errors ******************
D1-21: 1 ← 0
D1-6: 1 ← 0
D1-2: 0 ← 1
****************** Errors ******************
#CONDA: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 0 #$Opcode 144 #NCurPc: 16
D1: Int/5 D2: -- Tos: 19 RegAddr: 0
Executing uInst: fn3:199
#MIR: (Label←Fn3 EUop←D1<24>/D2<8> Tag←D1 RD2addr←MuxRdSel MuxRdSel←Tos Raddr←K Waddr←K K←StkHdr)
****************** Errors ******************
D1-21: 1 ← 0
D1-6: 1 ← 0
D1-2: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 0 #$Opcode 144 #NCurPc: 16
D1: XType/1073741587 D2: Object/19 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 0 #$Opcode 144 #NCurPc: 16
D1: XType/1073741587 D2: -- Tos: 19 RegAddr: 0
Executing uInst: LAB0051:125
#MIR: (EUop←D2 Tag←D2 Dswap Raddr←K K←StkHdr RCxt←Next WCxt←Next NewTos←D2 NewTopCxt←Next 
NextInstA←Done)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 0 #$Opcode 144 #NCurPc: 16
D1: -- D2: Int/16 Tos: 19 RegAddr: 0
****************** Errors ******************
D1-31: 0 ← 1
D1-29: 0 ← 1
D1-28: 0 ← 1
D1-27: 0 ← 1
D1-26: 0 ← 1
D1-25: 0 ← 1
D1-24: 0 ← 1
D1-23: 0 ← 1
D1-22: 0 ← 1
D1-21: 0 ← 1
D1-20: 0 ← 1
D1-19: 0 ← 1
D1-18: 0 ← 1
D1-17: 0 ← 1
D1-16: 0 ← 1
D1-15: 0 ← 1
D1-14: 0 ← 1
D1-13: 0 ← 1
D1-12: 0 ← 1
D1-11: 0 ← 1
D1-10: 0 ← 1
D1-9: 0 ← 1
D1-8: 0 ← 1
D1-7: 0 ← 1
D1-6: 0 ← 1
D1-5: 0 ← 1
D1-3: 0 ← 1
D1-2: 0 ← 1
D1-1: 0 ← 1
D1-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 0 #$Opcode 0 #NCurPc: 16
D1: Int/16 D2: -- Tos: 16 RegAddr: 0
New Opcode: 0 Length: 0 Data: Object/0 N: 32 PC: 16 OldOpLength: 0
Executing uInst: loadibuf:209
#MIR: (Label←LoadIBuf Cycle←R4 RD1addr←PcAddr W2addr←IBufD2PcD1 EUop←+16 Tag←Int 
Misc←ResetInitialRefill CondCode←NoFault NextInstA←Done NextInstB←IBufPageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010010 $Opcode: 0 #$Opcode 0 #NCurPc: 16
D1: Int/304 D2: Atm/3584 Tos: 16 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010001 $Opcode: 0 #$Opcode 0 #NCurPc: 16
D1: Int/320 D2: XType/440 Tos: 16 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 0 #$Opcode 0 #NCurPc: 16
D1: -- D2: Int/304 Tos: 16 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 124 #$Opcode 0 #NCurPc: 16
D1: -- D2: Int/304 Tos: 16 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 124 #$Opcode 124 #NCurPc: 16
D1: -- D2: Int/304 Tos: 16 RegAddr: 0
New Opcode: 124 Length: 1 Data: Object/0 N: 127 PC: 16 OldOpLength: 1
Executing uInst: retnp:220
#MIR: (Label←Retnp EUop←D1 Tag←Int Raddr←K K←StkHdr CondCode←TrapOnExit NextInstA←Ufn-0)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 127 #$Opcode 124 #NCurPc: 17
D1: Int/16 D2: -- Tos: 16 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 127 #$Opcode 124 #NCurPc: 17
D1: Int/16 D2: -- Tos: 16 RegAddr: 0
Executing uInst: LAB0065:139
#MIR: (EUop←D1 Tag←Int RCxt←Prev Raddr←K K←Pc W2Addr←PcD1 NewTopCxt←Prev 
Misc←Oplength=0&SetInitialRefill)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 127 #$Opcode 124 #NCurPc: 17
D1: Int/24 D2: XType/1073741587 Tos: 16 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 127 #$Opcode 124 #NCurPc: 17
D1: Int/24 D2: -- Tos: 16 RegAddr: 0
Executing uInst: LAB0066:140
#MIR: (Dswap Raddr←K K←StkHdr NewTos←D2 NextInstA←Done)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 255 #$Opcode 124 #NCurPc: 24
D1: Int/24 D2: XType/1073741587 Tos: 16 RegAddr: 0
****************** Errors ******************
D1-31: 1 ← 0
D1-29: 1 ← 0
D1-28: 1 ← 0
D1-27: 1 ← 0
D1-26: 1 ← 0
D1-25: 1 ← 0
D1-24: 1 ← 0
D1-23: 1 ← 0
D1-22: 1 ← 0
D1-21: 1 ← 0
D1-20: 1 ← 0
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 255 #$Opcode 255 #NCurPc: 24
D1: Int/1073741823 D2: -- Tos: 19 RegAddr: 0
New Opcode: 255 Length: 0 Data: Object/0 N: 127 PC: 24 OldOpLength: 0
Executing uInst: loadibuf:209
#MIR: (Label←LoadIBuf Cycle←R4 RD1addr←PcAddr W2addr←IBufD2PcD1 EUop←+16 Tag←Int 
Misc←ResetInitialRefill CondCode←NoFault NextInstA←Done NextInstB←IBufPageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010010 $Opcode: 255 #$Opcode 255 #NCurPc: 24
D1: Int/16 D2: Code/100663360 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010001 $Opcode: 255 #$Opcode 255 #NCurPc: 24
D1: Int/32 D2: XType/1052630751 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 255 #$Opcode 255 #NCurPc: 24
D1: -- D2: XType/996638711 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 255 #$Opcode 255 #NCurPc: 24
D1: -- D2: Int/1072168443 Tos: 19 RegAddr: 0
****************** Errors ******************
#OPCODE-7: 0 ← 1
#OPCODE-4: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 255 #$Opcode 255 #NCurPc: 24
D1: -- D2: XType/1054604287 Tos: 19 RegAddr: 0
New Opcode: 255 Length: 0 Data: Object/0 N: 127 PC: 24 OldOpLength: 0
Executing uInst: loadibuf:209
#MIR: (Label←LoadIBuf Cycle←R4 RD1addr←PcAddr W2addr←IBufD2PcD1 EUop←+16 Tag←Int 
Misc←ResetInitialRefill CondCode←NoFault NextInstA←Done NextInstB←IBufPageFault)
****************** Errors ******************
#IBUFN-6: 0 ← 1
#IBUFN-5: 0 ← 1
#IBUFN-4: 0 ← 1
#IBUFN-3: 0 ← 1
#IBUFN-2: 0 ← 1
#IBUFN-1: 0 ← 1
#IBUFN-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010010 $Opcode: 255 #$Opcode 255 #NCurPc: 24
D1: Int/32 D2: Code/100663360 Tos: 19 RegAddr: 0
****************** Errors ******************
#IBUFN-6: 0 ← 1
#IBUFN-5: 0 ← 1
#IBUFN-4: 0 ← 1
#IBUFN-3: 0 ← 1
#IBUFN-2: 0 ← 1
#IBUFN-1: 0 ← 1
#IBUFN-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010001 $Opcode: 255 #$Opcode 255 #NCurPc: 24
D1: Int/48 D2: XType/987200381 Tos: 19 RegAddr: 0
****************** Errors ******************
#IBUFN-6: 0 ← 1
#IBUFN-5: 0 ← 1
#IBUFN-4: 0 ← 1
#IBUFN-3: 0 ← 1
#IBUFN-2: 0 ← 1
#IBUFN-1: 0 ← 1
#IBUFN-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 255 #$Opcode 255 #NCurPc: 24
D1: -- D2: Int/1072160763 Tos: 19 RegAddr: 0
****************** Errors ******************
#IBUFN-6: 0 ← 1
#IBUFN-5: 0 ← 1
#IBUFN-4: 0 ← 1
#IBUFN-3: 0 ← 1
#IBUFN-2: 0 ← 1
#IBUFN-1: 0 ← 1
#IBUFN-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 144 #$Opcode 255 #NCurPc: 24
D1: -- D2: XType/1054604287 Tos: 19 RegAddr: 0
****************** Errors ******************
#IBUFN-6: 0 ← 1
#IBUFN-5: 0 ← 1
#IBUFN-4: 0 ← 1
#IBUFN-3: 0 ← 1
#IBUFN-2: 0 ← 1
#IBUFN-1: 0 ← 1
#IBUFN-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 144 #$Opcode 144 #NCurPc: 24
D1: -- D2: XType/987200351 Tos: 19 RegAddr: 0
New Opcode: 144 Length: 5 Data: Object/2098177 N: 1 PC: 24 OldOpLength: 5
Executing uInst: pconst:80
#MIR: (Label←PConst EUop←D2<2>Shl24/D1<30> Tag←D2<8:7> RD2addr←MuxRdSel MuxRdSel←K K←PtrTypeBits 
RD1addr←IBufData Waddr←TOS' TOS'←TOS+1 NewTos←Tos' NextInstA←Done)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 20 #$Opcode 144 #NCurPc: 29
D1: Object/2098177 D2: Object/0 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 20 #$Opcode 20 #NCurPc: 29
D1: Object/2098177 D2: -- Tos: 20 RegAddr: 0
New Opcode: 20 Length: 1 Data: Object/0 N: 32 PC: 29 OldOpLength: 1
Executing uInst: copy:20
#MIR: (Label←Copy EUop←D1 Tag←D1 Raddr←Tos Waddr←Tos' Tos'←Tos+1 NewTos←Tos' NextInstA←Done)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 32 #$Opcode 20 #NCurPc: 30
D1: Object/2098177 D2: Int/6 Tos: 20 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 32 #$Opcode 32 #NCurPc: 30
D1: Object/2098177 D2: -- Tos: 21 RegAddr: 0
New Opcode: 32 Length: 2 Data: Object/64 N: 64 PC: 30 OldOpLength: 2
Executing uInst: getptr:32
#MIR: (Label←Getptr EUop←+ Tag←D2 Dswap Raddr←Tos RD1addr←IBufData W2addr←MarD1 Condcode←PointerpD2 
NextInstB←Ufn-1d)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 26 #$Opcode 32 #NCurPc: 0
D1: Object/64 D2: Object/2098177 Tos: 21 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 26 #$Opcode 32 #NCurPc: 0
D1: Object/2098241 D2: -- Tos: 21 RegAddr: 0
Executing uInst: LAB0033:65
#MIR: (Cycle←R1 Waddr←Tos CondCode←NoFault Cwrite NextInstA←Done NextInstB←PageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 26 #$Opcode 32 #NCurPc: 0
D1: Object/2098177 D2: Object/2098177 Tos: 21 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 26 #$Opcode 32 #NCurPc: 0
D1: -- D2: Int/16 Tos: 21 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 26 #$Opcode 32 #NCurPc: 0
D1: Object/2098177 D2: Object/2098177 Tos: 21 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 26 #$Opcode 32 #NCurPc: 0
D1: -- D2: -- Tos: 21 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 26 #$Opcode 32 #NCurPc: 0
D1: -- D2: -- Tos: 21 RegAddr: 0
Executing uInst: pagefault:212
#MIR: (Label←PageFault EUop←D1 Tag←Int RD1addr←Mar Waddr←Tos' Tos'←Tos+1 NewTos←Tos' NewArg←K K←1 
Misc←OpLength=0 CondCode←FramesAvail Cwrite NextInstB←DumpFrame)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 26 #$Opcode 32 #NCurPc: 0
D1: Object/2098241 D2: Object/2098177 Tos: 21 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 26 #$Opcode 32 #NCurPc: 0
D1: Int/2098241 D2: -- Tos: 22 RegAddr: 0
Executing uInst: LAB0072:146
#MIR: (EUop←D1 Tag←D1 Raddr←K K←PFCode RCxt←K W2addr←MarD1 NextInstA←Fn1)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 32 #$Opcode 32 #NCurPc: 30
D1: Code/100663424 D2: -- Tos: 22 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 32 #$Opcode 32 #NCurPc: 30
D1: Code/100663424 D2: -- Tos: 22 RegAddr: 0
Executing uInst: fn1:197
#MIR: (Label←Fn1 EUop←+4 Tag←D1 RD1addr←Mar W2addr←MarD1 NewArg2←Arg NewArg←K K←StkHdr CondCode←CCodeP
 NextInstB←Fn5)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 32 #$Opcode 32 #NCurPc: 30
D1: Code/100663424 D2: Object/2098177 Tos: 22 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 32 #$Opcode 32 #NCurPc: 30
D1: Code/100663428 D2: -- Tos: 22 RegAddr: 0
Executing uInst: LAB0041:115
#MIR: (Cycle←R4 WCxt←Next Waddr←Arg<6>/QW<2> EUop←+4 Tag←D1 RD1addr←Mar W2addr←MarD1 CondCode←NoFault 
NextInstB←PageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010010 $Opcode: 32 #$Opcode 32 #NCurPc: 30
D1: Code/100663428 D2: Object/2098177 Tos: 22 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010001 $Opcode: 32 #$Opcode 32 #NCurPc: 30
D1: Code/100663432 D2: Int/16 Tos: 22 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 32 #$Opcode 32 #NCurPc: 30
D1: -- D2: Int/0 Tos: 22 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 32 #$Opcode 32 #NCurPc: 30
D1: -- D2: Code/100663424 Tos: 22 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 32 #$Opcode 32 #NCurPc: 30
D1: -- D2: Code/100663424 Tos: 22 RegAddr: 0
Executing uInst: LAB0042:116
#MIR: (EUop←D2 Tag←D2 RD2addr←Unbound Waddr←K K←PVar WCxt←Next Misc←WriteOctal NewArg←Arg2)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 32 #$Opcode 32 #NCurPc: 30
D1: Int/2098241 D2: Ptr-32/0 Tos: 22 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 32 #$Opcode 32 #NCurPc: 30
D1: Ptr-32/0 D2: -- Tos: 22 RegAddr: 0
Executing uInst: fn2:198
#MIR: (Label←Fn2 EUop←D2 Tag←D2 RD2addr←Nil Waddr←K K←IVar WCxt←Next Misc←WriteOctal)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 32 #$Opcode 32 #NCurPc: 30
D1: Int/2098241 D2: Atm/3584 Tos: 22 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 32 #$Opcode 32 #NCurPc: 30
D1: Atm/3584 D2: -- Tos: 22 RegAddr: 0
Executing uInst: LAB0043:117
#MIR: (EUop←D2 Tag←Int RD2addr←PC Waddr←K K←Pc Misc←Oplength=0&SetInitialRefill)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 32 #$Opcode 32 #NCurPc: 30
D1: Int/2098241 D2: Int/30 Tos: 22 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 32 #$Opcode 32 #NCurPc: 30
D1: Int/30 D2: -- Tos: 22 RegAddr: 0
Executing uInst: LAB0044:118
#MIR: (EUop←+ Tag←Int RD1addr←Mar RD2addr←MuxRdSel MuxRdSel←Arg W2Addr←MarD1)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 32 #$Opcode 32 #NCurPc: 30
D1: Code/100663432 D2: Object/1 Tos: 22 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 32 #$Opcode 32 #NCurPc: 30
D1: Int/100663433 D2: -- Tos: 22 RegAddr: 0
Executing uInst: LAB0045:119
#MIR: (Cycle←R1 Waddr←K WCxt←Next K←Pc)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 32 #$Opcode 32 #NCurPc: 30
D1: Int/2098241 D2: Object/2098177 Tos: 22 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 32 #$Opcode 32 #NCurPc: 30
D1: Int/1073741823 D2: Int/560 Tos: 22 RegAddr: 0
Executing uInst: LAB0046:120
#MIR: (EUop←D1 Tag←Int Raddr←K RCxt←Next K←PC W2addr←PCD1)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 32 #$Opcode 32 #NCurPc: 30
D1: Int/560 D2: Int/16 Tos: 22 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 32 #$Opcode 32 #NCurPc: 30
D1: Int/560 D2: -- Tos: 22 RegAddr: 0
Executing uInst: LAB0047:121
#MIR: (EUop←D2 Tag←Int RD2addr←MuxRdSel MuxRdSel←K K←Ivar NewArg2←K W2addr←MarD1 NewArg←Arg' 
Arg'←Arg-1 CondCode←Arg#0 NextInstB←Fn3)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 0 #$Opcode 32 #NCurPc: 16
D1: Int/2098241 D2: Object/8 Tos: 22 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 0 #$Opcode 32 #NCurPc: 16
D1: Int/8 D2: -- Tos: 22 RegAddr: 0
Executing uInst: LAB0048:122
#MIR: (EUop←+ Tag←Int RD1addr←Mar RD2addr←MuxRdSel MuxRdSel←Arg W2addr←Tmp1D1)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 0 #$Opcode 32 #NCurPc: 16
D1: Int/8 D2: Object/0 Tos: 22 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 0 #$Opcode 32 #NCurPc: 16
D1: Int/8 D2: -- Tos: 22 RegAddr: 0
Executing uInst: LAB0049:123
#MIR: (RD2addr←Tmp1 NewArg←D2)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 0 #$Opcode 32 #NCurPc: 16
D1: Int/2098241 D2: Int/8 Tos: 22 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 0 #$Opcode 32 #NCurPc: 16
D1: Int/1073741823 D2: -- Tos: 22 RegAddr: 0
Executing uInst: LAB0050:124
#MIR: (EUop←D1 Tag←D1 Raddr←Tos WCxt←Next Waddr←Arg NewTos←Tos' Tos'←Tos-1 NewArg←Arg' Arg'←Arg-1 
CondCode←Arg=Arg2 NextInstB←Rpt)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 0 #$Opcode 32 #NCurPc: 16
D1: Int/2098241 D2: Object/2098177 Tos: 22 RegAddr: 0
****************** Errors ******************
#CONDA: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 0 #$Opcode 32 #NCurPc: 16
D1: Int/2098241 D2: -- Tos: 21 RegAddr: 0
Executing uInst: fn3:199
#MIR: (Label←Fn3 EUop←D1<24>/D2<8> Tag←D1 RD2addr←MuxRdSel MuxRdSel←Tos Raddr←K Waddr←K K←StkHdr)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 0 #$Opcode 32 #NCurPc: 16
D1: XType/1073741587 D2: Object/21 Tos: 21 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 0 #$Opcode 32 #NCurPc: 16
D1: XType/1073741589 D2: -- Tos: 21 RegAddr: 0
Executing uInst: LAB0051:125
#MIR: (EUop←D2 Tag←D2 Dswap Raddr←K K←StkHdr RCxt←Next WCxt←Next NewTos←D2 NewTopCxt←Next 
NextInstA←Done)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 0 #$Opcode 32 #NCurPc: 16
D1: -- D2: Int/16 Tos: 21 RegAddr: 0
****************** Errors ******************
D1-31: 0 ← 1
D1-29: 0 ← 1
D1-28: 0 ← 1
D1-27: 0 ← 1
D1-26: 0 ← 1
D1-25: 0 ← 1
D1-24: 0 ← 1
D1-23: 0 ← 1
D1-22: 0 ← 1
D1-21: 0 ← 1
D1-20: 0 ← 1
D1-19: 0 ← 1
D1-18: 0 ← 1
D1-17: 0 ← 1
D1-16: 0 ← 1
D1-15: 0 ← 1
D1-14: 0 ← 1
D1-13: 0 ← 1
D1-12: 0 ← 1
D1-11: 0 ← 1
D1-10: 0 ← 1
D1-9: 0 ← 1
D1-8: 0 ← 1
D1-7: 0 ← 1
D1-6: 0 ← 1
D1-5: 0 ← 1
D1-3: 0 ← 1
D1-2: 0 ← 1
D1-1: 0 ← 1
D1-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 0 #$Opcode 0 #NCurPc: 16
D1: Int/16 D2: -- Tos: 16 RegAddr: 0
New Opcode: 0 Length: 0 Data: Object/0 N: 32 PC: 16 OldOpLength: 0
Executing uInst: loadibuf:209
#MIR: (Label←LoadIBuf Cycle←R4 RD1addr←PcAddr W2addr←IBufD2PcD1 EUop←+16 Tag←Int 
Misc←ResetInitialRefill CondCode←NoFault NextInstA←Done NextInstB←IBufPageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010010 $Opcode: 0 #$Opcode 0 #NCurPc: 16
D1: Int/560 D2: Atm/3584 Tos: 16 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010001 $Opcode: 0 #$Opcode 0 #NCurPc: 16
D1: Int/576 D2: List/80235720 Tos: 16 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 0 #$Opcode 0 #NCurPc: 16
D1: -- D2: Int/862283366 Tos: 16 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 200 #$Opcode 0 #NCurPc: 16
D1: -- D2: XType/1069448763 Tos: 16 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 200 #$Opcode 200 #NCurPc: 16
D1: -- D2: XType/526176237 Tos: 16 RegAddr: 0
New Opcode: 200 Length: 1 Data: Object/0 N: 145 PC: 16 OldOpLength: 1
Executing uInst: vark:233
#MIR: (Label←Vark EUop←D1 Tag←D1 Raddr←0<4>/OpCode<4> Waddr←Tos' Tos'←Tos+1 NewTos←Tos' NextInstA←Done
)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 145 #$Opcode 200 #NCurPc: 17
D1: Int/2098241 D2: -- Tos: 16 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 145 #$Opcode 145 #NCurPc: 17
D1: Int/2098241 D2: -- Tos: 17 RegAddr: 0
New Opcode: 145 Length: 5 Data: Int/16777215 N: 255 PC: 17 OldOpLength: 5
Executing uInst: intconst:81
#MIR: (Label←IntConst EUop←D1 Tag←Int RD1addr←IBufData Waddr←TOS' TOS'←TOS+1 NewTos←Tos' 
NextInstA←Done)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 16 #$Opcode 145 #NCurPc: 22
D1: Int/16777215 D2: Ptr-32/0 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 16 #$Opcode 16 #NCurPc: 22
D1: Int/16777215 D2: -- Tos: 18 RegAddr: 0
New Opcode: 16 Length: 0 Data: Object/0 N: 47 PC: 22 OldOpLength: 0
Executing uInst: loadibuf:209
#MIR: (Label←LoadIBuf Cycle←R4 RD1addr←PcAddr W2addr←IBufD2PcD1 EUop←+16 Tag←Int 
Misc←ResetInitialRefill CondCode←NoFault NextInstA←Done NextInstB←IBufPageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010010 $Opcode: 16 #$Opcode 16 #NCurPc: 22
D1: Int/576 D2: Int/2098241 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010001 $Opcode: 16 #$Opcode 16 #NCurPc: 22
D1: Int/592 D2: XType/1071816350 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 16 #$Opcode 16 #NCurPc: 22
D1: -- D2: Float/1073477457 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 16 #$Opcode 16 #NCurPc: 22
D1: -- D2: XType/1004404446 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 16 #$Opcode 16 #NCurPc: 22
D1: -- D2: Int/1073217523 Tos: 18 RegAddr: 0
New Opcode: 16 Length: 1 Data: Object/0 N: 47 PC: 22 OldOpLength: 1
Executing uInst: and:16
#MIR: (Label←And EUop←And Tag←Int Raddr←Tos RD2addr←Raddr-1 Waddr←Tos' Tos'←Tos-1 NewTos←Tos' 
CondCode←IntegerD1D2 CWrite NextInstA←Done NextInstB←Ufn-2)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 47 #$Opcode 16 #NCurPc: 23
D1: Int/16777215 D2: Int/2098241 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 47 #$Opcode 47 #NCurPc: 23
D1: Int/2098241 D2: -- Tos: 17 RegAddr: 0
New Opcode: 47 Length: 2 Data: Object/10 N: 10 PC: 23 OldOpLength: 2
Executing uInst: lrsh.n:228
#MIR: (Label←Lrsh.N EUop←D1 Tag←Int Raddr←Tos W2addr←MarD1 NewArg←IBufN CondCode←Integerp 
NextInstB←Ufn-1d)
****************** Errors ******************
D1-23: 1 ← 0
D1-22: 1 ← 0
D1-20: 1 ← 0
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/2098241 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-23: 1 ← 0
D1-22: 1 ← 0
D1-20: 1 ← 0
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/2098241 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0031:105
#MIR: (Arg'←Arg-1 NewArg←Arg' CondCode←Arg=0 NextInstA←Done)
****************** Errors ******************
D1-23: 1 ← 0
D1-22: 1 ← 0
D1-20: 1 ← 0
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/2098241 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-23: 1 ← 0
D1-22: 1 ← 0
D1-20: 1 ← 0
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/1073741823 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/2098241 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-23: 1 ← 0
D1-22: 1 ← 0
D1-20: 1 ← 0
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/1049120 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-22: 1 ← 0
D1-21: 1 ← 0
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/1049120 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-22: 1 ← 0
D1-21: 1 ← 0
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/524560 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-21: 1 ← 0
D1-20: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/524560 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-21: 1 ← 0
D1-20: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/262280 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-20: 1 ← 0
D1-19: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/262280 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-20: 1 ← 0
D1-19: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/131140 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/131140 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/65570 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/65570 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/32785 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/32785 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/16392 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/16392 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/8196 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/8196 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/4098 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/4098 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 35 #NCurPc: 25
D1: Int/2049 D2: -- Tos: 17 RegAddr: 0
New Opcode: 35 Length: 2 Data: Object/0 N: 0 PC: 25 OldOpLength: 2
Executing uInst: settype:35
#MIR: (Label←SetType EUop←D2<2>Shl24/D1<30> Tag←D2<8:7> Raddr←Tos RD2addr←MuxRdSel MuxRdSel←IBufN 
Waddr←Tos NextInstA←Done)
****************** Errors ******************
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 20 #$Opcode 35 #NCurPc: 27
D1: Int/2049 D2: Object/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 20 #$Opcode 20 #NCurPc: 27
D1: Object/2049 D2: -- Tos: 17 RegAddr: 0
New Opcode: 20 Length: 1 Data: Object/0 N: 32 PC: 27 OldOpLength: 1
Executing uInst: copy:20
#MIR: (Label←Copy EUop←D1 Tag←D1 Raddr←Tos Waddr←Tos' Tos'←Tos+1 NewTos←Tos' NextInstA←Done)
****************** Errors ******************
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 32 #$Opcode 20 #NCurPc: 28
D1: Object/2049 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 32 #$Opcode 32 #NCurPc: 28
D1: Object/2049 D2: -- Tos: 18 RegAddr: 0
New Opcode: 32 Length: 2 Data: Object/0 N: 0 PC: 28 OldOpLength: 2
Executing uInst: getptr:32
#MIR: (Label←Getptr EUop←+ Tag←D2 Dswap Raddr←Tos RD1addr←IBufData W2addr←MarD1 Condcode←PointerpD2 
NextInstB←Ufn-1d)
****************** Errors ******************
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 185 #$Opcode 32 #NCurPc: 30
D1: Object/0 D2: Object/2049 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 185 #$Opcode 32 #NCurPc: 30
D1: Object/2049 D2: -- Tos: 18 RegAddr: 0
Executing uInst: LAB0033:65
#MIR: (Cycle←R1 Waddr←Tos CondCode←NoFault Cwrite NextInstA←Done NextInstB←PageFault)
****************** Errors ******************
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-6: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 185 #$Opcode 32 #NCurPc: 30
D1: Object/2049 D2: Object/2049 Tos: 18 RegAddr: 0
****************** Errors ******************
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-6: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 185 #$Opcode 185 #NCurPc: 30
D1: Int/1073741823 D2: Int/16 Tos: 18 RegAddr: 0
New Opcode: 185 Length: 1 Data: Object/0 N: 26 PC: 30 OldOpLength: 1
Executing uInst: vark←:234
#MIR: (Label←Vark← EUop←D1 Tag←D1 Raddr←Tos Waddr←0<4>/OpCode<4> NextInstA←Done)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 26 #$Opcode 185 #NCurPc: 31
D1: Int/16 D2: Object/2049 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 26 #$Opcode 26 #NCurPc: 31
D1: Int/16 D2: -- Tos: 18 RegAddr: 0
New Opcode: 26 Length: 1 Data: Object/0 N: 16 PC: 31 OldOpLength: 1
Executing uInst: '1:26
#MIR: (Label←'1 EUop←D2 Tag←Int RD2addr←MuxRdSel MuxRdSel←K K←1 Waddr←Tos' Tos'←Tos+1 NewTos←Tos' 
NextInstA←Done)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 16 #$Opcode 26 #NCurPc: 0
D1: Int/16 D2: Object/1 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 16 #$Opcode 16 #NCurPc: 0
D1: Int/1 D2: -- Tos: 19 RegAddr: 0
New Opcode: 16 Length: 1 Data: Object/0 N: 26 PC: 0 OldOpLength: 1
Executing uInst: and:16
#MIR: (Label←And EUop←And Tag←Int Raddr←Tos RD2addr←Raddr-1 Waddr←Tos' Tos'←Tos-1 NewTos←Tos' 
CondCode←IntegerD1D2 CWrite NextInstA←Done NextInstB←Ufn-2)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 26 #$Opcode 16 #NCurPc: 1
D1: Int/1 D2: Int/16 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 26 #$Opcode 26 #NCurPc: 1
D1: Int/0 D2: -- Tos: 18 RegAddr: 0
New Opcode: 26 Length: 1 Data: Object/0 N: 10 PC: 1 OldOpLength: 1
Executing uInst: '1:228
#MIR: (Label←'1 EUop←D2 Tag←Int RD2addr←MuxRdSel MuxRdSel←K K←1 Waddr←Tos' Tos'←Tos+1 NewTos←Tos' 
NextInstA←Done)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 10 #$Opcode 26 #NCurPc: 2
D1: Int/0 D2: Object/1 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 10 #$Opcode 10 #NCurPc: 2
D1: Int/1 D2: -- Tos: 19 RegAddr: 0
New Opcode: 10 Length: 1 Data: Object/0 N: 53 PC: 2 OldOpLength: 1
Executing uInst: eq:10
#MIR: (Label←Eq Raddr←Tos RD2addr←Raddr-1 Tos'←Tos-1 NewTos←Tos' CondCode←D1=D2 NextInstA←SetT 
NextInstB←SetNil)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 53 #$Opcode 10 #NCurPc: 3
D1: Int/1 D2: Int/0 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 53 #$Opcode 10 #NCurPc: 3
D1: Int/1073741823 D2: -- Tos: 18 RegAddr: 0
Executing uInst: setnil:222
#MIR: (Label←SetNil EUop←D2 Tag←D2 RD2addr←Nil Waddr←Tos NextInstA←Done)
****************** Errors ******************
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-6: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 53 #$Opcode 10 #NCurPc: 3
D1: Int/0 D2: Atm/3584 Tos: 18 RegAddr: 0
****************** Errors ******************
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-6: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 53 #$Opcode 53 #NCurPc: 3
D1: Atm/3584 D2: -- Tos: 18 RegAddr: 0
New Opcode: 53 Length: 2 Data: Object/7 N: 7 PC: 3 OldOpLength: 2
Executing uInst: fjump:53
#MIR: (Label←FJump EUop←nop Raddr←Tos Tos'←Tos-1 NewTos←Tos' Rd2addr←Nil Condcode←D1#D2 NextInstA←Done
 NextInstB←DoJmp)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 145 #$Opcode 53 #NCurPc: 5
D1: Atm/3584 D2: Atm/3584 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 145 #$Opcode 53 #NCurPc: 5
D1: Int/1073741823 D2: -- Tos: 17 RegAddr: 0
Executing uInst: dojmp:209
#MIR: (Label←DoJmp EUop←+ Tag←Int RD2addr←PC RD1addr←IBufData W2addr←PCD1 
Misc←Oplength=0&SetInitialRefill NextInstA←Dojmp1)
****************** Errors ******************
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-6: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 145 #$Opcode 53 #NCurPc: 5
D1: Object/7 D2: Int/581 Tos: 17 RegAddr: 0
****************** Errors ******************
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-6: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 145 #$Opcode 53 #NCurPc: 5
D1: Int/588 D2: -- Tos: 17 RegAddr: 0
Executing uInst: dojmp1:193
#MIR: (Label←DoJmp1 NextInstA←Done)
****************** Errors ******************
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-6: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 145 #$Opcode 53 #NCurPc: 12
D1: Object/2049 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-30: 1 ← 0
D1-11: 0 ← 1
D1-0: 0 ← 1
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-6: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 145 #$Opcode 145 #NCurPc: 12
D1: Int/1073741823 D2: -- Tos: 17 RegAddr: 0
New Opcode: 145 Length: 0 Data: Object/0 N: 1 PC: 12 OldOpLength: 0
Executing uInst: loadibuf:209
#MIR: (Label←LoadIBuf Cycle←R4 RD1addr←PcAddr W2addr←IBufD2PcD1 EUop←+16 Tag←Int 
Misc←ResetInitialRefill CondCode←NoFault NextInstA←Done NextInstB←IBufPageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010010 $Opcode: 145 #$Opcode 145 #NCurPc: 12
D1: Int/576 D2: Ptr-32/0 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010001 $Opcode: 145 #$Opcode 145 #NCurPc: 12
D1: Int/592 D2: XType/1071816350 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 145 #$Opcode 145 #NCurPc: 12
D1: -- D2: Float/1073477457 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 145 #$Opcode 145 #NCurPc: 12
D1: -- D2: XType/1004404446 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 145 #$Opcode 145 #NCurPc: 12
D1: -- D2: Int/1073217523 Tos: 17 RegAddr: 0
New Opcode: 145 Length: 0 Data: Object/0 N: 1 PC: 12 OldOpLength: 0
Executing uInst: loadibuf:209
#MIR: (Label←LoadIBuf Cycle←R4 RD1addr←PcAddr W2addr←IBufD2PcD1 EUop←+16 Tag←Int 
Misc←ResetInitialRefill CondCode←NoFault NextInstA←Done NextInstB←IBufPageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010010 $Opcode: 145 #$Opcode 145 #NCurPc: 12
D1: Int/592 D2: Ptr-32/0 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010001 $Opcode: 145 #$Opcode 145 #NCurPc: 12
D1: Int/608 D2: Float/871219192 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 145 #$Opcode 145 #NCurPc: 12
D1: -- D2: XType/747145454 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 145 #$Opcode 145 #NCurPc: 12
D1: -- D2: Object/0 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 145 #$Opcode 145 #NCurPc: 12
D1: -- D2: Object/0 Tos: 17 RegAddr: 0
New Opcode: 145 Length: 5 Data: Int/1 N: 1 PC: 12 OldOpLength: 5
Executing uInst: intconst:81
#MIR: (Label←IntConst EUop←D1 Tag←Int RD1addr←IBufData Waddr←TOS' TOS'←TOS+1 NewTos←Tos' 
NextInstA←Done)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 201 #$Opcode 145 #NCurPc: 17
D1: Int/1 D2: Ptr-32/0 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 201 #$Opcode 201 #NCurPc: 17
D1: Int/1 D2: -- Tos: 18 RegAddr: 0
New Opcode: 201 Length: 1 Data: Object/0 N: 17 PC: 17 OldOpLength: 1
Executing uInst: vark:233
#MIR: (Label←Vark EUop←D1 Tag←D1 Raddr←0<4>/OpCode<4> Waddr←Tos' Tos'←Tos+1 NewTos←Tos' NextInstA←Done
)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 17 #$Opcode 201 #NCurPc: 18
D1: Int/16 D2: Int/2098241 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 17 #$Opcode 17 #NCurPc: 18
D1: Int/16 D2: -- Tos: 19 RegAddr: 0
New Opcode: 17 Length: 1 Data: Object/0 N: 33 PC: 18 OldOpLength: 1
Executing uInst: or:17
#MIR: (Label←Or EUop←Or Tag←Int Raddr←Tos RD2addr←Raddr-1 Waddr←Tos' Tos'←Tos-1 NewTos←Tos' 
CondCode←IntegerD1D2 CWrite NextInstA←Done NextInstB←Ufn-2)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 33 #$Opcode 17 #NCurPc: 19
D1: Int/16 D2: Int/1 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 33 #$Opcode 33 #NCurPc: 19
D1: Int/17 D2: -- Tos: 18 RegAddr: 0
New Opcode: 33 Length: 2 Data: Object/0 N: 0 PC: 19 OldOpLength: 2
Executing uInst: putptr:228
#MIR: (Label←Putptr EUop←D2 Tag←D2 Raddr←Tos RD2addr←Raddr-1 W2addr←MarD1 Condcode←PointerpD2 
NextInstB←Ufn-2d)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 60 #$Opcode 33 #NCurPc: 21
D1: Int/17 D2: Object/2049 Tos: 18 RegAddr: 0
****************** Errors ******************
#CONDA: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 60 #$Opcode 33 #NCurPc: 21
D1: Object/2049 D2: -- Tos: 18 RegAddr: 0
Executing uInst: LAB0034:229
#MIR: (EUop←+ Tag←D1 RD1addr←Mar RD2addr←MuxRdSel MuxRdSel←IBufN W2addr←MarD1)
****************** Errors ******************
D1-30: 1 ← 0
D1-11: 0 ← 1
D1-4: 1 ← 0
VAD-11: 0 ← 1
VAD'-11: 1 ← 0
VAD'-4: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 60 #$Opcode 33 #NCurPc: 21
D1: Object/2049 D2: Object/0 Tos: 18 RegAddr: 0
****************** Errors ******************
D1-30: 1 ← 0
D1-11: 0 ← 1
D1-4: 1 ← 0
VAD-11: 0 ← 1
VAD'-11: 1 ← 0
VAD'-4: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 60 #$Opcode 33 #NCurPc: 21
D1: Object/2049 D2: -- Tos: 18 RegAddr: 0
Executing uInst: LAB0035:109
#MIR: (Cycle←W1 Dswap Raddr←Tos Tos'←Tos-1 NewTos←Tos' CondCode←NoFault CWrite NextInstA←Done 
NextInstB←PageFault)
****************** Errors ******************
D1-30: 1 ← 0
D1-11: 0 ← 1
D1-4: 1 ← 0
VAD-11: 0 ← 1
VAD'-11: 1 ← 0
VAD'-4: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 60 #$Opcode 33 #NCurPc: 21
D1: Object/2049 D2: Int/17 Tos: 18 RegAddr: 0
****************** Errors ******************
D1-30: 1 ← 0
D1-11: 0 ← 1
D1-4: 1 ← 0
VAD-11: 0 ← 1
VAD'-11: 1 ← 0
VAD'-4: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 60 #$Opcode 60 #NCurPc: 21
D1: Int/1073741823 D2: -- Tos: 17 RegAddr: 0
New Opcode: 60 Length: 0 Data: Object/0 N: 124 PC: 21 OldOpLength: 0
Executing uInst: loadibuf:209
#MIR: (Label←LoadIBuf Cycle←R4 RD1addr←PcAddr W2addr←IBufD2PcD1 EUop←+16 Tag←Int 
Misc←ResetInitialRefill CondCode←NoFault NextInstA←Done NextInstB←IBufPageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010010 $Opcode: 60 #$Opcode 60 #NCurPc: 21
D1: Int/608 D2: Ptr-32/0 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010001 $Opcode: 60 #$Opcode 60 #NCurPc: 21
D1: Int/624 D2: Object/0 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 60 #$Opcode 60 #NCurPc: 21
D1: -- D2: Object/0 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 60 #$Opcode 60 #NCurPc: 21
D1: -- D2: Object/0 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 60 #$Opcode 60 #NCurPc: 21
D1: -- D2: Object/0 Tos: 17 RegAddr: 0
New Opcode: 60 Length: 1 Data: Object/0 N: 124 PC: 21 OldOpLength: 1
Executing uInst: reset-vmm:219
#MIR: (Label←Reset-Vmm Misc←Reset-Vmm NextInstA←Done)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 124 #$Opcode 60 #NCurPc: 22
D1: Object/2049 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-30: 1 ← 0
D1-11: 0 ← 1
D1-4: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 124 #$Opcode 124 #NCurPc: 22
D1: Int/1073741823 D2: -- Tos: 17 RegAddr: 0
New Opcode: 124 Length: 1 Data: Object/0 N: 255 PC: 22 OldOpLength: 1
Executing uInst: retnp:220
#MIR: (Label←Retnp EUop←D1 Tag←Int Raddr←K K←StkHdr CondCode←TrapOnExit NextInstA←Ufn-0)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 255 #$Opcode 124 #NCurPc: 23
D1: Int/16 D2: -- Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 255 #$Opcode 124 #NCurPc: 23
D1: Int/16 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0065:139
#MIR: (EUop←D1 Tag←Int RCxt←Prev Raddr←K K←Pc W2Addr←PcD1 NewTopCxt←Prev 
Misc←Oplength=0&SetInitialRefill)
****************** Errors ******************
VAD-11: 0 ← 1
VAD'-11: 1 ← 0
VAD'-4: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 255 #$Opcode 124 #NCurPc: 23
D1: Int/30 D2: XType/1073741589 Tos: 17 RegAddr: 0
****************** Errors ******************
VAD-11: 0 ← 1
VAD'-11: 1 ← 0
VAD'-4: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 255 #$Opcode 124 #NCurPc: 23
D1: Int/30 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0066:140
#MIR: (Dswap Raddr←K K←StkHdr NewTos←D2 NextInstA←Done)
****************** Errors ******************
VAD-11: 0 ← 1
VAD'-11: 1 ← 0
VAD'-4: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 255 #$Opcode 124 #NCurPc: 30
D1: Int/30 D2: XType/1073741589 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-31: 1 ← 0
D1-29: 1 ← 0
D1-28: 1 ← 0
D1-27: 1 ← 0
D1-26: 1 ← 0
D1-25: 1 ← 0
D1-24: 1 ← 0
D1-23: 1 ← 0
D1-22: 1 ← 0
D1-21: 1 ← 0
D1-20: 1 ← 0
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-0: 1 ← 0
VAD-11: 0 ← 1
VAD'-11: 1 ← 0
VAD'-4: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 255 #$Opcode 255 #NCurPc: 30
D1: Int/1073741823 D2: -- Tos: 21 RegAddr: 0
New Opcode: 255 Length: 0 Data: Object/0 N: 255 PC: 30 OldOpLength: 0
Executing uInst: loadibuf:209
#MIR: (Label←LoadIBuf Cycle←R4 RD1addr←PcAddr W2addr←IBufD2PcD1 EUop←+16 Tag←Int 
Misc←ResetInitialRefill CondCode←NoFault NextInstA←Done NextInstB←IBufPageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010010 $Opcode: 255 #$Opcode 255 #NCurPc: 30
D1: Int/16 D2: Object/2098177 Tos: 21 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010001 $Opcode: 255 #$Opcode 255 #NCurPc: 30
D1: Int/32 D2: XType/1052630751 Tos: 21 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 255 #$Opcode 255 #NCurPc: 30
D1: -- D2: XType/996638711 Tos: 21 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 255 #$Opcode 255 #NCurPc: 30
D1: -- D2: Int/1072168443 Tos: 21 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 255 #$Opcode 255 #NCurPc: 30
D1: -- D2: XType/1054604287 Tos: 21 RegAddr: 0
New Opcode: 255 Length: 0 Data: Object/0 N: 255 PC: 30 OldOpLength: 0
Executing uInst: loadibuf:209
#MIR: (Label←LoadIBuf Cycle←R4 RD1addr←PcAddr W2addr←IBufD2PcD1 EUop←+16 Tag←Int 
Misc←ResetInitialRefill CondCode←NoFault NextInstA←Done NextInstB←IBufPageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010010 $Opcode: 255 #$Opcode 255 #NCurPc: 30
D1: Int/32 D2: Object/2098177 Tos: 21 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010001 $Opcode: 255 #$Opcode 255 #NCurPc: 30
D1: Int/48 D2: XType/987200381 Tos: 21 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 255 #$Opcode 255 #NCurPc: 30
D1: -- D2: Int/1072160763 Tos: 21 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 32 #$Opcode 255 #NCurPc: 30
D1: -- D2: XType/1054604287 Tos: 21 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 32 #$Opcode 32 #NCurPc: 30
D1: -- D2: XType/987200351 Tos: 21 RegAddr: 0
New Opcode: 32 Length: 2 Data: Object/64 N: 64 PC: 30 OldOpLength: 2
Executing uInst: getptr:32
#MIR: (Label←Getptr EUop←+ Tag←D2 Dswap Raddr←Tos RD1addr←IBufData W2addr←MarD1 Condcode←PointerpD2 
NextInstB←Ufn-1d)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 26 #$Opcode 32 #NCurPc: 0
D1: Object/64 D2: Object/2098177 Tos: 21 RegAddr: 0
****************** Errors ******************
#CONDA: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 26 #$Opcode 32 #NCurPc: 0
D1: Object/2098241 D2: -- Tos: 21 RegAddr: 0
Executing uInst: LAB0033:65
#MIR: (Cycle←R1 Waddr←Tos CondCode←NoFault Cwrite NextInstA←Done NextInstB←PageFault)
****************** Errors ******************
D1-30: 1 ← 0
D1-7: 1 ← 0
D1-6: 0 ← 1
VAD'-7: 0 ← 1
VAD'-6: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 26 #$Opcode 32 #NCurPc: 0
D1: Object/2098177 D2: Object/2098177 Tos: 21 RegAddr: 0
****************** Errors ******************
D1-30: 1 ← 0
D1-6: 1 ← 0
VAD'-7: 0 ← 1
VAD'-6: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 26 #$Opcode 32 #NCurPc: 0
D1: -- D2: Int/17 Tos: 21 RegAddr: 0
****************** Errors ******************
VAD'-7: 0 ← 1
VAD'-6: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 26 #$Opcode 32 #NCurPc: 0
D1: Object/2098177 D2: Object/2098177 Tos: 21 RegAddr: 0
****************** Errors ******************
D1-30: 1 ← 0
D1-6: 1 ← 0
VAD'-7: 0 ← 1
VAD'-6: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 26 #$Opcode 26 #NCurPc: 0
D1: Int/1073741823 D2: Int/6 Tos: 21 RegAddr: 0
New Opcode: 26 Length: 1 Data: Object/0 N: 68 PC: 0 OldOpLength: 1
Executing uInst: '1:26
#MIR: (Label←'1 EUop←D2 Tag←Int RD2addr←MuxRdSel MuxRdSel←K K←1 Waddr←Tos' Tos'←Tos+1 NewTos←Tos' 
NextInstA←Done)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 68 #$Opcode 26 #NCurPc: 1
D1: Int/6 D2: Object/1 Tos: 21 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 68 #$Opcode 68 #NCurPc: 1
D1: Int/1 D2: -- Tos: 22 RegAddr: 0
New Opcode: 68 Length: 1 Data: Object/0 N: 33 PC: 1 OldOpLength: 1
Executing uInst: plus:213
#MIR: (Label←Plus EUop←+ Tag←Int Raddr←Tos RD2addr←Raddr-1 W2addr←Tmp1D1 CondCode←IntegerD1D2 
NextInstB←Ufn-2)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 33 #$Opcode 68 #NCurPc: 2
D1: Int/1 D2: Int/6 Tos: 22 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 33 #$Opcode 68 #NCurPc: 2
D1: Int/7 D2: -- Tos: 22 RegAddr: 0
Executing uInst: LAB0019:228
#MIR: (EUop←D2 Tag←Int RD2addr←Tmp1 Waddr←Tos' Tos'←Tos-1 NewTos←Tos' CondCode←NoOverflow CWrite 
NextInstA←Done NextInstB←Ufn-2)
****************** Errors ******************
D1-2: 0 ← 1
D1-0: 0 ← 1
VAD'-7: 0 ← 1
VAD'-6: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 33 #$Opcode 68 #NCurPc: 2
D1: Int/1 D2: Int/7 Tos: 22 RegAddr: 0
****************** Errors ******************
VAD'-7: 0 ← 1
VAD'-6: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 33 #$Opcode 33 #NCurPc: 2
D1: Int/7 D2: -- Tos: 21 RegAddr: 0
New Opcode: 33 Length: 2 Data: Object/64 N: 64 PC: 2 OldOpLength: 2
Executing uInst: putptr:33
#MIR: (Label←Putptr EUop←D2 Tag←D2 Raddr←Tos RD2addr←Raddr-1 W2addr←MarD1 Condcode←PointerpD2 
NextInstB←Ufn-2d)
****************** Errors ******************
D1-2: 0 ← 1
D1-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 144 #$Opcode 33 #NCurPc: 4
D1: Int/7 D2: Object/2098177 Tos: 21 RegAddr: 0
****************** Errors ******************
D1-2: 0 ← 1
D1-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 144 #$Opcode 33 #NCurPc: 4
D1: Object/2098177 D2: -- Tos: 21 RegAddr: 0
Executing uInst: LAB0034:229
#MIR: (EUop←+ Tag←D1 RD1addr←Mar RD2addr←MuxRdSel MuxRdSel←IBufN W2addr←MarD1)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 144 #$Opcode 33 #NCurPc: 4
D1: Object/2098177 D2: Object/64 Tos: 21 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 144 #$Opcode 33 #NCurPc: 4
D1: Object/2098241 D2: -- Tos: 21 RegAddr: 0
Executing uInst: LAB0035:109
#MIR: (Cycle←W1 Dswap Raddr←Tos Tos'←Tos-1 NewTos←Tos' CondCode←NoFault CWrite NextInstA←Done 
NextInstB←PageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 144 #$Opcode 33 #NCurPc: 4
D1: Object/2098177 D2: Int/7 Tos: 21 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 144 #$Opcode 33 #NCurPc: 4
D1: -- D2: -- Tos: 21 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 144 #$Opcode 33 #NCurPc: 4
D1: -- D2: -- Tos: 21 RegAddr: 0
Executing uInst: pagefault:212
#MIR: (Label←PageFault EUop←D1 Tag←Int RD1addr←Mar Waddr←Tos' Tos'←Tos+1 NewTos←Tos' NewArg←K K←1 
Misc←OpLength=0 CondCode←FramesAvail Cwrite NextInstB←DumpFrame)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 144 #$Opcode 33 #NCurPc: 4
D1: Object/2098241 D2: Object/2098177 Tos: 21 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 144 #$Opcode 33 #NCurPc: 4
D1: Int/2098241 D2: -- Tos: 22 RegAddr: 0
Executing uInst: LAB0072:146
#MIR: (EUop←D1 Tag←D1 Raddr←K K←PFCode RCxt←K W2addr←MarD1 NextInstA←Fn1)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 33 #$Opcode 33 #NCurPc: 2
D1: Code/100663424 D2: -- Tos: 22 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 33 #$Opcode 33 #NCurPc: 2
D1: Code/100663424 D2: -- Tos: 22 RegAddr: 0
Executing uInst: fn1:197
#MIR: (Label←Fn1 EUop←+4 Tag←D1 RD1addr←Mar W2addr←MarD1 NewArg2←Arg NewArg←K K←StkHdr CondCode←CCodeP
 NextInstB←Fn5)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 33 #$Opcode 33 #NCurPc: 2
D1: Code/100663424 D2: Int/7 Tos: 22 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 33 #$Opcode 33 #NCurPc: 2
D1: Code/100663428 D2: -- Tos: 22 RegAddr: 0
Executing uInst: LAB0041:115
#MIR: (Cycle←R4 WCxt←Next Waddr←Arg<6>/QW<2> EUop←+4 Tag←D1 RD1addr←Mar W2addr←MarD1 CondCode←NoFault 
NextInstB←PageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010010 $Opcode: 33 #$Opcode 33 #NCurPc: 2
D1: Code/100663428 D2: Int/7 Tos: 22 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010001 $Opcode: 33 #$Opcode 33 #NCurPc: 2
D1: Code/100663432 D2: Int/16 Tos: 22 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 33 #$Opcode 33 #NCurPc: 2
D1: -- D2: Int/0 Tos: 22 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 33 #$Opcode 33 #NCurPc: 2
D1: -- D2: Code/100663424 Tos: 22 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 33 #$Opcode 33 #NCurPc: 2
D1: -- D2: Code/100663424 Tos: 22 RegAddr: 0
Executing uInst: LAB0042:116
#MIR: (EUop←D2 Tag←D2 RD2addr←Unbound Waddr←K K←PVar WCxt←Next Misc←WriteOctal NewArg←Arg2)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 33 #$Opcode 33 #NCurPc: 2
D1: Int/2098241 D2: Ptr-32/0 Tos: 22 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 33 #$Opcode 33 #NCurPc: 2
D1: Ptr-32/0 D2: -- Tos: 22 RegAddr: 0
Executing uInst: fn2:198
#MIR: (Label←Fn2 EUop←D2 Tag←D2 RD2addr←Nil Waddr←K K←IVar WCxt←Next Misc←WriteOctal)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 33 #$Opcode 33 #NCurPc: 2
D1: Int/2098241 D2: Atm/3584 Tos: 22 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 33 #$Opcode 33 #NCurPc: 2
D1: Atm/3584 D2: -- Tos: 22 RegAddr: 0
Executing uInst: LAB0043:117
#MIR: (EUop←D2 Tag←Int RD2addr←PC Waddr←K K←Pc Misc←Oplength=0&SetInitialRefill)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 33 #$Opcode 33 #NCurPc: 2
D1: Int/2098241 D2: Int/34 Tos: 22 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 33 #$Opcode 33 #NCurPc: 2
D1: Int/34 D2: -- Tos: 22 RegAddr: 0
Executing uInst: LAB0044:118
#MIR: (EUop←+ Tag←Int RD1addr←Mar RD2addr←MuxRdSel MuxRdSel←Arg W2Addr←MarD1)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 33 #$Opcode 33 #NCurPc: 2
D1: Code/100663432 D2: Object/1 Tos: 22 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 33 #$Opcode 33 #NCurPc: 2
D1: Int/100663433 D2: -- Tos: 22 RegAddr: 0
Executing uInst: LAB0045:119
#MIR: (Cycle←R1 Waddr←K WCxt←Next K←Pc)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 33 #$Opcode 33 #NCurPc: 2
D1: Int/2098241 D2: Int/7 Tos: 22 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 33 #$Opcode 33 #NCurPc: 2
D1: Int/1073741823 D2: Int/560 Tos: 22 RegAddr: 0
Executing uInst: LAB0046:120
#MIR: (EUop←D1 Tag←Int Raddr←K RCxt←Next K←PC W2addr←PCD1)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 33 #$Opcode 33 #NCurPc: 2
D1: Int/560 D2: Int/16 Tos: 22 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 33 #$Opcode 33 #NCurPc: 2
D1: Int/560 D2: -- Tos: 22 RegAddr: 0
Executing uInst: LAB0047:121
#MIR: (EUop←D2 Tag←Int RD2addr←MuxRdSel MuxRdSel←K K←Ivar NewArg2←K W2addr←MarD1 NewArg←Arg' 
Arg'←Arg-1 CondCode←Arg#0 NextInstB←Fn3)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 0 #$Opcode 33 #NCurPc: 16
D1: Int/2098241 D2: Object/8 Tos: 22 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 0 #$Opcode 33 #NCurPc: 16
D1: Int/8 D2: -- Tos: 22 RegAddr: 0
Executing uInst: LAB0048:122
#MIR: (EUop←+ Tag←Int RD1addr←Mar RD2addr←MuxRdSel MuxRdSel←Arg W2addr←Tmp1D1)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 0 #$Opcode 33 #NCurPc: 16
D1: Int/8 D2: Object/0 Tos: 22 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 0 #$Opcode 33 #NCurPc: 16
D1: Int/8 D2: -- Tos: 22 RegAddr: 0
Executing uInst: LAB0049:123
#MIR: (RD2addr←Tmp1 NewArg←D2)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 0 #$Opcode 33 #NCurPc: 16
D1: Int/2098241 D2: Int/8 Tos: 22 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 0 #$Opcode 33 #NCurPc: 16
D1: Int/1073741823 D2: -- Tos: 22 RegAddr: 0
Executing uInst: LAB0050:124
#MIR: (EUop←D1 Tag←D1 Raddr←Tos WCxt←Next Waddr←Arg NewTos←Tos' Tos'←Tos-1 NewArg←Arg' Arg'←Arg-1 
CondCode←Arg=Arg2 NextInstB←Rpt)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 0 #$Opcode 33 #NCurPc: 16
D1: Int/2098241 D2: Int/7 Tos: 22 RegAddr: 0
****************** Errors ******************
#CONDA: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 0 #$Opcode 33 #NCurPc: 16
D1: Int/2098241 D2: -- Tos: 21 RegAddr: 0
Executing uInst: fn3:199
#MIR: (Label←Fn3 EUop←D1<24>/D2<8> Tag←D1 RD2addr←MuxRdSel MuxRdSel←Tos Raddr←K Waddr←K K←StkHdr)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 0 #$Opcode 33 #NCurPc: 16
D1: XType/1073741589 D2: Object/21 Tos: 21 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 0 #$Opcode 33 #NCurPc: 16
D1: XType/1073741589 D2: -- Tos: 21 RegAddr: 0
Executing uInst: LAB0051:125
#MIR: (EUop←D2 Tag←D2 Dswap Raddr←K K←StkHdr RCxt←Next WCxt←Next NewTos←D2 NewTopCxt←Next 
NextInstA←Done)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 0 #$Opcode 33 #NCurPc: 16
D1: -- D2: Int/16 Tos: 21 RegAddr: 0
****************** Errors ******************
D1-31: 0 ← 1
D1-29: 0 ← 1
D1-28: 0 ← 1
D1-27: 0 ← 1
D1-26: 0 ← 1
D1-25: 0 ← 1
D1-24: 0 ← 1
D1-23: 0 ← 1
D1-22: 0 ← 1
D1-21: 0 ← 1
D1-20: 0 ← 1
D1-19: 0 ← 1
D1-18: 0 ← 1
D1-17: 0 ← 1
D1-16: 0 ← 1
D1-15: 0 ← 1
D1-14: 0 ← 1
D1-13: 0 ← 1
D1-12: 0 ← 1
D1-11: 0 ← 1
D1-10: 0 ← 1
D1-9: 0 ← 1
D1-8: 0 ← 1
D1-7: 0 ← 1
D1-6: 0 ← 1
D1-5: 0 ← 1
D1-3: 0 ← 1
D1-2: 0 ← 1
D1-1: 0 ← 1
D1-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 0 #$Opcode 0 #NCurPc: 16
D1: Int/16 D2: -- Tos: 16 RegAddr: 0
New Opcode: 0 Length: 0 Data: Object/0 N: 32 PC: 16 OldOpLength: 0
Executing uInst: loadibuf:209
#MIR: (Label←LoadIBuf Cycle←R4 RD1addr←PcAddr W2addr←IBufD2PcD1 EUop←+16 Tag←Int 
Misc←ResetInitialRefill CondCode←NoFault NextInstA←Done NextInstB←IBufPageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010010 $Opcode: 0 #$Opcode 0 #NCurPc: 16
D1: Int/560 D2: Atm/3584 Tos: 16 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010001 $Opcode: 0 #$Opcode 0 #NCurPc: 16
D1: Int/576 D2: List/80235720 Tos: 16 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 0 #$Opcode 0 #NCurPc: 16
D1: -- D2: Int/862283366 Tos: 16 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 200 #$Opcode 0 #NCurPc: 16
D1: -- D2: XType/1069448763 Tos: 16 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 200 #$Opcode 200 #NCurPc: 16
D1: -- D2: XType/526176237 Tos: 16 RegAddr: 0
New Opcode: 200 Length: 1 Data: Object/0 N: 145 PC: 16 OldOpLength: 1
Executing uInst: vark:233
#MIR: (Label←Vark EUop←D1 Tag←D1 Raddr←0<4>/OpCode<4> Waddr←Tos' Tos'←Tos+1 NewTos←Tos' NextInstA←Done
)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 145 #$Opcode 200 #NCurPc: 17
D1: Int/2098241 D2: -- Tos: 16 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 145 #$Opcode 145 #NCurPc: 17
D1: Int/2098241 D2: -- Tos: 17 RegAddr: 0
New Opcode: 145 Length: 5 Data: Int/16777215 N: 255 PC: 17 OldOpLength: 5
Executing uInst: intconst:81
#MIR: (Label←IntConst EUop←D1 Tag←Int RD1addr←IBufData Waddr←TOS' TOS'←TOS+1 NewTos←Tos' 
NextInstA←Done)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 16 #$Opcode 145 #NCurPc: 22
D1: Int/16777215 D2: Ptr-32/0 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 16 #$Opcode 16 #NCurPc: 22
D1: Int/16777215 D2: -- Tos: 18 RegAddr: 0
New Opcode: 16 Length: 0 Data: Object/0 N: 47 PC: 22 OldOpLength: 0
Executing uInst: loadibuf:209
#MIR: (Label←LoadIBuf Cycle←R4 RD1addr←PcAddr W2addr←IBufD2PcD1 EUop←+16 Tag←Int 
Misc←ResetInitialRefill CondCode←NoFault NextInstA←Done NextInstB←IBufPageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010010 $Opcode: 16 #$Opcode 16 #NCurPc: 22
D1: Int/576 D2: Int/2098241 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010001 $Opcode: 16 #$Opcode 16 #NCurPc: 22
D1: Int/592 D2: XType/1071816350 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 16 #$Opcode 16 #NCurPc: 22
D1: -- D2: Float/1073477457 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 16 #$Opcode 16 #NCurPc: 22
D1: -- D2: XType/1004404446 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 16 #$Opcode 16 #NCurPc: 22
D1: -- D2: Int/1073217523 Tos: 18 RegAddr: 0
New Opcode: 16 Length: 1 Data: Object/0 N: 47 PC: 22 OldOpLength: 1
Executing uInst: and:16
#MIR: (Label←And EUop←And Tag←Int Raddr←Tos RD2addr←Raddr-1 Waddr←Tos' Tos'←Tos-1 NewTos←Tos' 
CondCode←IntegerD1D2 CWrite NextInstA←Done NextInstB←Ufn-2)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 47 #$Opcode 16 #NCurPc: 23
D1: Int/16777215 D2: Int/2098241 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 47 #$Opcode 47 #NCurPc: 23
D1: Int/2098241 D2: -- Tos: 17 RegAddr: 0
New Opcode: 47 Length: 2 Data: Object/10 N: 10 PC: 23 OldOpLength: 2
Executing uInst: lrsh.n:228
#MIR: (Label←Lrsh.N EUop←D1 Tag←Int Raddr←Tos W2addr←MarD1 NewArg←IBufN CondCode←Integerp 
NextInstB←Ufn-1d)
****************** Errors ******************
D1-23: 1 ← 0
D1-22: 1 ← 0
D1-20: 1 ← 0
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/2098241 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-23: 1 ← 0
D1-22: 1 ← 0
D1-20: 1 ← 0
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/2098241 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0031:105
#MIR: (Arg'←Arg-1 NewArg←Arg' CondCode←Arg=0 NextInstA←Done)
****************** Errors ******************
D1-23: 1 ← 0
D1-22: 1 ← 0
D1-20: 1 ← 0
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/2098241 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-23: 1 ← 0
D1-22: 1 ← 0
D1-20: 1 ← 0
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/1073741823 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/2098241 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-23: 1 ← 0
D1-22: 1 ← 0
D1-20: 1 ← 0
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/1049120 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-22: 1 ← 0
D1-21: 1 ← 0
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/1049120 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-22: 1 ← 0
D1-21: 1 ← 0
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/524560 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-21: 1 ← 0
D1-20: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/524560 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-21: 1 ← 0
D1-20: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/262280 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-20: 1 ← 0
D1-19: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/262280 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-20: 1 ← 0
D1-19: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/131140 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/131140 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/65570 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/65570 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/32785 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/32785 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/16392 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/16392 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/8196 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/8196 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/4098 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/4098 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-11: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-11: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 35 #NCurPc: 25
D1: Int/2049 D2: -- Tos: 17 RegAddr: 0
New Opcode: 35 Length: 2 Data: Object/0 N: 0 PC: 25 OldOpLength: 2
Executing uInst: settype:35
#MIR: (Label←SetType EUop←D2<2>Shl24/D1<30> Tag←D2<8:7> Raddr←Tos RD2addr←MuxRdSel MuxRdSel←IBufN 
Waddr←Tos NextInstA←Done)
****************** Errors ******************
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 20 #$Opcode 35 #NCurPc: 27
D1: Int/2049 D2: Object/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 20 #$Opcode 20 #NCurPc: 27
D1: Object/2049 D2: -- Tos: 17 RegAddr: 0
New Opcode: 20 Length: 1 Data: Object/0 N: 32 PC: 27 OldOpLength: 1
Executing uInst: copy:20
#MIR: (Label←Copy EUop←D1 Tag←D1 Raddr←Tos Waddr←Tos' Tos'←Tos+1 NewTos←Tos' NextInstA←Done)
****************** Errors ******************
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 32 #$Opcode 20 #NCurPc: 28
D1: Object/2049 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 32 #$Opcode 32 #NCurPc: 28
D1: Object/2049 D2: -- Tos: 18 RegAddr: 0
New Opcode: 32 Length: 2 Data: Object/0 N: 0 PC: 28 OldOpLength: 2
Executing uInst: getptr:32
#MIR: (Label←Getptr EUop←+ Tag←D2 Dswap Raddr←Tos RD1addr←IBufData W2addr←MarD1 Condcode←PointerpD2 
NextInstB←Ufn-1d)
****************** Errors ******************
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 185 #$Opcode 32 #NCurPc: 30
D1: Object/0 D2: Object/2049 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 185 #$Opcode 32 #NCurPc: 30
D1: Object/2049 D2: -- Tos: 18 RegAddr: 0
Executing uInst: LAB0033:65
#MIR: (Cycle←R1 Waddr←Tos CondCode←NoFault Cwrite NextInstA←Done NextInstB←PageFault)
****************** Errors ******************
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-6: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 185 #$Opcode 32 #NCurPc: 30
D1: Object/2049 D2: Object/2049 Tos: 18 RegAddr: 0
****************** Errors ******************
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-6: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 185 #$Opcode 185 #NCurPc: 30
D1: Int/1073741823 D2: Int/17 Tos: 18 RegAddr: 0
New Opcode: 185 Length: 1 Data: Object/0 N: 26 PC: 30 OldOpLength: 1
Executing uInst: vark←:234
#MIR: (Label←Vark← EUop←D1 Tag←D1 Raddr←Tos Waddr←0<4>/OpCode<4> NextInstA←Done)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 26 #$Opcode 185 #NCurPc: 31
D1: Int/17 D2: Object/2049 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 26 #$Opcode 26 #NCurPc: 31
D1: Int/17 D2: -- Tos: 18 RegAddr: 0
New Opcode: 26 Length: 1 Data: Object/0 N: 16 PC: 31 OldOpLength: 1
Executing uInst: '1:26
#MIR: (Label←'1 EUop←D2 Tag←Int RD2addr←MuxRdSel MuxRdSel←K K←1 Waddr←Tos' Tos'←Tos+1 NewTos←Tos' 
NextInstA←Done)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 16 #$Opcode 26 #NCurPc: 0
D1: Int/17 D2: Object/1 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 16 #$Opcode 16 #NCurPc: 0
D1: Int/1 D2: -- Tos: 19 RegAddr: 0
New Opcode: 16 Length: 1 Data: Object/0 N: 26 PC: 0 OldOpLength: 1
Executing uInst: and:16
#MIR: (Label←And EUop←And Tag←Int Raddr←Tos RD2addr←Raddr-1 Waddr←Tos' Tos'←Tos-1 NewTos←Tos' 
CondCode←IntegerD1D2 CWrite NextInstA←Done NextInstB←Ufn-2)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 26 #$Opcode 16 #NCurPc: 1
D1: Int/1 D2: Int/17 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 26 #$Opcode 26 #NCurPc: 1
D1: Int/1 D2: -- Tos: 18 RegAddr: 0
New Opcode: 26 Length: 1 Data: Object/0 N: 10 PC: 1 OldOpLength: 1
Executing uInst: '1:228
#MIR: (Label←'1 EUop←D2 Tag←Int RD2addr←MuxRdSel MuxRdSel←K K←1 Waddr←Tos' Tos'←Tos+1 NewTos←Tos' 
NextInstA←Done)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 10 #$Opcode 26 #NCurPc: 2
D1: Int/1 D2: Object/1 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 10 #$Opcode 10 #NCurPc: 2
D1: Int/1 D2: -- Tos: 19 RegAddr: 0
New Opcode: 10 Length: 1 Data: Object/0 N: 53 PC: 2 OldOpLength: 1
Executing uInst: eq:10
#MIR: (Label←Eq Raddr←Tos RD2addr←Raddr-1 Tos'←Tos-1 NewTos←Tos' CondCode←D1=D2 NextInstA←SetT 
NextInstB←SetNil)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 53 #$Opcode 10 #NCurPc: 3
D1: Int/1 D2: Int/1 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 53 #$Opcode 10 #NCurPc: 3
D1: Int/1073741823 D2: -- Tos: 18 RegAddr: 0
Executing uInst: sett:222
#MIR: (Label←SetT EUop←D2 Tag←D2 RD2addr←T Waddr←Tos NextInstA←Done)
****************** Errors ******************
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-6: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 53 #$Opcode 10 #NCurPc: 3
D1: Int/1 D2: Atm/3600 Tos: 18 RegAddr: 0
****************** Errors ******************
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-6: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 53 #$Opcode 53 #NCurPc: 3
D1: Atm/3600 D2: -- Tos: 18 RegAddr: 0
New Opcode: 53 Length: 2 Data: Object/7 N: 7 PC: 3 OldOpLength: 2
Executing uInst: fjump:53
#MIR: (Label←FJump EUop←nop Raddr←Tos Tos'←Tos-1 NewTos←Tos' Rd2addr←Nil Condcode←D1#D2 NextInstA←Done
 NextInstB←DoJmp)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 145 #$Opcode 53 #NCurPc: 5
D1: Atm/3600 D2: Atm/3584 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 145 #$Opcode 145 #NCurPc: 5
D1: Int/1073741823 D2: -- Tos: 17 RegAddr: 0
New Opcode: 145 Length: 0 Data: Object/0 N: 3 PC: 5 OldOpLength: 0
Executing uInst: loadibuf:209
#MIR: (Label←LoadIBuf Cycle←R4 RD1addr←PcAddr W2addr←IBufD2PcD1 EUop←+16 Tag←Int 
Misc←ResetInitialRefill CondCode←NoFault NextInstA←Done NextInstB←IBufPageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010010 $Opcode: 145 #$Opcode 145 #NCurPc: 5
D1: Int/592 D2: Ptr-32/0 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010001 $Opcode: 145 #$Opcode 145 #NCurPc: 5
D1: Int/608 D2: Float/871219192 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 145 #$Opcode 145 #NCurPc: 5
D1: -- D2: XType/747145454 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 145 #$Opcode 145 #NCurPc: 5
D1: -- D2: Object/0 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 145 #$Opcode 145 #NCurPc: 5
D1: -- D2: Object/0 Tos: 17 RegAddr: 0
New Opcode: 145 Length: 5 Data: Int/3 N: 3 PC: 5 OldOpLength: 5
Executing uInst: intconst:81
#MIR: (Label←IntConst EUop←D1 Tag←Int RD1addr←IBufData Waddr←TOS' TOS'←TOS+1 NewTos←Tos' 
NextInstA←Done)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 50 #$Opcode 145 #NCurPc: 10
D1: Int/3 D2: Ptr-32/0 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 50 #$Opcode 50 #NCurPc: 10
D1: Int/3 D2: -- Tos: 18 RegAddr: 0
New Opcode: 50 Length: 2 Data: Object/5 N: 5 PC: 10 OldOpLength: 2
Executing uInst: dojmp:50
#MIR: (Label←DoJmp EUop←+ Tag←Int RD2addr←PC RD1addr←IBufData W2addr←PCD1 
Misc←Oplength=0&SetInitialRefill NextInstA←Dojmp1)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 145 #$Opcode 50 #NCurPc: 12
D1: Object/5 D2: Int/588 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 145 #$Opcode 50 #NCurPc: 12
D1: Int/593 D2: -- Tos: 18 RegAddr: 0
Executing uInst: dojmp1:193
#MIR: (Label←DoJmp1 NextInstA←Done)
****************** Errors ******************
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-6: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 201 #$Opcode 50 #NCurPc: 17
D1: Int/3 D2: Object/2049 Tos: 18 RegAddr: 0
****************** Errors ******************
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-6: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 201 #$Opcode 201 #NCurPc: 17
D1: Int/1073741823 D2: -- Tos: 18 RegAddr: 0
New Opcode: 201 Length: 0 Data: Object/0 N: 17 PC: 17 OldOpLength: 0
Executing uInst: loadibuf:209
#MIR: (Label←LoadIBuf Cycle←R4 RD1addr←PcAddr W2addr←IBufD2PcD1 EUop←+16 Tag←Int 
Misc←ResetInitialRefill CondCode←NoFault NextInstA←Done NextInstB←IBufPageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010010 $Opcode: 201 #$Opcode 201 #NCurPc: 17
D1: Int/592 D2: Object/2049 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010001 $Opcode: 201 #$Opcode 201 #NCurPc: 17
D1: Int/608 D2: Float/871219192 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 201 #$Opcode 201 #NCurPc: 17
D1: -- D2: XType/747145454 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 201 #$Opcode 201 #NCurPc: 17
D1: -- D2: Object/0 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 201 #$Opcode 201 #NCurPc: 17
D1: -- D2: Object/0 Tos: 18 RegAddr: 0
New Opcode: 201 Length: 1 Data: Object/0 N: 17 PC: 17 OldOpLength: 1
Executing uInst: vark:233
#MIR: (Label←Vark EUop←D1 Tag←D1 Raddr←0<4>/OpCode<4> Waddr←Tos' Tos'←Tos+1 NewTos←Tos' NextInstA←Done
)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 17 #$Opcode 201 #NCurPc: 18
D1: Int/17 D2: Int/2098241 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 17 #$Opcode 17 #NCurPc: 18
D1: Int/17 D2: -- Tos: 19 RegAddr: 0
New Opcode: 17 Length: 1 Data: Object/0 N: 33 PC: 18 OldOpLength: 1
Executing uInst: or:17
#MIR: (Label←Or EUop←Or Tag←Int Raddr←Tos RD2addr←Raddr-1 Waddr←Tos' Tos'←Tos-1 NewTos←Tos' 
CondCode←IntegerD1D2 CWrite NextInstA←Done NextInstB←Ufn-2)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 33 #$Opcode 17 #NCurPc: 19
D1: Int/17 D2: Int/3 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 33 #$Opcode 33 #NCurPc: 19
D1: Int/19 D2: -- Tos: 18 RegAddr: 0
New Opcode: 33 Length: 2 Data: Object/0 N: 0 PC: 19 OldOpLength: 2
Executing uInst: putptr:228
#MIR: (Label←Putptr EUop←D2 Tag←D2 Raddr←Tos RD2addr←Raddr-1 W2addr←MarD1 Condcode←PointerpD2 
NextInstB←Ufn-2d)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 60 #$Opcode 33 #NCurPc: 21
D1: Int/19 D2: Object/2049 Tos: 18 RegAddr: 0
****************** Errors ******************
#CONDA: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 60 #$Opcode 33 #NCurPc: 21
D1: Object/2049 D2: -- Tos: 18 RegAddr: 0
Executing uInst: LAB0034:229
#MIR: (EUop←+ Tag←D1 RD1addr←Mar RD2addr←MuxRdSel MuxRdSel←IBufN W2addr←MarD1)
****************** Errors ******************
D1-30: 1 ← 0
D1-11: 0 ← 1
D1-4: 1 ← 0
D1-1: 1 ← 0
VAD-11: 0 ← 1
VAD'-11: 1 ← 0
VAD'-4: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 60 #$Opcode 33 #NCurPc: 21
D1: Object/2049 D2: Object/0 Tos: 18 RegAddr: 0
****************** Errors ******************
D1-30: 1 ← 0
D1-11: 0 ← 1
D1-4: 1 ← 0
D1-1: 1 ← 0
VAD-11: 0 ← 1
VAD'-11: 1 ← 0
VAD'-4: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 60 #$Opcode 33 #NCurPc: 21
D1: Object/2049 D2: -- Tos: 18 RegAddr: 0
Executing uInst: LAB0035:109
#MIR: (Cycle←W1 Dswap Raddr←Tos Tos'←Tos-1 NewTos←Tos' CondCode←NoFault CWrite NextInstA←Done 
NextInstB←PageFault)
****************** Errors ******************
D1-30: 1 ← 0
D1-11: 0 ← 1
D1-4: 1 ← 0
D1-1: 1 ← 0
VAD-11: 0 ← 1
VAD'-11: 1 ← 0
VAD'-4: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 60 #$Opcode 33 #NCurPc: 21
D1: Object/2049 D2: Int/19 Tos: 18 RegAddr: 0
****************** Errors ******************
D1-30: 1 ← 0
D1-11: 0 ← 1
D1-4: 1 ← 0
D1-1: 1 ← 0
VAD-11: 0 ← 1
VAD'-11: 1 ← 0
VAD'-4: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 60 #$Opcode 60 #NCurPc: 21
D1: Int/1073741823 D2: -- Tos: 17 RegAddr: 0
New Opcode: 60 Length: 0 Data: Object/0 N: 124 PC: 21 OldOpLength: 0
Executing uInst: loadibuf:209
#MIR: (Label←LoadIBuf Cycle←R4 RD1addr←PcAddr W2addr←IBufD2PcD1 EUop←+16 Tag←Int 
Misc←ResetInitialRefill CondCode←NoFault NextInstA←Done NextInstB←IBufPageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010010 $Opcode: 60 #$Opcode 60 #NCurPc: 21
D1: Int/608 D2: Ptr-32/0 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010001 $Opcode: 60 #$Opcode 60 #NCurPc: 21
D1: Int/624 D2: Object/0 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 60 #$Opcode 60 #NCurPc: 21
D1: -- D2: Object/0 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 60 #$Opcode 60 #NCurPc: 21
D1: -- D2: Object/0 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 60 #$Opcode 60 #NCurPc: 21
D1: -- D2: Object/0 Tos: 17 RegAddr: 0
New Opcode: 60 Length: 1 Data: Object/0 N: 124 PC: 21 OldOpLength: 1
Executing uInst: reset-vmm:219
#MIR: (Label←Reset-Vmm Misc←Reset-Vmm NextInstA←Done)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 124 #$Opcode 60 #NCurPc: 22
D1: Object/2049 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-30: 1 ← 0
D1-11: 0 ← 1
D1-4: 1 ← 0
D1-1: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 124 #$Opcode 124 #NCurPc: 22
D1: Int/1073741823 D2: -- Tos: 17 RegAddr: 0
New Opcode: 124 Length: 1 Data: Object/0 N: 255 PC: 22 OldOpLength: 1
Executing uInst: retnp:220
#MIR: (Label←Retnp EUop←D1 Tag←Int Raddr←K K←StkHdr CondCode←TrapOnExit NextInstA←Ufn-0)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 255 #$Opcode 124 #NCurPc: 23
D1: Int/16 D2: -- Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 255 #$Opcode 124 #NCurPc: 23
D1: Int/16 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0065:139
#MIR: (EUop←D1 Tag←Int RCxt←Prev Raddr←K K←Pc W2Addr←PcD1 NewTopCxt←Prev 
Misc←Oplength=0&SetInitialRefill)
****************** Errors ******************
VAD-11: 0 ← 1
VAD'-11: 1 ← 0
VAD'-4: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 255 #$Opcode 124 #NCurPc: 23
D1: Int/34 D2: XType/1073741589 Tos: 17 RegAddr: 0
****************** Errors ******************
VAD-11: 0 ← 1
VAD'-11: 1 ← 0
VAD'-4: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 255 #$Opcode 124 #NCurPc: 23
D1: Int/34 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0066:140
#MIR: (Dswap Raddr←K K←StkHdr NewTos←D2 NextInstA←Done)
****************** Errors ******************
VAD-11: 0 ← 1
VAD'-11: 1 ← 0
VAD'-4: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 255 #$Opcode 124 #NCurPc: 2
D1: Int/34 D2: XType/1073741589 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-31: 1 ← 0
D1-29: 1 ← 0
D1-28: 1 ← 0
D1-27: 1 ← 0
D1-26: 1 ← 0
D1-25: 1 ← 0
D1-24: 1 ← 0
D1-23: 1 ← 0
D1-22: 1 ← 0
D1-21: 1 ← 0
D1-20: 1 ← 0
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-0: 1 ← 0
VAD-11: 0 ← 1
VAD'-11: 1 ← 0
VAD'-4: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 255 #$Opcode 255 #NCurPc: 2
D1: Int/1073741823 D2: -- Tos: 21 RegAddr: 0
New Opcode: 255 Length: 0 Data: Object/0 N: 255 PC: 2 OldOpLength: 0
Executing uInst: loadibuf:209
#MIR: (Label←LoadIBuf Cycle←R4 RD1addr←PcAddr W2addr←IBufD2PcD1 EUop←+16 Tag←Int 
Misc←ResetInitialRefill CondCode←NoFault NextInstA←Done NextInstB←IBufPageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010010 $Opcode: 255 #$Opcode 255 #NCurPc: 2
D1: Int/32 D2: Object/2098177 Tos: 21 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010001 $Opcode: 255 #$Opcode 255 #NCurPc: 2
D1: Int/48 D2: XType/987200381 Tos: 21 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 255 #$Opcode 255 #NCurPc: 2
D1: -- D2: Int/1072160763 Tos: 21 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 33 #$Opcode 255 #NCurPc: 2
D1: -- D2: XType/1054604287 Tos: 21 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 33 #$Opcode 33 #NCurPc: 2
D1: -- D2: XType/987200351 Tos: 21 RegAddr: 0
New Opcode: 33 Length: 2 Data: Object/64 N: 64 PC: 2 OldOpLength: 2
Executing uInst: putptr:33
#MIR: (Label←Putptr EUop←D2 Tag←D2 Raddr←Tos RD2addr←Raddr-1 W2addr←MarD1 Condcode←PointerpD2 
NextInstB←Ufn-2d)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 144 #$Opcode 33 #NCurPc: 4
D1: Int/7 D2: Object/2098177 Tos: 21 RegAddr: 0
****************** Errors ******************
D1-21: 1 ← 0
D1-10: 1 ← 0
D1-6: 1 ← 0
D1-2: 0 ← 1
D1-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 144 #$Opcode 33 #NCurPc: 4
D1: Object/2098177 D2: -- Tos: 21 RegAddr: 0
Executing uInst: LAB0034:229
#MIR: (EUop←+ Tag←D1 RD1addr←Mar RD2addr←MuxRdSel MuxRdSel←IBufN W2addr←MarD1)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 144 #$Opcode 33 #NCurPc: 4
D1: Object/2098177 D2: Object/64 Tos: 21 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 144 #$Opcode 33 #NCurPc: 4
D1: Object/2098241 D2: -- Tos: 21 RegAddr: 0
Executing uInst: LAB0035:109
#MIR: (Cycle←W1 Dswap Raddr←Tos Tos'←Tos-1 NewTos←Tos' CondCode←NoFault CWrite NextInstA←Done 
NextInstB←PageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 144 #$Opcode 33 #NCurPc: 4
D1: Object/2098177 D2: Int/7 Tos: 21 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 144 #$Opcode 33 #NCurPc: 4
D1: -- D2: Int/19 Tos: 21 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 144 #$Opcode 33 #NCurPc: 4
D1: Object/2098177 D2: Int/7 Tos: 21 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 144 #$Opcode 144 #NCurPc: 4
D1: Int/1073741823 D2: -- Tos: 20 RegAddr: 0
New Opcode: 144 Length: 0 Data: Object/0 N: 1 PC: 4 OldOpLength: 0
Executing uInst: loadibuf:209
#MIR: (Label←LoadIBuf Cycle←R4 RD1addr←PcAddr W2addr←IBufD2PcD1 EUop←+16 Tag←Int 
Misc←ResetInitialRefill CondCode←NoFault NextInstA←Done NextInstB←IBufPageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010010 $Opcode: 144 #$Opcode 144 #NCurPc: 4
D1: Int/48 D2: Int/6 Tos: 20 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010001 $Opcode: 144 #$Opcode 144 #NCurPc: 4
D1: Int/64 D2: XType/928513019 Tos: 20 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 144 #$Opcode 144 #NCurPc: 4
D1: -- D2: Float/143165568 Tos: 20 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 144 #$Opcode 144 #NCurPc: 4
D1: -- D2: Object/0 Tos: 20 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 144 #$Opcode 144 #NCurPc: 4
D1: -- D2: Object/0 Tos: 20 RegAddr: 0
New Opcode: 144 Length: 5 Data: Object/2099201 N: 1 PC: 4 OldOpLength: 5
Executing uInst: pconst:80
#MIR: (Label←PConst EUop←D2<2>Shl24/D1<30> Tag←D2<8:7> RD2addr←MuxRdSel MuxRdSel←K K←PtrTypeBits 
RD1addr←IBufData Waddr←TOS' TOS'←TOS+1 NewTos←Tos' NextInstA←Done)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 20 #$Opcode 144 #NCurPc: 9
D1: Object/2099201 D2: Object/0 Tos: 20 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 20 #$Opcode 20 #NCurPc: 9
D1: Object/2099201 D2: -- Tos: 21 RegAddr: 0
New Opcode: 20 Length: 1 Data: Object/0 N: 32 PC: 9 OldOpLength: 1
Executing uInst: copy:20
#MIR: (Label←Copy EUop←D1 Tag←D1 Raddr←Tos Waddr←Tos' Tos'←Tos+1 NewTos←Tos' NextInstA←Done)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 32 #$Opcode 20 #NCurPc: 10
D1: Object/2099201 D2: Object/2098177 Tos: 21 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 32 #$Opcode 32 #NCurPc: 10
D1: Object/2099201 D2: -- Tos: 22 RegAddr: 0
New Opcode: 32 Length: 2 Data: Object/64 N: 64 PC: 10 OldOpLength: 2
Executing uInst: getptr:32
#MIR: (Label←Getptr EUop←+ Tag←D2 Dswap Raddr←Tos RD1addr←IBufData W2addr←MarD1 Condcode←PointerpD2 
NextInstB←Ufn-1d)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 26 #$Opcode 32 #NCurPc: 12
D1: Object/64 D2: Object/2099201 Tos: 22 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 26 #$Opcode 32 #NCurPc: 12
D1: Object/2099265 D2: -- Tos: 22 RegAddr: 0
Executing uInst: LAB0033:65
#MIR: (Cycle←R1 Waddr←Tos CondCode←NoFault Cwrite NextInstA←Done NextInstB←PageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 26 #$Opcode 32 #NCurPc: 12
D1: Object/2099201 D2: Object/2099201 Tos: 22 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 26 #$Opcode 32 #NCurPc: 12
D1: -- D2: Int/16 Tos: 22 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 26 #$Opcode 32 #NCurPc: 12
D1: Object/2099201 D2: Object/2099201 Tos: 22 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 26 #$Opcode 32 #NCurPc: 12
D1: -- D2: -- Tos: 22 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 26 #$Opcode 32 #NCurPc: 12
D1: -- D2: -- Tos: 22 RegAddr: 0
Executing uInst: pagefault:212
#MIR: (Label←PageFault EUop←D1 Tag←Int RD1addr←Mar Waddr←Tos' Tos'←Tos+1 NewTos←Tos' NewArg←K K←1 
Misc←OpLength=0 CondCode←FramesAvail Cwrite NextInstB←DumpFrame)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 26 #$Opcode 32 #NCurPc: 12
D1: Object/2099265 D2: Object/2099201 Tos: 22 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 26 #$Opcode 32 #NCurPc: 12
D1: Int/2099265 D2: -- Tos: 23 RegAddr: 0
Executing uInst: LAB0072:146
#MIR: (EUop←D1 Tag←D1 Raddr←K K←PFCode RCxt←K W2addr←MarD1 NextInstA←Fn1)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 32 #$Opcode 32 #NCurPc: 10
D1: Code/100663424 D2: -- Tos: 23 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 32 #$Opcode 32 #NCurPc: 10
D1: Code/100663424 D2: -- Tos: 23 RegAddr: 0
Executing uInst: fn1:197
#MIR: (Label←Fn1 EUop←+4 Tag←D1 RD1addr←Mar W2addr←MarD1 NewArg2←Arg NewArg←K K←StkHdr CondCode←CCodeP
 NextInstB←Fn5)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 32 #$Opcode 32 #NCurPc: 10
D1: Code/100663424 D2: Object/2099201 Tos: 23 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 32 #$Opcode 32 #NCurPc: 10
D1: Code/100663428 D2: -- Tos: 23 RegAddr: 0
Executing uInst: LAB0041:115
#MIR: (Cycle←R4 WCxt←Next Waddr←Arg<6>/QW<2> EUop←+4 Tag←D1 RD1addr←Mar W2addr←MarD1 CondCode←NoFault 
NextInstB←PageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010010 $Opcode: 32 #$Opcode 32 #NCurPc: 10
D1: Code/100663428 D2: Object/2099201 Tos: 23 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010001 $Opcode: 32 #$Opcode 32 #NCurPc: 10
D1: Code/100663432 D2: Int/16 Tos: 23 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 32 #$Opcode 32 #NCurPc: 10
D1: -- D2: Int/0 Tos: 23 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 32 #$Opcode 32 #NCurPc: 10
D1: -- D2: Code/100663424 Tos: 23 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 32 #$Opcode 32 #NCurPc: 10
D1: -- D2: Code/100663424 Tos: 23 RegAddr: 0
Executing uInst: LAB0042:116
#MIR: (EUop←D2 Tag←D2 RD2addr←Unbound Waddr←K K←PVar WCxt←Next Misc←WriteOctal NewArg←Arg2)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 32 #$Opcode 32 #NCurPc: 10
D1: Int/2099265 D2: Ptr-32/0 Tos: 23 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 32 #$Opcode 32 #NCurPc: 10
D1: Ptr-32/0 D2: -- Tos: 23 RegAddr: 0
Executing uInst: fn2:198
#MIR: (Label←Fn2 EUop←D2 Tag←D2 RD2addr←Nil Waddr←K K←IVar WCxt←Next Misc←WriteOctal)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 32 #$Opcode 32 #NCurPc: 10
D1: Int/2099265 D2: Atm/3584 Tos: 23 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 32 #$Opcode 32 #NCurPc: 10
D1: Atm/3584 D2: -- Tos: 23 RegAddr: 0
Executing uInst: LAB0043:117
#MIR: (EUop←D2 Tag←Int RD2addr←PC Waddr←K K←Pc Misc←Oplength=0&SetInitialRefill)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 32 #$Opcode 32 #NCurPc: 10
D1: Int/2099265 D2: Int/42 Tos: 23 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 32 #$Opcode 32 #NCurPc: 10
D1: Int/42 D2: -- Tos: 23 RegAddr: 0
Executing uInst: LAB0044:118
#MIR: (EUop←+ Tag←Int RD1addr←Mar RD2addr←MuxRdSel MuxRdSel←Arg W2Addr←MarD1)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 32 #$Opcode 32 #NCurPc: 10
D1: Code/100663432 D2: Object/1 Tos: 23 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 32 #$Opcode 32 #NCurPc: 10
D1: Int/100663433 D2: -- Tos: 23 RegAddr: 0
Executing uInst: LAB0045:119
#MIR: (Cycle←R1 Waddr←K WCxt←Next K←Pc)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 32 #$Opcode 32 #NCurPc: 10
D1: Int/2099265 D2: Object/2099201 Tos: 23 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 32 #$Opcode 32 #NCurPc: 10
D1: Int/1073741823 D2: Int/560 Tos: 23 RegAddr: 0
Executing uInst: LAB0046:120
#MIR: (EUop←D1 Tag←Int Raddr←K RCxt←Next K←PC W2addr←PCD1)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 32 #$Opcode 32 #NCurPc: 10
D1: Int/560 D2: Int/16 Tos: 23 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 32 #$Opcode 32 #NCurPc: 10
D1: Int/560 D2: -- Tos: 23 RegAddr: 0
Executing uInst: LAB0047:121
#MIR: (EUop←D2 Tag←Int RD2addr←MuxRdSel MuxRdSel←K K←Ivar NewArg2←K W2addr←MarD1 NewArg←Arg' 
Arg'←Arg-1 CondCode←Arg#0 NextInstB←Fn3)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 112 #$Opcode 32 #NCurPc: 16
D1: Int/2099265 D2: Object/8 Tos: 23 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 112 #$Opcode 32 #NCurPc: 16
D1: Int/8 D2: -- Tos: 23 RegAddr: 0
Executing uInst: LAB0048:122
#MIR: (EUop←+ Tag←Int RD1addr←Mar RD2addr←MuxRdSel MuxRdSel←Arg W2addr←Tmp1D1)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 112 #$Opcode 32 #NCurPc: 16
D1: Int/8 D2: Object/0 Tos: 23 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 112 #$Opcode 32 #NCurPc: 16
D1: Int/8 D2: -- Tos: 23 RegAddr: 0
Executing uInst: LAB0049:123
#MIR: (RD2addr←Tmp1 NewArg←D2)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 112 #$Opcode 32 #NCurPc: 16
D1: Int/2099265 D2: Int/8 Tos: 23 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 112 #$Opcode 32 #NCurPc: 16
D1: Int/1073741823 D2: -- Tos: 23 RegAddr: 0
Executing uInst: LAB0050:124
#MIR: (EUop←D1 Tag←D1 Raddr←Tos WCxt←Next Waddr←Arg NewTos←Tos' Tos'←Tos-1 NewArg←Arg' Arg'←Arg-1 
CondCode←Arg=Arg2 NextInstB←Rpt)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 112 #$Opcode 32 #NCurPc: 16
D1: Int/2099265 D2: Object/2099201 Tos: 23 RegAddr: 0
****************** Errors ******************
#CONDA: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 112 #$Opcode 32 #NCurPc: 16
D1: Int/2099265 D2: -- Tos: 22 RegAddr: 0
Executing uInst: fn3:199
#MIR: (Label←Fn3 EUop←D1<24>/D2<8> Tag←D1 RD2addr←MuxRdSel MuxRdSel←Tos Raddr←K Waddr←K K←StkHdr)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 112 #$Opcode 32 #NCurPc: 16
D1: XType/1073741589 D2: Object/22 Tos: 22 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 112 #$Opcode 32 #NCurPc: 16
D1: XType/1073741590 D2: -- Tos: 22 RegAddr: 0
Executing uInst: LAB0051:125
#MIR: (EUop←D2 Tag←D2 Dswap Raddr←K K←StkHdr RCxt←Next WCxt←Next NewTos←D2 NewTopCxt←Next 
NextInstA←Done)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 112 #$Opcode 32 #NCurPc: 16
D1: -- D2: Int/16 Tos: 22 RegAddr: 0
****************** Errors ******************
D1-31: 0 ← 1
D1-29: 0 ← 1
D1-28: 0 ← 1
D1-27: 0 ← 1
D1-26: 0 ← 1
D1-25: 0 ← 1
D1-24: 0 ← 1
D1-23: 0 ← 1
D1-22: 0 ← 1
D1-21: 0 ← 1
D1-20: 0 ← 1
D1-19: 0 ← 1
D1-18: 0 ← 1
D1-17: 0 ← 1
D1-16: 0 ← 1
D1-15: 0 ← 1
D1-14: 0 ← 1
D1-13: 0 ← 1
D1-12: 0 ← 1
D1-11: 0 ← 1
D1-10: 0 ← 1
D1-9: 0 ← 1
D1-8: 0 ← 1
D1-7: 0 ← 1
D1-6: 0 ← 1
D1-5: 0 ← 1
D1-3: 0 ← 1
D1-2: 0 ← 1
D1-1: 0 ← 1
D1-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 112 #$Opcode 112 #NCurPc: 16
D1: Int/16 D2: -- Tos: 16 RegAddr: 0
New Opcode: 112 Length: 0 Data: Object/0 N: 5 PC: 16 OldOpLength: 0
Executing uInst: loadibuf:209
#MIR: (Label←LoadIBuf Cycle←R4 RD1addr←PcAddr W2addr←IBufD2PcD1 EUop←+16 Tag←Int 
Misc←ResetInitialRefill CondCode←NoFault NextInstA←Done NextInstB←IBufPageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010010 $Opcode: 112 #$Opcode 112 #NCurPc: 16
D1: Int/560 D2: Atm/3584 Tos: 16 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010001 $Opcode: 112 #$Opcode 112 #NCurPc: 16
D1: Int/576 D2: List/80235720 Tos: 16 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 112 #$Opcode 112 #NCurPc: 16
D1: -- D2: Int/862283366 Tos: 16 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 200 #$Opcode 112 #NCurPc: 16
D1: -- D2: XType/1069448763 Tos: 16 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 200 #$Opcode 200 #NCurPc: 16
D1: -- D2: XType/526176237 Tos: 16 RegAddr: 0
New Opcode: 200 Length: 1 Data: Object/0 N: 145 PC: 16 OldOpLength: 1
Executing uInst: vark:233
#MIR: (Label←Vark EUop←D1 Tag←D1 Raddr←0<4>/OpCode<4> Waddr←Tos' Tos'←Tos+1 NewTos←Tos' NextInstA←Done
)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 145 #$Opcode 200 #NCurPc: 17
D1: Int/2099265 D2: -- Tos: 16 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 145 #$Opcode 145 #NCurPc: 17
D1: Int/2099265 D2: -- Tos: 17 RegAddr: 0
New Opcode: 145 Length: 5 Data: Int/16777215 N: 255 PC: 17 OldOpLength: 5
Executing uInst: intconst:81
#MIR: (Label←IntConst EUop←D1 Tag←Int RD1addr←IBufData Waddr←TOS' TOS'←TOS+1 NewTos←Tos' 
NextInstA←Done)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 16 #$Opcode 145 #NCurPc: 22
D1: Int/16777215 D2: Ptr-32/0 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 16 #$Opcode 16 #NCurPc: 22
D1: Int/16777215 D2: -- Tos: 18 RegAddr: 0
New Opcode: 16 Length: 0 Data: Object/0 N: 47 PC: 22 OldOpLength: 0
Executing uInst: loadibuf:209
#MIR: (Label←LoadIBuf Cycle←R4 RD1addr←PcAddr W2addr←IBufD2PcD1 EUop←+16 Tag←Int 
Misc←ResetInitialRefill CondCode←NoFault NextInstA←Done NextInstB←IBufPageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010010 $Opcode: 16 #$Opcode 16 #NCurPc: 22
D1: Int/576 D2: Int/2099265 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010001 $Opcode: 16 #$Opcode 16 #NCurPc: 22
D1: Int/592 D2: XType/1071816350 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 16 #$Opcode 16 #NCurPc: 22
D1: -- D2: Float/1073477457 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 16 #$Opcode 16 #NCurPc: 22
D1: -- D2: XType/1004404446 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 16 #$Opcode 16 #NCurPc: 22
D1: -- D2: Int/1073217523 Tos: 18 RegAddr: 0
New Opcode: 16 Length: 1 Data: Object/0 N: 47 PC: 22 OldOpLength: 1
Executing uInst: and:16
#MIR: (Label←And EUop←And Tag←Int Raddr←Tos RD2addr←Raddr-1 Waddr←Tos' Tos'←Tos-1 NewTos←Tos' 
CondCode←IntegerD1D2 CWrite NextInstA←Done NextInstB←Ufn-2)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 47 #$Opcode 16 #NCurPc: 23
D1: Int/16777215 D2: Int/2099265 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 47 #$Opcode 47 #NCurPc: 23
D1: Int/2099265 D2: -- Tos: 17 RegAddr: 0
New Opcode: 47 Length: 2 Data: Object/10 N: 10 PC: 23 OldOpLength: 2
Executing uInst: lrsh.n:228
#MIR: (Label←Lrsh.N EUop←D1 Tag←Int Raddr←Tos W2addr←MarD1 NewArg←IBufN CondCode←Integerp 
NextInstB←Ufn-1d)
****************** Errors ******************
D1-23: 1 ← 0
D1-22: 1 ← 0
D1-20: 1 ← 0
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/2099265 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-23: 1 ← 0
D1-22: 1 ← 0
D1-20: 1 ← 0
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/2099265 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0031:105
#MIR: (Arg'←Arg-1 NewArg←Arg' CondCode←Arg=0 NextInstA←Done)
****************** Errors ******************
D1-23: 1 ← 0
D1-22: 1 ← 0
D1-20: 1 ← 0
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/2099265 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-23: 1 ← 0
D1-22: 1 ← 0
D1-20: 1 ← 0
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/1073741823 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/2099265 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-23: 1 ← 0
D1-22: 1 ← 0
D1-20: 1 ← 0
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/1049632 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-22: 1 ← 0
D1-21: 1 ← 0
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/1049632 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-22: 1 ← 0
D1-21: 1 ← 0
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/524816 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-21: 1 ← 0
D1-20: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/524816 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-21: 1 ← 0
D1-20: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/262408 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-20: 1 ← 0
D1-19: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/262408 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-20: 1 ← 0
D1-19: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/131204 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/131204 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/65602 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/65602 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/32801 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/32801 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/16400 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/16400 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/8200 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/8200 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/4100 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/4100 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 35 #NCurPc: 25
D1: Int/2050 D2: -- Tos: 17 RegAddr: 0
New Opcode: 35 Length: 2 Data: Object/0 N: 0 PC: 25 OldOpLength: 2
Executing uInst: settype:35
#MIR: (Label←SetType EUop←D2<2>Shl24/D1<30> Tag←D2<8:7> Raddr←Tos RD2addr←MuxRdSel MuxRdSel←IBufN 
Waddr←Tos NextInstA←Done)
****************** Errors ******************
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 20 #$Opcode 35 #NCurPc: 27
D1: Int/2050 D2: Object/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 20 #$Opcode 20 #NCurPc: 27
D1: Object/2050 D2: -- Tos: 17 RegAddr: 0
New Opcode: 20 Length: 1 Data: Object/0 N: 32 PC: 27 OldOpLength: 1
Executing uInst: copy:20
#MIR: (Label←Copy EUop←D1 Tag←D1 Raddr←Tos Waddr←Tos' Tos'←Tos+1 NewTos←Tos' NextInstA←Done)
****************** Errors ******************
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 32 #$Opcode 20 #NCurPc: 28
D1: Object/2050 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 32 #$Opcode 32 #NCurPc: 28
D1: Object/2050 D2: -- Tos: 18 RegAddr: 0
New Opcode: 32 Length: 2 Data: Object/0 N: 0 PC: 28 OldOpLength: 2
Executing uInst: getptr:32
#MIR: (Label←Getptr EUop←+ Tag←D2 Dswap Raddr←Tos RD1addr←IBufData W2addr←MarD1 Condcode←PointerpD2 
NextInstB←Ufn-1d)
****************** Errors ******************
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 185 #$Opcode 32 #NCurPc: 30
D1: Object/0 D2: Object/2050 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 185 #$Opcode 32 #NCurPc: 30
D1: Object/2050 D2: -- Tos: 18 RegAddr: 0
Executing uInst: LAB0033:65
#MIR: (Cycle←R1 Waddr←Tos CondCode←NoFault Cwrite NextInstA←Done NextInstB←PageFault)
****************** Errors ******************
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-0: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-6: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 185 #$Opcode 32 #NCurPc: 30
D1: Object/2050 D2: Object/2050 Tos: 18 RegAddr: 0
****************** Errors ******************
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-0: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-6: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 185 #$Opcode 185 #NCurPc: 30
D1: Int/1073741823 D2: Int/16 Tos: 18 RegAddr: 0
New Opcode: 185 Length: 1 Data: Object/0 N: 26 PC: 30 OldOpLength: 1
Executing uInst: vark←:234
#MIR: (Label←Vark← EUop←D1 Tag←D1 Raddr←Tos Waddr←0<4>/OpCode<4> NextInstA←Done)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 26 #$Opcode 185 #NCurPc: 31
D1: Int/16 D2: Object/2050 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 26 #$Opcode 26 #NCurPc: 31
D1: Int/16 D2: -- Tos: 18 RegAddr: 0
New Opcode: 26 Length: 1 Data: Object/0 N: 16 PC: 31 OldOpLength: 1
Executing uInst: '1:26
#MIR: (Label←'1 EUop←D2 Tag←Int RD2addr←MuxRdSel MuxRdSel←K K←1 Waddr←Tos' Tos'←Tos+1 NewTos←Tos' 
NextInstA←Done)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 16 #$Opcode 26 #NCurPc: 0
D1: Int/16 D2: Object/1 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 16 #$Opcode 16 #NCurPc: 0
D1: Int/1 D2: -- Tos: 19 RegAddr: 0
New Opcode: 16 Length: 1 Data: Object/0 N: 26 PC: 0 OldOpLength: 1
Executing uInst: and:16
#MIR: (Label←And EUop←And Tag←Int Raddr←Tos RD2addr←Raddr-1 Waddr←Tos' Tos'←Tos-1 NewTos←Tos' 
CondCode←IntegerD1D2 CWrite NextInstA←Done NextInstB←Ufn-2)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 26 #$Opcode 16 #NCurPc: 1
D1: Int/1 D2: Int/16 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 26 #$Opcode 26 #NCurPc: 1
D1: Int/0 D2: -- Tos: 18 RegAddr: 0
New Opcode: 26 Length: 1 Data: Object/0 N: 10 PC: 1 OldOpLength: 1
Executing uInst: '1:228
#MIR: (Label←'1 EUop←D2 Tag←Int RD2addr←MuxRdSel MuxRdSel←K K←1 Waddr←Tos' Tos'←Tos+1 NewTos←Tos' 
NextInstA←Done)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 10 #$Opcode 26 #NCurPc: 2
D1: Int/0 D2: Object/1 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 10 #$Opcode 10 #NCurPc: 2
D1: Int/1 D2: -- Tos: 19 RegAddr: 0
New Opcode: 10 Length: 1 Data: Object/0 N: 53 PC: 2 OldOpLength: 1
Executing uInst: eq:10
#MIR: (Label←Eq Raddr←Tos RD2addr←Raddr-1 Tos'←Tos-1 NewTos←Tos' CondCode←D1=D2 NextInstA←SetT 
NextInstB←SetNil)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 53 #$Opcode 10 #NCurPc: 3
D1: Int/1 D2: Int/0 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 53 #$Opcode 10 #NCurPc: 3
D1: Int/1073741823 D2: -- Tos: 18 RegAddr: 0
Executing uInst: setnil:222
#MIR: (Label←SetNil EUop←D2 Tag←D2 RD2addr←Nil Waddr←Tos NextInstA←Done)
****************** Errors ******************
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-6: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 53 #$Opcode 10 #NCurPc: 3
D1: Int/0 D2: Atm/3584 Tos: 18 RegAddr: 0
****************** Errors ******************
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-6: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 53 #$Opcode 53 #NCurPc: 3
D1: Atm/3584 D2: -- Tos: 18 RegAddr: 0
New Opcode: 53 Length: 2 Data: Object/7 N: 7 PC: 3 OldOpLength: 2
Executing uInst: fjump:53
#MIR: (Label←FJump EUop←nop Raddr←Tos Tos'←Tos-1 NewTos←Tos' Rd2addr←Nil Condcode←D1#D2 NextInstA←Done
 NextInstB←DoJmp)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 145 #$Opcode 53 #NCurPc: 5
D1: Atm/3584 D2: Atm/3584 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 145 #$Opcode 53 #NCurPc: 5
D1: Int/1073741823 D2: -- Tos: 17 RegAddr: 0
Executing uInst: dojmp:209
#MIR: (Label←DoJmp EUop←+ Tag←Int RD2addr←PC RD1addr←IBufData W2addr←PCD1 
Misc←Oplength=0&SetInitialRefill NextInstA←Dojmp1)
****************** Errors ******************
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-6: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 145 #$Opcode 53 #NCurPc: 5
D1: Object/7 D2: Int/581 Tos: 17 RegAddr: 0
****************** Errors ******************
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-6: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 145 #$Opcode 53 #NCurPc: 5
D1: Int/588 D2: -- Tos: 17 RegAddr: 0
Executing uInst: dojmp1:193
#MIR: (Label←DoJmp1 NextInstA←Done)
****************** Errors ******************
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-6: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 145 #$Opcode 53 #NCurPc: 12
D1: Object/2050 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-30: 1 ← 0
D1-11: 0 ← 1
D1-1: 0 ← 1
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-6: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 145 #$Opcode 145 #NCurPc: 12
D1: Int/1073741823 D2: -- Tos: 17 RegAddr: 0
New Opcode: 145 Length: 0 Data: Object/0 N: 1 PC: 12 OldOpLength: 0
Executing uInst: loadibuf:209
#MIR: (Label←LoadIBuf Cycle←R4 RD1addr←PcAddr W2addr←IBufD2PcD1 EUop←+16 Tag←Int 
Misc←ResetInitialRefill CondCode←NoFault NextInstA←Done NextInstB←IBufPageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010010 $Opcode: 145 #$Opcode 145 #NCurPc: 12
D1: Int/576 D2: Ptr-32/0 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010001 $Opcode: 145 #$Opcode 145 #NCurPc: 12
D1: Int/592 D2: XType/1071816350 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 145 #$Opcode 145 #NCurPc: 12
D1: -- D2: Float/1073477457 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 145 #$Opcode 145 #NCurPc: 12
D1: -- D2: XType/1004404446 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 145 #$Opcode 145 #NCurPc: 12
D1: -- D2: Int/1073217523 Tos: 17 RegAddr: 0
New Opcode: 145 Length: 0 Data: Object/0 N: 1 PC: 12 OldOpLength: 0
Executing uInst: loadibuf:209
#MIR: (Label←LoadIBuf Cycle←R4 RD1addr←PcAddr W2addr←IBufD2PcD1 EUop←+16 Tag←Int 
Misc←ResetInitialRefill CondCode←NoFault NextInstA←Done NextInstB←IBufPageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010010 $Opcode: 145 #$Opcode 145 #NCurPc: 12
D1: Int/592 D2: Ptr-32/0 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010001 $Opcode: 145 #$Opcode 145 #NCurPc: 12
D1: Int/608 D2: Float/871219192 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 145 #$Opcode 145 #NCurPc: 12
D1: -- D2: XType/747145454 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 145 #$Opcode 145 #NCurPc: 12
D1: -- D2: Object/0 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 145 #$Opcode 145 #NCurPc: 12
D1: -- D2: Object/0 Tos: 17 RegAddr: 0
New Opcode: 145 Length: 5 Data: Int/1 N: 1 PC: 12 OldOpLength: 5
Executing uInst: intconst:81
#MIR: (Label←IntConst EUop←D1 Tag←Int RD1addr←IBufData Waddr←TOS' TOS'←TOS+1 NewTos←Tos' 
NextInstA←Done)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 201 #$Opcode 145 #NCurPc: 17
D1: Int/1 D2: Ptr-32/0 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 201 #$Opcode 201 #NCurPc: 17
D1: Int/1 D2: -- Tos: 18 RegAddr: 0
New Opcode: 201 Length: 1 Data: Object/0 N: 17 PC: 17 OldOpLength: 1
Executing uInst: vark:233
#MIR: (Label←Vark EUop←D1 Tag←D1 Raddr←0<4>/OpCode<4> Waddr←Tos' Tos'←Tos+1 NewTos←Tos' NextInstA←Done
)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 17 #$Opcode 201 #NCurPc: 18
D1: Int/16 D2: Int/2099265 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 17 #$Opcode 17 #NCurPc: 18
D1: Int/16 D2: -- Tos: 19 RegAddr: 0
New Opcode: 17 Length: 1 Data: Object/0 N: 33 PC: 18 OldOpLength: 1
Executing uInst: or:17
#MIR: (Label←Or EUop←Or Tag←Int Raddr←Tos RD2addr←Raddr-1 Waddr←Tos' Tos'←Tos-1 NewTos←Tos' 
CondCode←IntegerD1D2 CWrite NextInstA←Done NextInstB←Ufn-2)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 33 #$Opcode 17 #NCurPc: 19
D1: Int/16 D2: Int/1 Tos: 19 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 33 #$Opcode 33 #NCurPc: 19
D1: Int/17 D2: -- Tos: 18 RegAddr: 0
New Opcode: 33 Length: 2 Data: Object/0 N: 0 PC: 19 OldOpLength: 2
Executing uInst: putptr:228
#MIR: (Label←Putptr EUop←D2 Tag←D2 Raddr←Tos RD2addr←Raddr-1 W2addr←MarD1 Condcode←PointerpD2 
NextInstB←Ufn-2d)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 60 #$Opcode 33 #NCurPc: 21
D1: Int/17 D2: Object/2050 Tos: 18 RegAddr: 0
****************** Errors ******************
#CONDA: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 60 #$Opcode 33 #NCurPc: 21
D1: Object/2050 D2: -- Tos: 18 RegAddr: 0
Executing uInst: LAB0034:229
#MIR: (EUop←+ Tag←D1 RD1addr←Mar RD2addr←MuxRdSel MuxRdSel←IBufN W2addr←MarD1)
****************** Errors ******************
D1-30: 1 ← 0
D1-11: 0 ← 1
D1-4: 1 ← 0
D1-1: 0 ← 1
D1-0: 1 ← 0
VAD-11: 0 ← 1
VAD'-11: 1 ← 0
VAD'-4: 0 ← 1
VAD'-1: 1 ← 0
VAD'-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 60 #$Opcode 33 #NCurPc: 21
D1: Object/2050 D2: Object/0 Tos: 18 RegAddr: 0
****************** Errors ******************
D1-30: 1 ← 0
D1-11: 0 ← 1
D1-4: 1 ← 0
D1-1: 0 ← 1
D1-0: 1 ← 0
VAD-11: 0 ← 1
VAD'-11: 1 ← 0
VAD'-4: 0 ← 1
VAD'-1: 1 ← 0
VAD'-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 60 #$Opcode 33 #NCurPc: 21
D1: Object/2050 D2: -- Tos: 18 RegAddr: 0
Executing uInst: LAB0035:109
#MIR: (Cycle←W1 Dswap Raddr←Tos Tos'←Tos-1 NewTos←Tos' CondCode←NoFault CWrite NextInstA←Done 
NextInstB←PageFault)
****************** Errors ******************
D1-30: 1 ← 0
D1-11: 0 ← 1
D1-4: 1 ← 0
D1-1: 0 ← 1
D1-0: 1 ← 0
VAD-11: 0 ← 1
VAD'-11: 1 ← 0
VAD'-4: 0 ← 1
VAD'-1: 1 ← 0
VAD'-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 60 #$Opcode 33 #NCurPc: 21
D1: Object/2050 D2: Int/17 Tos: 18 RegAddr: 0
****************** Errors ******************
D1-30: 1 ← 0
D1-11: 0 ← 1
D1-4: 1 ← 0
D1-1: 0 ← 1
D1-0: 1 ← 0
VAD-11: 0 ← 1
VAD'-11: 1 ← 0
VAD'-4: 0 ← 1
VAD'-1: 1 ← 0
VAD'-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 60 #$Opcode 60 #NCurPc: 21
D1: Int/1073741823 D2: -- Tos: 17 RegAddr: 0
New Opcode: 60 Length: 0 Data: Object/0 N: 124 PC: 21 OldOpLength: 0
Executing uInst: loadibuf:209
#MIR: (Label←LoadIBuf Cycle←R4 RD1addr←PcAddr W2addr←IBufD2PcD1 EUop←+16 Tag←Int 
Misc←ResetInitialRefill CondCode←NoFault NextInstA←Done NextInstB←IBufPageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010010 $Opcode: 60 #$Opcode 60 #NCurPc: 21
D1: Int/608 D2: Ptr-32/0 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010001 $Opcode: 60 #$Opcode 60 #NCurPc: 21
D1: Int/624 D2: Object/0 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 60 #$Opcode 60 #NCurPc: 21
D1: -- D2: Object/0 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 60 #$Opcode 60 #NCurPc: 21
D1: -- D2: Object/0 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 60 #$Opcode 60 #NCurPc: 21
D1: -- D2: Object/0 Tos: 17 RegAddr: 0
New Opcode: 60 Length: 1 Data: Object/0 N: 124 PC: 21 OldOpLength: 1
Executing uInst: reset-vmm:219
#MIR: (Label←Reset-Vmm Misc←Reset-Vmm NextInstA←Done)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 124 #$Opcode 60 #NCurPc: 22
D1: Object/2050 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-30: 1 ← 0
D1-11: 0 ← 1
D1-4: 1 ← 0
D1-1: 0 ← 1
D1-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 124 #$Opcode 124 #NCurPc: 22
D1: Int/1073741823 D2: -- Tos: 17 RegAddr: 0
New Opcode: 124 Length: 1 Data: Object/0 N: 255 PC: 22 OldOpLength: 1
Executing uInst: retnp:220
#MIR: (Label←Retnp EUop←D1 Tag←Int Raddr←K K←StkHdr CondCode←TrapOnExit NextInstA←Ufn-0)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 255 #$Opcode 124 #NCurPc: 23
D1: Int/16 D2: -- Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 255 #$Opcode 124 #NCurPc: 23
D1: Int/16 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0065:139
#MIR: (EUop←D1 Tag←Int RCxt←Prev Raddr←K K←Pc W2Addr←PcD1 NewTopCxt←Prev 
Misc←Oplength=0&SetInitialRefill)
****************** Errors ******************
VAD-11: 0 ← 1
VAD'-11: 1 ← 0
VAD'-4: 0 ← 1
VAD'-1: 1 ← 0
VAD'-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 255 #$Opcode 124 #NCurPc: 23
D1: Int/42 D2: XType/1073741590 Tos: 17 RegAddr: 0
****************** Errors ******************
VAD-11: 0 ← 1
VAD'-11: 1 ← 0
VAD'-4: 0 ← 1
VAD'-1: 1 ← 0
VAD'-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 255 #$Opcode 124 #NCurPc: 23
D1: Int/42 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0066:140
#MIR: (Dswap Raddr←K K←StkHdr NewTos←D2 NextInstA←Done)
****************** Errors ******************
VAD-11: 0 ← 1
VAD'-11: 1 ← 0
VAD'-4: 0 ← 1
VAD'-1: 1 ← 0
VAD'-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 255 #$Opcode 124 #NCurPc: 10
D1: Int/42 D2: XType/1073741590 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-31: 1 ← 0
D1-29: 1 ← 0
D1-28: 1 ← 0
D1-27: 1 ← 0
D1-26: 1 ← 0
D1-25: 1 ← 0
D1-24: 1 ← 0
D1-23: 1 ← 0
D1-22: 1 ← 0
D1-21: 1 ← 0
D1-20: 1 ← 0
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-4: 1 ← 0
D1-2: 1 ← 0
D1-0: 1 ← 0
VAD-11: 0 ← 1
VAD'-11: 1 ← 0
VAD'-4: 0 ← 1
VAD'-1: 1 ← 0
VAD'-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 255 #$Opcode 255 #NCurPc: 10
D1: Int/1073741823 D2: -- Tos: 22 RegAddr: 0
New Opcode: 255 Length: 0 Data: Object/0 N: 255 PC: 10 OldOpLength: 0
Executing uInst: loadibuf:209
#MIR: (Label←LoadIBuf Cycle←R4 RD1addr←PcAddr W2addr←IBufD2PcD1 EUop←+16 Tag←Int 
Misc←ResetInitialRefill CondCode←NoFault NextInstA←Done NextInstB←IBufPageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010010 $Opcode: 255 #$Opcode 255 #NCurPc: 10
D1: Int/32 D2: Object/2099201 Tos: 22 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010001 $Opcode: 255 #$Opcode 255 #NCurPc: 10
D1: Int/48 D2: XType/987200381 Tos: 22 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 255 #$Opcode 255 #NCurPc: 10
D1: -- D2: Int/1072160763 Tos: 22 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 255 #$Opcode 255 #NCurPc: 10
D1: -- D2: XType/1054604287 Tos: 22 RegAddr: 0
****************** Errors ******************
#OPCODE-5: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 255 #$Opcode 255 #NCurPc: 10
D1: -- D2: XType/987200351 Tos: 22 RegAddr: 0
New Opcode: 255 Length: 0 Data: Object/0 N: 255 PC: 10 OldOpLength: 0
Executing uInst: loadibuf:209
#MIR: (Label←LoadIBuf Cycle←R4 RD1addr←PcAddr W2addr←IBufD2PcD1 EUop←+16 Tag←Int 
Misc←ResetInitialRefill CondCode←NoFault NextInstA←Done NextInstB←IBufPageFault)
****************** Errors ******************
#IBUFN-7: 0 ← 1
#IBUFN-6: 0 ← 1
#IBUFN-5: 0 ← 1
#IBUFN-4: 0 ← 1
#IBUFN-3: 0 ← 1
#IBUFN-2: 0 ← 1
#IBUFN-1: 0 ← 1
#IBUFN-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010010 $Opcode: 255 #$Opcode 255 #NCurPc: 10
D1: Int/48 D2: Object/2099201 Tos: 22 RegAddr: 0
****************** Errors ******************
#IBUFN-7: 0 ← 1
#IBUFN-6: 0 ← 1
#IBUFN-5: 0 ← 1
#IBUFN-4: 0 ← 1
#IBUFN-3: 0 ← 1
#IBUFN-2: 0 ← 1
#IBUFN-1: 0 ← 1
#IBUFN-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010001 $Opcode: 255 #$Opcode 255 #NCurPc: 10
D1: Int/64 D2: XType/928513019 Tos: 22 RegAddr: 0
****************** Errors ******************
#IBUFN-7: 0 ← 1
#IBUFN-6: 0 ← 1
#IBUFN-5: 0 ← 1
#IBUFN-4: 0 ← 1
#IBUFN-3: 0 ← 1
#IBUFN-2: 0 ← 1
#IBUFN-1: 0 ← 1
#IBUFN-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 255 #$Opcode 255 #NCurPc: 10
D1: -- D2: Float/143165568 Tos: 22 RegAddr: 0
****************** Errors ******************
#IBUFN-7: 0 ← 1
#IBUFN-6: 0 ← 1
#IBUFN-5: 0 ← 1
#IBUFN-4: 0 ← 1
#IBUFN-3: 0 ← 1
#IBUFN-2: 0 ← 1
#IBUFN-1: 0 ← 1
#IBUFN-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 32 #$Opcode 255 #NCurPc: 10
D1: -- D2: Object/0 Tos: 22 RegAddr: 0
****************** Errors ******************
#IBUFN-7: 0 ← 1
#IBUFN-6: 0 ← 1
#IBUFN-5: 0 ← 1
#IBUFN-4: 0 ← 1
#IBUFN-3: 0 ← 1
#IBUFN-2: 0 ← 1
#IBUFN-1: 0 ← 1
#IBUFN-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 32 #$Opcode 32 #NCurPc: 10
D1: -- D2: Object/0 Tos: 22 RegAddr: 0
New Opcode: 32 Length: 2 Data: Object/64 N: 64 PC: 10 OldOpLength: 2
Executing uInst: getptr:32
#MIR: (Label←Getptr EUop←+ Tag←D2 Dswap Raddr←Tos RD1addr←IBufData W2addr←MarD1 Condcode←PointerpD2 
NextInstB←Ufn-1d)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 26 #$Opcode 32 #NCurPc: 12
D1: Object/64 D2: Object/2099201 Tos: 22 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 26 #$Opcode 32 #NCurPc: 12
D1: Object/2099265 D2: -- Tos: 22 RegAddr: 0
Executing uInst: LAB0033:65
#MIR: (Cycle←R1 Waddr←Tos CondCode←NoFault Cwrite NextInstA←Done NextInstB←PageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 26 #$Opcode 32 #NCurPc: 12
D1: Object/2099201 D2: Object/2099201 Tos: 22 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 26 #$Opcode 32 #NCurPc: 12
D1: -- D2: Int/17 Tos: 22 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 26 #$Opcode 32 #NCurPc: 12
D1: Object/2099201 D2: Object/2099201 Tos: 22 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 26 #$Opcode 26 #NCurPc: 12
D1: Int/1073741823 D2: Int/7 Tos: 22 RegAddr: 0
New Opcode: 26 Length: 1 Data: Object/0 N: 68 PC: 12 OldOpLength: 1
Executing uInst: '1:26
#MIR: (Label←'1 EUop←D2 Tag←Int RD2addr←MuxRdSel MuxRdSel←K K←1 Waddr←Tos' Tos'←Tos+1 NewTos←Tos' 
NextInstA←Done)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 68 #$Opcode 26 #NCurPc: 13
D1: Int/7 D2: Object/1 Tos: 22 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 68 #$Opcode 68 #NCurPc: 13
D1: Int/1 D2: -- Tos: 23 RegAddr: 0
New Opcode: 68 Length: 1 Data: Object/0 N: 34 PC: 13 OldOpLength: 1
Executing uInst: plus:213
#MIR: (Label←Plus EUop←+ Tag←Int Raddr←Tos RD2addr←Raddr-1 W2addr←Tmp1D1 CondCode←IntegerD1D2 
NextInstB←Ufn-2)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 34 #$Opcode 68 #NCurPc: 14
D1: Int/1 D2: Int/7 Tos: 23 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 34 #$Opcode 68 #NCurPc: 14
D1: Int/8 D2: -- Tos: 23 RegAddr: 0
Executing uInst: LAB0019:228
#MIR: (EUop←D2 Tag←Int RD2addr←Tmp1 Waddr←Tos' Tos'←Tos-1 NewTos←Tos' CondCode←NoOverflow CWrite 
NextInstA←Done NextInstB←Ufn-2)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 34 #$Opcode 68 #NCurPc: 14
D1: Int/1 D2: Int/8 Tos: 23 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 34 #$Opcode 34 #NCurPc: 14
D1: Int/8 D2: -- Tos: 22 RegAddr: 0
New Opcode: 34 Length: 2 Data: Object/64 N: 64 PC: 14 OldOpLength: 2
Executing uInst: rplptr:34
#MIR: (Label←Rplptr EUop←D2 Tag←D2 Raddr←Tos RD2addr←Raddr-1 W2addr←MarD1 Condcode←PointerpD2 
NextInstB←Ufn-2d)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 112 #$Opcode 34 #NCurPc: 16
D1: Int/8 D2: Object/2099201 Tos: 22 RegAddr: 0
****************** Errors ******************
#CONDA: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 112 #$Opcode 34 #NCurPc: 16
D1: Object/2099201 D2: -- Tos: 22 RegAddr: 0
Executing uInst: LAB0036:229
#MIR: (EUop←+ Tag←D1 RD1addr←Mar RD2addr←MuxRdSel MuxRdSel←IBufN W2addr←MarD1 
NextInstA←RefCountStorePop)
****************** Errors ******************
D1-30: 1 ← 0
D1-21: 0 ← 1
D1-11: 0 ← 1
D1-3: 1 ← 0
D1-0: 0 ← 1
VAD-21: 0 ← 1
VAD-11: 0 ← 1
VAD'-21: 1 ← 0
VAD'-11: 1 ← 0
VAD'-3: 0 ← 1
VAD'-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 112 #$Opcode 34 #NCurPc: 16
D1: Object/2099201 D2: Object/64 Tos: 22 RegAddr: 0
****************** Errors ******************
D1-30: 1 ← 0
D1-21: 0 ← 1
D1-11: 0 ← 1
D1-3: 1 ← 0
D1-0: 0 ← 1
VAD-21: 0 ← 1
VAD-11: 0 ← 1
VAD'-21: 1 ← 0
VAD'-11: 1 ← 0
VAD'-3: 0 ← 1
VAD'-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 112 #$Opcode 34 #NCurPc: 16
D1: Object/2099265 D2: -- Tos: 22 RegAddr: 0
Executing uInst: refcountstorepop:216
#MIR: (Label←RefCountStorePop Cycle←R1 Waddr←K WCxt←K K←Decref CondCode←NoFault NextInstB←PageFault)
****************** Errors ******************
D1-30: 1 ← 0
D1-21: 0 ← 1
D1-11: 0 ← 1
D1-3: 1 ← 0
D1-0: 0 ← 1
VAD-21: 0 ← 1
VAD-11: 0 ← 1
VAD'-21: 1 ← 0
VAD'-11: 1 ← 0
VAD'-3: 0 ← 1
VAD'-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 112 #$Opcode 34 #NCurPc: 16
D1: Int/8 D2: Object/2099201 Tos: 22 RegAddr: 0
****************** Errors ******************
VAD-21: 0 ← 1
VAD-11: 0 ← 1
VAD'-21: 1 ← 0
VAD'-11: 1 ← 0
VAD'-3: 0 ← 1
VAD'-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 112 #$Opcode 34 #NCurPc: 16
D1: Int/1073741823 D2: Int/7 Tos: 22 RegAddr: 0
Executing uInst: LAB0037:111
#MIR: (Cycle←W1 Dswap Raddr←Tos CondCode←NoFault NextInstB←PageFault)
****************** Errors ******************
VAD-21: 0 ← 1
VAD-11: 0 ← 1
VAD'-21: 1 ← 0
VAD'-11: 1 ← 0
VAD'-3: 0 ← 1
VAD'-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 112 #$Opcode 34 #NCurPc: 16
D1: Object/2099201 D2: Int/8 Tos: 22 RegAddr: 0
****************** Errors ******************
D1-30: 1 ← 0
D1-21: 0 ← 1
D1-11: 0 ← 1
D1-3: 1 ← 0
D1-0: 0 ← 1
VAD-21: 0 ← 1
VAD-11: 0 ← 1
VAD'-21: 1 ← 0
VAD'-11: 1 ← 0
VAD'-3: 0 ← 1
VAD'-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 112 #$Opcode 34 #NCurPc: 16
D1: -- D2: -- Tos: 22 RegAddr: 0
****************** Errors ******************
VAD-21: 0 ← 1
VAD-11: 0 ← 1
VAD'-21: 1 ← 0
VAD'-11: 1 ← 0
VAD'-3: 0 ← 1
VAD'-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 112 #$Opcode 34 #NCurPc: 16
D1: -- D2: -- Tos: 22 RegAddr: 0
Executing uInst: pagefault:212
#MIR: (Label←PageFault EUop←D1 Tag←Int RD1addr←Mar Waddr←Tos' Tos'←Tos+1 NewTos←Tos' NewArg←K K←1 
Misc←OpLength=0 CondCode←FramesAvail Cwrite NextInstB←DumpFrame)
****************** Errors ******************
VAD-21: 0 ← 1
VAD-11: 0 ← 1
VAD'-21: 1 ← 0
VAD'-11: 1 ← 0
VAD'-3: 0 ← 1
VAD'-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 112 #$Opcode 34 #NCurPc: 16
D1: Object/2099265 D2: Object/2099201 Tos: 22 RegAddr: 0
****************** Errors ******************
D1-30: 1 ← 0
D1-21: 0 ← 1
D1-11: 0 ← 1
D1-3: 1 ← 0
D1-0: 0 ← 1
VAD-21: 0 ← 1
VAD-11: 0 ← 1
VAD'-21: 1 ← 0
VAD'-11: 1 ← 0
VAD'-3: 0 ← 1
VAD'-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 112 #$Opcode 34 #NCurPc: 16
D1: Int/2099265 D2: -- Tos: 23 RegAddr: 0
Executing uInst: LAB0072:146
#MIR: (EUop←D1 Tag←D1 Raddr←K K←PFCode RCxt←K W2addr←MarD1 NextInstA←Fn1)
****************** Errors ******************
D1-21: 0 ← 1
D1-11: 0 ← 1
D1-3: 1 ← 0
D1-0: 0 ← 1
VAD-21: 0 ← 1
VAD-11: 0 ← 1
VAD'-21: 1 ← 0
VAD'-11: 1 ← 0
VAD'-3: 0 ← 1
VAD'-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 34 #$Opcode 34 #NCurPc: 14
D1: Code/100663424 D2: -- Tos: 23 RegAddr: 0
****************** Errors ******************
VAD-21: 0 ← 1
VAD-11: 0 ← 1
VAD'-21: 1 ← 0
VAD'-11: 1 ← 0
VAD'-3: 0 ← 1
VAD'-0: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 34 #$Opcode 34 #NCurPc: 14
D1: Code/100663424 D2: -- Tos: 23 RegAddr: 0
Executing uInst: fn1:197
#MIR: (Label←Fn1 EUop←+4 Tag←D1 RD1addr←Mar W2addr←MarD1 NewArg2←Arg NewArg←K K←StkHdr CondCode←CCodeP
 NextInstB←Fn5)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 34 #$Opcode 34 #NCurPc: 14
D1: Code/100663424 D2: Int/8 Tos: 23 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 34 #$Opcode 34 #NCurPc: 14
D1: Code/100663428 D2: -- Tos: 23 RegAddr: 0
Executing uInst: LAB0041:115
#MIR: (Cycle←R4 WCxt←Next Waddr←Arg<6>/QW<2> EUop←+4 Tag←D1 RD1addr←Mar W2addr←MarD1 CondCode←NoFault 
NextInstB←PageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010010 $Opcode: 34 #$Opcode 34 #NCurPc: 14
D1: Code/100663428 D2: Int/8 Tos: 23 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010001 $Opcode: 34 #$Opcode 34 #NCurPc: 14
D1: Code/100663432 D2: Int/16 Tos: 23 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 34 #$Opcode 34 #NCurPc: 14
D1: -- D2: Int/0 Tos: 23 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 34 #$Opcode 34 #NCurPc: 14
D1: -- D2: Code/100663424 Tos: 23 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 34 #$Opcode 34 #NCurPc: 14
D1: -- D2: Code/100663424 Tos: 23 RegAddr: 0
Executing uInst: LAB0042:116
#MIR: (EUop←D2 Tag←D2 RD2addr←Unbound Waddr←K K←PVar WCxt←Next Misc←WriteOctal NewArg←Arg2)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 34 #$Opcode 34 #NCurPc: 14
D1: Int/2099265 D2: Ptr-32/0 Tos: 23 RegAddr: 0
****************** Errors ******************
D1-21: 0 ← 1
D1-11: 0 ← 1
D1-3: 1 ← 0
D1-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 34 #$Opcode 34 #NCurPc: 14
D1: Ptr-32/0 D2: -- Tos: 23 RegAddr: 0
Executing uInst: fn2:198
#MIR: (Label←Fn2 EUop←D2 Tag←D2 RD2addr←Nil Waddr←K K←IVar WCxt←Next Misc←WriteOctal)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 34 #$Opcode 34 #NCurPc: 14
D1: Int/2099265 D2: Atm/3584 Tos: 23 RegAddr: 0
****************** Errors ******************
D1-21: 0 ← 1
D1-11: 0 ← 1
D1-3: 1 ← 0
D1-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 34 #$Opcode 34 #NCurPc: 14
D1: Atm/3584 D2: -- Tos: 23 RegAddr: 0
Executing uInst: LAB0043:117
#MIR: (EUop←D2 Tag←Int RD2addr←PC Waddr←K K←Pc Misc←Oplength=0&SetInitialRefill)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 34 #$Opcode 34 #NCurPc: 14
D1: Int/2099265 D2: Int/46 Tos: 23 RegAddr: 0
****************** Errors ******************
D1-21: 0 ← 1
D1-11: 0 ← 1
D1-3: 1 ← 0
D1-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 34 #$Opcode 34 #NCurPc: 14
D1: Int/46 D2: -- Tos: 23 RegAddr: 0
Executing uInst: LAB0044:118
#MIR: (EUop←+ Tag←Int RD1addr←Mar RD2addr←MuxRdSel MuxRdSel←Arg W2Addr←MarD1)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 34 #$Opcode 34 #NCurPc: 14
D1: Code/100663432 D2: Object/1 Tos: 23 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 34 #$Opcode 34 #NCurPc: 14
D1: Int/100663433 D2: -- Tos: 23 RegAddr: 0
Executing uInst: LAB0045:119
#MIR: (Cycle←R1 Waddr←K WCxt←Next K←Pc)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 34 #$Opcode 34 #NCurPc: 14
D1: Int/2099265 D2: Int/8 Tos: 23 RegAddr: 0
****************** Errors ******************
D1-21: 0 ← 1
D1-11: 0 ← 1
D1-3: 1 ← 0
D1-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 34 #$Opcode 34 #NCurPc: 14
D1: Int/1073741823 D2: Int/560 Tos: 23 RegAddr: 0
Executing uInst: LAB0046:120
#MIR: (EUop←D1 Tag←Int Raddr←K RCxt←Next K←PC W2addr←PCD1)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 34 #$Opcode 34 #NCurPc: 14
D1: Int/560 D2: Int/16 Tos: 23 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 34 #$Opcode 34 #NCurPc: 14
D1: Int/560 D2: -- Tos: 23 RegAddr: 0
Executing uInst: LAB0047:121
#MIR: (EUop←D2 Tag←Int RD2addr←MuxRdSel MuxRdSel←K K←Ivar NewArg2←K W2addr←MarD1 NewArg←Arg' 
Arg'←Arg-1 CondCode←Arg#0 NextInstB←Fn3)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 112 #$Opcode 34 #NCurPc: 16
D1: Int/2099265 D2: Object/8 Tos: 23 RegAddr: 0
****************** Errors ******************
D1-21: 0 ← 1
D1-11: 0 ← 1
D1-3: 1 ← 0
D1-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 112 #$Opcode 34 #NCurPc: 16
D1: Int/8 D2: -- Tos: 23 RegAddr: 0
Executing uInst: LAB0048:122
#MIR: (EUop←+ Tag←Int RD1addr←Mar RD2addr←MuxRdSel MuxRdSel←Arg W2addr←Tmp1D1)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 112 #$Opcode 34 #NCurPc: 16
D1: Int/8 D2: Object/0 Tos: 23 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 112 #$Opcode 34 #NCurPc: 16
D1: Int/8 D2: -- Tos: 23 RegAddr: 0
Executing uInst: LAB0049:123
#MIR: (RD2addr←Tmp1 NewArg←D2)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 112 #$Opcode 34 #NCurPc: 16
D1: Int/2099265 D2: Int/8 Tos: 23 RegAddr: 0
****************** Errors ******************
D1-21: 0 ← 1
D1-11: 0 ← 1
D1-3: 1 ← 0
D1-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 112 #$Opcode 34 #NCurPc: 16
D1: Int/1073741823 D2: -- Tos: 23 RegAddr: 0
Executing uInst: LAB0050:124
#MIR: (EUop←D1 Tag←D1 Raddr←Tos WCxt←Next Waddr←Arg NewTos←Tos' Tos'←Tos-1 NewArg←Arg' Arg'←Arg-1 
CondCode←Arg=Arg2 NextInstB←Rpt)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 112 #$Opcode 34 #NCurPc: 16
D1: Int/2099265 D2: Int/8 Tos: 23 RegAddr: 0
****************** Errors ******************
D1-21: 0 ← 1
D1-11: 0 ← 1
D1-3: 1 ← 0
D1-0: 0 ← 1
****************** Errors ******************
#CONDA: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 112 #$Opcode 34 #NCurPc: 16
D1: Int/2099265 D2: -- Tos: 22 RegAddr: 0
Executing uInst: fn3:199
#MIR: (Label←Fn3 EUop←D1<24>/D2<8> Tag←D1 RD2addr←MuxRdSel MuxRdSel←Tos Raddr←K Waddr←K K←StkHdr)
****************** Errors ******************
D1-21: 0 ← 1
D1-11: 0 ← 1
D1-3: 1 ← 0
D1-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 112 #$Opcode 34 #NCurPc: 16
D1: XType/1073741590 D2: Object/22 Tos: 22 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 112 #$Opcode 34 #NCurPc: 16
D1: XType/1073741590 D2: -- Tos: 22 RegAddr: 0
Executing uInst: LAB0051:125
#MIR: (EUop←D2 Tag←D2 Dswap Raddr←K K←StkHdr RCxt←Next WCxt←Next NewTos←D2 NewTopCxt←Next 
NextInstA←Done)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 112 #$Opcode 34 #NCurPc: 16
D1: -- D2: Int/16 Tos: 22 RegAddr: 0
****************** Errors ******************
D1-31: 0 ← 1
D1-29: 0 ← 1
D1-28: 0 ← 1
D1-27: 0 ← 1
D1-26: 0 ← 1
D1-25: 0 ← 1
D1-24: 0 ← 1
D1-23: 0 ← 1
D1-22: 0 ← 1
D1-21: 0 ← 1
D1-20: 0 ← 1
D1-19: 0 ← 1
D1-18: 0 ← 1
D1-17: 0 ← 1
D1-16: 0 ← 1
D1-15: 0 ← 1
D1-14: 0 ← 1
D1-13: 0 ← 1
D1-12: 0 ← 1
D1-11: 0 ← 1
D1-10: 0 ← 1
D1-9: 0 ← 1
D1-8: 0 ← 1
D1-7: 0 ← 1
D1-6: 0 ← 1
D1-5: 0 ← 1
D1-3: 0 ← 1
D1-2: 0 ← 1
D1-1: 0 ← 1
D1-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 112 #$Opcode 112 #NCurPc: 16
D1: Int/16 D2: -- Tos: 16 RegAddr: 0
New Opcode: 112 Length: 0 Data: Object/0 N: 5 PC: 16 OldOpLength: 0
Executing uInst: loadibuf:209
#MIR: (Label←LoadIBuf Cycle←R4 RD1addr←PcAddr W2addr←IBufD2PcD1 EUop←+16 Tag←Int 
Misc←ResetInitialRefill CondCode←NoFault NextInstA←Done NextInstB←IBufPageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010010 $Opcode: 112 #$Opcode 112 #NCurPc: 16
D1: Int/560 D2: Atm/3584 Tos: 16 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010001 $Opcode: 112 #$Opcode 112 #NCurPc: 16
D1: Int/576 D2: List/80235720 Tos: 16 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 112 #$Opcode 112 #NCurPc: 16
D1: -- D2: Int/862283366 Tos: 16 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 200 #$Opcode 112 #NCurPc: 16
D1: -- D2: XType/1069448763 Tos: 16 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 200 #$Opcode 200 #NCurPc: 16
D1: -- D2: XType/526176237 Tos: 16 RegAddr: 0
New Opcode: 200 Length: 1 Data: Object/0 N: 145 PC: 16 OldOpLength: 1
Executing uInst: vark:233
#MIR: (Label←Vark EUop←D1 Tag←D1 Raddr←0<4>/OpCode<4> Waddr←Tos' Tos'←Tos+1 NewTos←Tos' NextInstA←Done
)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 145 #$Opcode 200 #NCurPc: 17
D1: Int/2099265 D2: -- Tos: 16 RegAddr: 0
****************** Errors ******************
D1-21: 0 ← 1
D1-11: 0 ← 1
D1-3: 1 ← 0
D1-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 145 #$Opcode 145 #NCurPc: 17
D1: Int/2099265 D2: -- Tos: 17 RegAddr: 0
New Opcode: 145 Length: 5 Data: Int/16777215 N: 255 PC: 17 OldOpLength: 5
Executing uInst: intconst:81
#MIR: (Label←IntConst EUop←D1 Tag←Int RD1addr←IBufData Waddr←TOS' TOS'←TOS+1 NewTos←Tos' 
NextInstA←Done)
****************** Errors ******************
D1-21: 0 ← 1
D1-11: 0 ← 1
D1-3: 1 ← 0
D1-0: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 16 #$Opcode 145 #NCurPc: 22
D1: Int/16777215 D2: Ptr-32/0 Tos: 17 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 16 #$Opcode 16 #NCurPc: 22
D1: Int/16777215 D2: -- Tos: 18 RegAddr: 0
New Opcode: 16 Length: 0 Data: Object/0 N: 47 PC: 22 OldOpLength: 0
Executing uInst: loadibuf:209
#MIR: (Label←LoadIBuf Cycle←R4 RD1addr←PcAddr W2addr←IBufD2PcD1 EUop←+16 Tag←Int 
Misc←ResetInitialRefill CondCode←NoFault NextInstA←Done NextInstB←IBufPageFault)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010010 $Opcode: 16 #$Opcode 16 #NCurPc: 22
D1: Int/576 D2: Int/2099265 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010001 $Opcode: 16 #$Opcode 16 #NCurPc: 22
D1: Int/592 D2: XType/1071816350 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010000 $Opcode: 16 #$Opcode 16 #NCurPc: 22
D1: -- D2: Float/1073477457 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011000 $Opcode: 16 #$Opcode 16 #NCurPc: 22
D1: -- D2: XType/1004404446 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010100 $Opcode: 16 #$Opcode 16 #NCurPc: 22
D1: -- D2: Int/1073217523 Tos: 18 RegAddr: 0
New Opcode: 16 Length: 1 Data: Object/0 N: 47 PC: 22 OldOpLength: 1
Executing uInst: and:16
#MIR: (Label←And EUop←And Tag←Int Raddr←Tos RD2addr←Raddr-1 Waddr←Tos' Tos'←Tos-1 NewTos←Tos' 
CondCode←IntegerD1D2 CWrite NextInstA←Done NextInstB←Ufn-2)
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 47 #$Opcode 16 #NCurPc: 23
D1: Int/16777215 D2: Int/2099265 Tos: 18 RegAddr: 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 47 #$Opcode 47 #NCurPc: 23
D1: Int/2099265 D2: -- Tos: 17 RegAddr: 0
New Opcode: 47 Length: 2 Data: Object/10 N: 10 PC: 23 OldOpLength: 2
Executing uInst: lrsh.n:228
#MIR: (Label←Lrsh.N EUop←D1 Tag←Int Raddr←Tos W2addr←MarD1 NewArg←IBufN CondCode←Integerp 
NextInstB←Ufn-1d)
****************** Errors ******************
D1-23: 1 ← 0
D1-22: 1 ← 0
D1-20: 1 ← 0
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/2099265 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-23: 1 ← 0
D1-22: 1 ← 0
D1-20: 1 ← 0
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/2099265 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0031:105
#MIR: (Arg'←Arg-1 NewArg←Arg' CondCode←Arg=0 NextInstA←Done)
****************** Errors ******************
D1-23: 1 ← 0
D1-22: 1 ← 0
D1-20: 1 ← 0
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/2099265 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-23: 1 ← 0
D1-22: 1 ← 0
D1-20: 1 ← 0
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/1073741823 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/2099265 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-23: 1 ← 0
D1-22: 1 ← 0
D1-20: 1 ← 0
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/1049632 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-22: 1 ← 0
D1-21: 1 ← 0
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/1049632 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-22: 1 ← 0
D1-21: 1 ← 0
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/524816 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-21: 1 ← 0
D1-20: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/524816 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-21: 1 ← 0
D1-20: 1 ← 0
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/262408 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-20: 1 ← 0
D1-19: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/262408 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-20: 1 ← 0
D1-19: 1 ← 0
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/131204 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/131204 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-19: 1 ← 0
D1-18: 1 ← 0
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/65602 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/65602 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-18: 1 ← 0
D1-17: 1 ← 0
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/32801 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/32801 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-17: 1 ← 0
D1-16: 1 ← 0
D1-14: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-4: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/16400 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 011010 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/16400 D2: Ptr-32/0 Tos: 17 RegAddr: 0
****************** Errors ******************
D1-16: 1 ← 0
D1-15: 1 ← 0
D1-13: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-3: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1
 *pre/*clock/*op/*micro/*firstcy/*secondcy: 010101 $Opcode: 35 #$Opcode 47 #NCurPc: 25
D1: Int/8200 D2: -- Tos: 17 RegAddr: 0
Executing uInst: LAB0032:106
#MIR: (EUop←Rshft1 Tag←Int Raddr←Tos Waddr←Tos NewArg←Arg' Arg'←Arg-1 CondCode←Arg=0 NextInstA←Done 
NextInstB←Rpt)
****************** Errors ******************
D1-15: 1 ← 0
D1-14: 1 ← 0
D1-12: 1 ← 0
D1-11: 1 ← 0
D1-10: 1 ← 0
D1-9: 1 ← 0
D1-8: 1 ← 0
D1-7: 1 ← 0
D1-6: 1 ← 0
D1-5: 1 ← 0
D1-4: 1 ← 0
D1-2: 1 ← 0
D1-1: 1 ← 0
D1-0: 1 ← 0
VAD-23: 1 ← 0
VAD-22: 1 ← 0
VAD-20: 1 ← 0
VAD-19: 1 ← 0
VAD-18: 1 ← 0
VAD-17: 1 ← 0
VAD-16: 1 ← 0
VAD-15: 1 ← 0
VAD-14: 1 ← 0
VAD-13: 1 ← 0
VAD-12: 1 ← 0
VAD-10: 1 ← 0
VAD'-23: 0 ← 1
VAD'-22: 0 ← 1
VAD'-20: 0 ← 1
VAD'-19: 0 ← 1
VAD'-18: 0 ← 1
VAD'-17: 0 ← 1
VAD'-16: 0 ← 1
VAD'-15: 0 ← 1
VAD'-14: 0 ← 1
VAD'-13: 0 ← 1
VAD'-12: 0 ← 1
VAD'-10: 0 ← 1
VAD'-9: 0 ← 1
VAD'-8: 0 ← 1
VAD'-7: 0 ← 1
VAD'-5: 0 ← 1
VAD'-4: 0 ← 1
VAD'-3: 0 ← 1
VAD'-2: 0 ← 1
VAD'-1: 0 ← 1