<> <> <> <> <<>> <> <<>> DIRECTORY Core, CoreCreate, ICTest, Ports, Rope, TestCable, IO, FS, Convert; TestDRam: CEDAR PROGRAM IMPORTS CoreCreate, ICTest, Ports, TestCable, Rope, IO, FS, Convert = BEGIN <<-- Types>> ROPE: TYPE = Rope.ROPE; VectorEntries: TYPE = RECORD [entrymode: ATOM, entryvalue: LONG CARDINAL]; TestVector: TYPE = ARRAY [0..20] OF VectorEntries; <<-- Vector Assignments>> vectorStream,outstream: IO.STREAM; endofvectors: BOOL; vectors: TestVector; debugging: BOOL; <<-- Port Assignments >> ras: NAT = 0; cas: NAT = 1; we: NAT = 2; addr: NAT = 3; datain: NAT = 4; dataout: NAT = 5; trigger: NAT = 6; lastport: NAT = 6; <<-- Program Controled Ports:>> gnd: NAT = 7; vdd: NAT = 8; cycle: NAT = 9; <<-- Other Globals:>> Assignments: TYPE = ICTest.Assignments; assignments: Assignments; thisTest: Rope.ROPE = "DRam Tester"; groups: ICTest.Groups _ NIL; PrintAssignments: PROC = { stream: FS.STREAM _ FS.StreamOpen["Pinout.txt",$create]; j: ICTest.Assignment; i: Assignments _ assignments; WHILE i#NIL DO { j _ i.first; IO.PutF[stream,"%15g: ",IO.rope[j.name]]; IF j.group = 0 THEN IO.PutF[stream," "] ELSE IO.PutF[stream,"%g %g.%g[%1g] ", IO.rope[IF j.loadBoardSide = R THEN "Right" ELSE "Left "], IO.rope[ SELECT j.podPair FROM AB => "AB", CD => "CD", EF => "EF", GH => "GH", IJ => "IJ", KL => "KL", ENDCASE => "??"], IO.char[SELECT j.pod FROM A => 'A, B => 'B, ENDCASE => '?], IO.int[j.channel], ]; IO.PutF[stream," _ %3g \n",IO.int[j.probeCardPin]]; i _ i.rest; }; ENDLOOP; IO.Close[stream]; }; Init: PROC = { R: PROC [a: ICTest.Assignment] = {assignments _ CONS[a, assignments]}; ct: Core.CellType _ CoreCreate.Cell[name:"DRam", public: CoreCreate.WireList[LIST[ "ras", "cas", "we", CoreCreate.Seq["addr",10], "datain", "dataout", "trigger", "gnd","vdd","cycle"]], onlyInternal: NIL, instances: NIL ]; assignments _ NIL; groups _ LIST [ [number: 1, name: "CtlLines", directionality: force, format: DNRZ, delay: 0], [number: 2, name: "DataIn", directionality: force, format: DNRZ, delay: 0], [number: 3, name: "DataOut", directionality: acquire, format: DNRZ, sample: 5], [number: 4, name: "ClockCycle", directionality: force, format: RZ, delay: 0, width: 20] ]; assignments _ NIL; << L>> << o >> << a T>> << d e>> << s>> << B t D>> << o e U>> << a P r T>> << r o C D>> << d d h H H U>> << G B a e e T>> << r o S P B n a a >> << o a i a y n d d P>> << u r d i t e e e i>> <> R[["gnd", 0,0,R,AB, A,1,001,001,18]]; R[["vdd", 0,0,R,AB, A,0,001,001,9]]; R[["ras", 1,0,R,AB, B,0,001,001,3]]; R[["cas", 1,0,R,AB, B,1,001,001,16]]; R[["we", 1,0,R,AB, B,2,001,001,2]]; R[["trigger", 1,0,R,AB, B,3,001,001,100]]; R[["addr[9]", 1,2,R,EF, B,1,001,001,15]]; R[["addr[8]", 1,2,R,EF, B,0,001,001,14]]; R[["addr[7]", 1,1,R,CD, B,7,001,001,13]]; R[["addr[6]", 1,1,R,CD, B,6,001,001,12]]; R[["addr[5]", 1,1,R,CD, B,5,001,001,11]]; R[["addr[4]", 1,1,R,CD, B,4,001,001,10]]; R[["addr[3]", 1,1,R,CD, B,3,001,001,8]]; R[["addr[2]", 1,1,R,CD, B,2,001,001,7]]; R[["addr[1]", 1,1,R,CD, B,1,001,001,6]]; R[["addr[0]", 1,1,R,CD, B,0,001,001,5]]; R[["datain", 2,3,R,GH, B,0,001,001,1]]; R[["dataout", 3,4,R,IJ, B,0,001,001,17]]; R[["cycle", 4,0,R,AB, A,3,001,001,200]]; [] _ Ports.InitPort[ct.public[datain],c]; [] _ Ports.InitPort[ct.public[dataout],c]; [] _ Ports.InitPort[ct.public[addr],c]; [] _ Ports.InitPort[ct.public[ras],c]; [] _ Ports.InitPort[ct.public[cas],c]; [] _ Ports.InitPort[ct.public[we],c]; [] _ Ports.InitPort[ct.public[cycle],b]; [] _ Ports.InitPort[ct.public[trigger],c]; Ports.InitTesterDrive[ct.public[vdd],force]; Ports.InitTesterDrive[ct.public[gnd],force]; Ports.InitTesterDrive[ct.public[cycle],force]; Ports.InitTesterDrive[ct.public[addr],force]; Ports.InitTesterDrive[ct.public[ras],force]; Ports.InitTesterDrive[ct.public[cas],force]; Ports.InitTesterDrive[ct.public[we],force]; Ports.InitTesterDrive[ct.public[datain],force]; Ports.InitTesterDrive[ct.public[dataout],none]; Ports.InitTesterDrive[ct.public[trigger],force]; <> ICTest.MakeStandardViewer[ testName: thisTest, cellType: ct, clockAName: "cycle", groups: groups, assignments: assignments, period: 250]; }; PeriodChange: ICTest.PeriodChangeProc ~ { <<--PROC [period: Period] RETURNS [newGroups: Groups]-->> <> <> <> <> <> RETURN[groups]; }; NextVector: PROC = { <<-- Read in the next cycle's test vectors>> i,j: INT; needrparen: BOOL; token: ROPE; needrparen _ TRUE; j_0; i_0; IF ~ IO.EndOf[vectorStream] THEN { WHILE needrparen AND ~ endofvectors AND ~ IO.EndOf[vectorStream] DO { j _ j+1; token _ IO.GetTokenRope[vectorStream].token; SELECT Rope.Fetch[token,0] FROM ') => needrparen _ FALSE; '( => i _ 0; 'S => { vectors[i].entryvalue _ Convert.CardFromRope[Rope.Substr[token,1]]; vectors[i].entrymode _ $Set; i _ i + 1; }; 'x,'X => { vectors[i].entryvalue _ 0; vectors[i].entrymode _ $Ignore; i _ i + 1; }; 'E => endofvectors _ TRUE; '0,'1,'2,'3,'4,'5,'6,'7,'8,'9 => { vectors[i].entryvalue _ Convert.CardFromRope[token]; vectors[i].entrymode _ $Set; i _ i + 1; }; ENDCASE; }; ENDLOOP; } ELSE endofvectors _ TRUE; }; OpenVectors: PROC = { <<>> vectorStream _ FS.StreamOpen["///datools/DRam2.txt"]; IF debugging THEN outstream _ FS.StreamOpen["///datools/debug.txt", $create]; <<>> <<>> endofvectors _ FALSE; NextVector[]; }; CloseVectors: PROC = { IO.Close[vectorStream]; IF debugging THEN IO.Close[outstream]; }; DoTest: ICTest.TestProc = { SetP: PROC [vectorindex, value: LONG CARDINAL, mode: Ports.Drive] = { p[vectorindex].d _ mode; p[vectorindex].c _ value; }; ClearEntry: PROC [vectorindex: INT] = { SetP[vectorindex, 0, none]; }; SetEntry: PROC [vectorindex: INT] = { SELECT vectors[vectorindex].entrymode FROM $Set => SetP[vectorindex, vectors[vectorindex].entryvalue, force]; $Check => SetP[vectorindex, vectors[vectorindex].entryvalue, expect]; $Ignore => SetP[vectorindex, 0, none]; ENDCASE; }; DoEval: PROC = { p[cycle].b _ TRUE; IF debugging THEN FOR i: INT _ 0, i+1 DO { IF i > lastport THEN {IO.Put[outstream,IO.char[15C]]; EXIT;} ELSE { IO.PutF[outstream, SELECT p[i].d FROM expect => " C: ", force => " S: ", drive => " D: ", none => " x ", ENDCASE => " ?: " ]; IF p[i].d # none THEN IO.Put[outstream,IO.int[p[i].c]]; }; }; ENDLOOP ELSE Eval[]; }; Cycle: PROC = { FOR i: INT _ 0, i+1 DO SetEntry[i]; IF i = lastport THEN EXIT; ENDLOOP; DoEval[]; }; InitState: PROC = { FOR i: INT _ 0, i+1 DO ClearEntry[i]; IF i = lastport THEN EXIT; ENDLOOP; p[gnd].c _ 0; p[gnd].d _ force; p[vdd].c _ 1; p[vdd].d _ force; p[cycle].b _ TRUE; p[cycle].d _ force; }; InitState[]; OpenVectors[]; WHILE ~endofvectors DO Cycle[]; NextVector[]; ENDLOOP; CloseVectors[]; }; Runit: PROC = { debugging _ FALSE; Init[]; ICTest.RegisterTestProc[thisTest,"RamTest",DoTest]; <> ICTest.RegisterPeriodChangeProc[thisTest, PeriodChange]; }; Runit[]; END. <<>> <<>>