Notes about MI2 chip - Feb 10, 1985 4pm The version number on the chip is MI2-9. The file version is MI2-8. The MPCHIP submittal is MI2-7. This chip has several minor bug fixes from MI1-85 1) Changed ratios on 2 pullups in arbiter. The old version worked at 6 volts. This should allow it to work at 5.0 volts 2) Inverted RASx inputs so RASOK is correct. On MI1, had to disable this feature. 3) Moved pads on the top-right side over one position to avoid the seal ring pad. 4) Changed T30 to be T40 to slightly correct timing. To create CIF file, I used CIFGEN with lambda = 200 and the normal layer names. To verify, I made a sim file by modifying the design: VCTLConnect symbol was removed, T0 was moved to T10. The file MI2-pullup provided dummy pullups for RAS, CAS, WE. Sim file was created by doing Extract with SIM: Y, Crystal: Y, Wiring: MI2. To run MOSSIM, @MI2-sim. Then Init, 0 0 DoRead (to initialize) and then it was ready. Without moving T0 to T10, the simulator would propogate Xs on RAS0, RASOK, T0. This could be avoided by tying RASOK high or RASx high. Remaining problems: 1) Rdy output may still use clock of wrong polarity. 2) No pullups on RAS, CAS, etc.