; VTIDrc.rul ; ============================================================================ ; Copyright (C) 1986, 1987 by Xerox Corporation. All rights reserved. ; Written by Mark Ross January 13, 1987 8:24:13 am PST ; ; The design rules contained herein are proprietary and confidential. Any ; release of these rules without the written consent of Xerox Corporation is prohibited. ; ; Command file for 2 micron design rules. ; Basic design rules (i.e., those common to VTI and Dragon) are contained in this file. ; An advisory set of rules can be found by looking in AdvisoryDrc.rul. ; ; Rules which are not checked: ; Bonding pads, I/O rules, well and substrate Taps. For more info on these see ; VTI document 02-ECLA-2 rev *F ; ; Edit History: ; ; -- Last Edited: Ross March 30, 1987 9:26:37 am PST ; Added checks for max. size of vias and contacts. ; Added the complete set of VTI design rules. ; -- Last Edited: Ross April 16, 1987 1:38:30 pm PDT ; Modified check for large vias not to flag large vias under oxide cut ; ; -- Last Edited: Ross April 27, 1987 9:30:11 am PDT ; Modified rules implementation to use atoms from VTIRulesImpl.mesa ; ============================================================================ *DESCRIPTION PROGRAM-DIR = /user/csl/ecad/drc16p/ SYSTEM = CIF SCALE = 0.01 MIC RESOLUTION = 0.01 MIC INDISK = in.cif OUTDISK = drcout.cif KEEPDATA = SMART MODE = EXEC NOW SYSOUT = CIF SCALEOUT = 0.25 MIC PRINTFILE = drcout *END ; ============================================================================ ; Specify the input layers coming from the tape. ; ============================================================================ *Input-Layer nwell = CNW nwcont = CNWC pwcont = CPWC ndiff = CND pdiff = CPD poly = CP cont = CC met1 = CM via = CC2 met2 = CM2 butting = CB pad = CG *END ; ============================================================================ ; Actual DRC follows: ; ============================================================================ *Operation ; Create all of the right "things" from the mask data NOT cont butting contact ; Eliminate all of the butting contacts. AND cont butting butcont ; The residue will go here. OR nwcont pwcont cdiff OR pdiff ndiff sdiff OR cdiff sdiff diff AND poly ndiff ntrans AND poly pdiff ptrans OR ptrans ntrans trans ; Generate necessary layers AND poly contact polcont AND diff contact dcont AND pdiff contact pdcont AND ndiff contact ndcont ; Checks (listed in order of VTI design rules) ; **** Tub Rules **** WIDTH nwell LT $NWellWidth OUTPUT errw1 1 ; VTIRule 6.1.1 (4) EXT[h] nwell LT $NWellSpace OUTPUT errw2 1 ; VTIRule 6.1.2 (12) ; **** Diffusion Rules **** WIDTH diff LT $NDifWidth OUTPUT errd1 2 ; VTIRule 6.3.1 (2) ENC[t] trans sdiff LT 0.01 & WIDTH trans lt $NTransistorChannelWidth OUTPUT errd2 2 ; VTIRule 6.3.2 (3) EXT[h] diff LT $NDifSpace OUTPUT errd3 2 ; VTIRule 6.3.3 (3.5) EXT[o] sdiff cdiff LT $NWellDifPWellDifSpace OUTPUT errd4 2 ; VTIRule 6.3.4 (3.5) ENC[to] pdiff nwell LT $NWellPDifSurround OUTPUT errd5 2 ; VTIRule 6.3.5 (5) ENC[to] nwcont nwell LT $NWellNWellDifSurround OUTPUT errd6 2 ; VTIRule 6.3.6 (3) EXT[to] ndiff nwell LT $NWellNDifSpace OUTPUT errd7 2 ; VTIRule 6.3.7 (7) EXT[to] pwcont nwell LT $PWellDifNWellSpace OUTPUT errd9 2 ; VTIRule 6.3.9 (5) EXT[to] pwcont nwcont LT $PWellDifNWellDifSpace OUTPUT errd10 2 ; VTIRule 6.3.10 (4) EXT[to] pdiff ndiff LT $NDifPWellPDifNWellSpace OUTPUT errd11 2 ; VTIRule 6.3.12 (12) ENC trans diff LT $NTransistorChannelExtension OUTPUT errd12 2 ; VTIRule 6.3.18 (3) ; **** Poly Rules **** WIDTH poly LT $PolyWidth OUTPUT errp1 3 ; VTIRule 6.4.1 (2) EXT[h] poly LT $PolySpace OUTPUT errp2 3 ; VTIRule 6.4.3 (2.5) ENC[t] trans sdiff LT 0.01 & ENC[t] trans poly LT $NTransistorGateExtension OUTPUT errp3 3 ; VTIRule 6.4.4 (2) EXT[t] poly diff LT $PolyNDifSpace OUTPUT errp4 3 ; VTIRule 6.4.5 (1) AND poly cdiff foo OUTPUT errp5 3 ; Poly over tap ; **** Contact Rules **** WIDTH contact LT $ContactWidth OUTPUT errc1 4 ; VTIRule 6.5.1.1 (2) WIDTH[r] contact LE $ContactMaxWidth gdcont NOT contact gdcont bdcont OUTPUT errc9 4 ; VTI rule 6.5.1.2 (5x5) EXT[h] contact LT $ContactSpace OUTPUT errc2 4 ; VTIRule 6.5.1.3 (3) ENC[to] contact poly LT $PolyContactSurround OUTPUT errc3 4 ; VTIRule 6.5.1.4 (1) ENC[to] contact diff LT $NDifContactSurround OUTPUT errc4 4 ; VTIRule 6.5.1.5 (1) EXT[t] dcont trans LT $ContactGateSpace OUTPUT errc5 4 ; VTIRule 6.5.1.6 (1.5) EXT[t] polcont diff LT $PolyContactNDifSpace OUTPUT errc6 4 ; VTIRule 6.5.1.7 (2) ENC[to] contact met1 LT $Metal1ContactSurround OUTPUT errc7 4 ; VTIRule 6.5.1.8 (1) EXT[o] trans cdiff LT $NTransistorPWellDifSpace OUTPUT errc8 4 ; VTIRule 6.5.2.3 (3) ; Any "butting contact" which is not generated atomically will be flagged. ; **** Met1 Rules **** WIDTH met1 LT $Metal1Width OUTPUT err1m1 5 ; VTIRule 6.6.1 (2) EXT[h] met1 LT $Metal1Space OUTPUT err1m2 5 ; VTIRule 6.6.2 (3) ; **** Via Rules **** WIDTH via LT $ViaWidth OUTPUT errv1 6 ; VTIRule 6.7.2 (2) WIDTH[r] via LE $ViaMaxWidth gdvia NOT via gdvia bdvia NOT bdvia pad rbdvia OUTPUT errv9 6 ; VTIRule 6.7.3 big via over pad ok EXT[h] via LT $ViaSpace OUTPUT errv2 6 ; VTIRule 6.7.4 (4) ENC[to] via met1 LT $Metal1ViaSurround OUTPUT errv3 6 ; VTIRule 6.7.5 (1) ENC[to] via met2 LT $Metal2ViaSurround OUTPUT errv4 6 ; VTIRule 6.7.5 (1) EXT via poly LT $PolyViaSpace OUTPUT errv5 6 ; VTIRule 6.7.6 (2) ENC[to] via poly LT $PolyViaSurround OUTPUT errv6 6 ; VTIRule 6.7.7 (3) EXT[to] via dcont LT $DifCutViaSpace OUTPUT errv7 6 ; VTIRule 6.7.8 (2) EXT[to] via polcont LT $PolyCutViaSpace OUTPUT errv8 6 ; VTIRule 6.7.9 (3) ; **** Met2 Rules **** WIDTH met2 LT $Metal2Width OUTPUT err2m1 7 ; VTIRule 6.8.1 (3) EXT[h] met2 LT $Metal2Space OUTPUT err2m2 7 ; VTIRule 6.8.2 (4) ; **** Misc. Checks **** AND ndiff nwell junk1 OUTPUT errsc1 8 ; Check for bad ndiff NOT pdiff nwell junk2 OUTPUT errsc2 8 ; Check for bad pdiff *END