0 0 60 1f 0 | xxxxxxxxx fedcba98 0 60 1f 0 | fffffffff 0 0 00 7f 1 | 01234567f 0 0 00 7f 1 | 1234567ff 0 0 00 7f 1 | 234567fff 0 0 00 7f 1 | 34567ffff 0 0 00 7f 1 | 4567fffff 0 0 00 7f 1 | 567ffffff 0 0 00 7f 1 | 67fffffff 0 0 00 7f 1 | 7ffffffff 0 0 00 7f 0 | fffffffff fedcba98 0 60 1f 0 | fffffffff 0 0 00 7f 2 | 01234567f 0 0 00 7f 2 | 01234567f 0 0 00 7f 2 | 01234567f 0 0 00 7f 2 | 01234567f 0 0 00 7f 2 | 01234567f 0 0 00 7f 2 | 01234567f 0 0 00 7f 2 | 01234567f 0 0 00 7f 2 | 01234567f 0 0 00 7f 0 | 01234567f . °ARegTopTestVecs.tioga by Ross May 6, 1987 5:39:49 pm PDT Last Edited by: Ross May 11, 1987 4:06:42 pm PDT These vectors check to see that the a-register for the multiplier is working properly. The essential operation is to load D2, load FLTD2, hold (recirculate data), or shift. NOTE THAT THE OUTPUT IS INVERTED TO CONFORM TO THE REQUIREMENTS OF THE SHIFTER. Shifting accomplishes the partial product shifting necessary during the mode for performing lower only products. State assignments for "state" are repeated below for convenience: 00 done 01 doingLower 10 doingUpper 11 Invalid D2 fltD2 EUctl nEUctl state | ARegOut Make sure that in the other mode it doesn't shift Κ–˜™J™"Icode™0J™J™—™³J™J™ J™ J™ J™—J™'J˜J˜#J˜J˜J˜J˜J˜J˜J˜J˜J˜J˜J™1J˜J˜#J˜J˜J˜J˜J˜J˜J˜J˜J˜J˜J˜J˜—…—œβ