[phylum]<CTamarin>TestVecs>IBufTestVecs.tioga!2

IBufTestVecs.tioga

Last Edited by: Ross April 16, 1987 3:51:10 pm PDT

Note: These vectors assume take into account the delay caused by the IBufDataRegs.

xbus nwtibuf selwt selnext selcur selshft selibdata nbytesel load | opcode ibsres

Load up the inst buffer

03020100 0 8 1 8 4 2 7 1 | XX XXXXXXXX

07060504 0 4 1 8 4 2 7 1 | XX XXXXXXXX

0B0A0908 0 2 1 8 4 2 7 1 | XX XXXXXXXX

0F0E0D0C 0 1 1 8 4 2 7 1 | XX XXXXXXXX

00000000 0 80 1 8 4 2 7 1 | XX XXXXXXXX

00000000 0 40 1 8 4 2 7 1 | XX XXXXXXXX

00000000 0 20 1 8 4 2 7 1 | XX XXXXXXXX

00000000 0 10 1 8 4 2 7 1 | XX XXXXXXXX

Now sit there for a cycle:

00000000 1 1 1 0 0 1 0 1 | XX XXXXXXXX

00000000 1 1 4 8 8 1 0 1 | 00 XXXXXXXX

00000000 1 1 4 8 4 1 0 1 | 01 04030201

00000000 1 1 4 8 2 1 0 1 | 02 05040302

00000000 1 1 4 8 1 1 0 1 | 03 06050403

00000000 0 1 1 0 4 8 8 1 | 00 XXXXXXXX

00000000 0 1 1 0 4 8 4 1 | 01 04030201

00000000 0 1 1 0 4 8 2 1 | 02 05040302

00000000 0 1 1 0 4 8 1 1 | 03 06050403

00000000 0 1 1 0 2 4 8 1 | 04 07060504

00000000 0 1 1 0 2 4 4 1 | 05 08070605

00000000 0 1 1 0 2 4 2 1 | 06 09080706

00000000 0 1 1 0 2 4 1 1 | 07 0A090807

00000000 0 1 1 0 1 2 8 1 | 08 0B0A0908

00000000 0 1 1 0 1 2 4 1 | 09 0C0B0A09

00000000 0 1 1 0 1 2 2 1 | 0A 0D0C0B0A

00000000 0 1 1 0 1 2 1 1 | 0B 0E0D0C0B

00000000 0 1 1 0 8 1 8 1 | 0C 0F0E0D0C

00000000 0 1 1 0 8 1 4 1 | 0D 000F0E0D

00000000 0 1 1 0 8 1 2 1 | 0E 01000F0E

00000000 0 1 1 0 8 1 1 1 | 0F 0201000F

00000000 0 1 1 0 8 1 1 1 | 0F 03020100

xbus reset load nen writeIbuf selNext selcur sel selibdat | opcode ibsres