DIRECTORY Basics, BitOps, Core, CoreClasses, CoreCreate, CoreFlat, CoreProperties, Logic, Ports, Rosemary, RosemaryUser, TamPorts, Rope, TamDefs, TerminalIO; TamRegFile6TCell: CEDAR PROGRAM IMPORTS CoreCreate, CoreFlat, CoreClasses, Logic, Ports, Rosemary, TamPorts, TerminalIO = BEGIN OPEN TamDefs, TamPorts; busBits: NAT _ 32; RegFile6TRamCellState: TYPE = REF RegFile6TRamCellStateRec; RegFile6TRamCellStateRec: TYPE = RECORD [in, nIn, selWrite, out, vdd, gnd: NAT _ LAST[NAT], storedval: NAT]; regFile6TCellName: Rope.ROPE = Rosemary.Register[roseClassName: "RegFile6TRamCell", init: RegFile6TRamCellInit, evalSimple: RegFile6TRamCellEvalSimple]; Reg6TRamCell: PUBLIC PROC RETURNS [ct: CoreCreate.CellType] = { ct _ CoreClasses.CreateUnspecified[ name: regFile6TCellName, public: CoreCreate.Wires["In", "nIn", "Out", "SelWrite", "Vdd", "Gnd"]]; [] _ Rosemary.BindCellType[cellType: ct, roseClassName: regFile6TCellName]; [] _ CoreFlat.CellTypeCutLabels[ct, Logic.logicCutSet]; TerminalIO.PutRope["Creating 6T RamCell"]; }; RegFile6TRamCellInit: Rosemary.InitProc = { state: RegFile6TRamCellState _ NEW[RegFile6TRamCellStateRec]; [] _ Ports.InitPorts[cellType, l, none, "Vdd", "Gnd"]; [] _ Ports.InitPorts[cellType, l, none, "In", "nIn", "SelWrite"]; [] _ Ports.InitPorts[cellType, l, drive, "Out",]; [state.vdd, state.gnd] _ Ports.PortIndexes[cellType.public, "Vdd", "Gnd"]; [state.in, state.nIn, state.selWrite, state.out] _ Ports.PortIndexes[cellType.public, "In", "nIn", "SelWrite", "Out"]; state.storedval _ 0; [] _ Rosemary.SetFixedWire[cellType.public[state.vdd], H]; [] _ Rosemary.SetFixedWire[cellType.public[state.gnd], L]; stateAny _ state; }; RegFile6TRamCellEvalSimple: Rosemary.EvalProc = { state: RegFile6TRamCellState _ NARROW[stateAny]; xS: BOOL _ HasXs[p, state.in] OR HasXs[p, state.nIn] OR HasXs[p, state.selWrite]; IF NOT xS THEN IF PortToNat[p, state.selWrite] = 1 THEN { in: NAT _ PortToNat[p, state.in]; nIn: NAT _ PortToNat[p, state.nIn]; IF (in + nIn) = 1 THEN state.storedval _ in; }; IF state.storedval = 1 THEN {SetP[p, state.out, state.storedval]; p[state.out].d _ none; p[state.out].d _ drive;} ELSE {SetP[p, state.out, state.storedval]; p[state.out].d _ drive;}; stateAny _ state; }; END. rTamRegFile6TCell.mesa Copyright س 1987 by Xerox Corporation. All rights reserved. June 22, 1987 4:53:50 pm PDT Last Edited by: Krivacic April June 26, 1987 3:09:37 pm PDT -------------------- RegFile6TRamCell --------------------- --PROC [cellType: Core.CellType, p: Ports.Port] RETURNS [stateAny: REF ANY _ NIL]-- PROC [p: Ports.Port, stateAny: REF ANY]-- ‌تtکJڑœڈدkدr™¬JکJکJڑ‌ ک Icodeڑœ“ک“Jکڑدnœ‌œ‌کJڑ‌œPکWJکJڑœ‌œ‌œک JکJڑœ ‌œکJکJکJکJ™J™Jڑدcœ œ™;JکJڑœ‌œ‌œک;Kڑ œ‌œ‌œ$‌œ‌œ‌œ‌œکlKکKکKڑœ‌œ|ککKکڑںœ‌œ‌œ‌œک?ک#KڑœکKڑœHکHKڑœKکKKڑœ7ک7Kک*Kڑœک——KکKکڑںœک+K™Kڑ S™SKکKڑœ‌œک=KکKڑœ6ک6KڑœAکAKڑœ1ک1KکKڑœJکJKڑœvکvKکKکKکKڑœ:ک:Kڑœ:ک:KڑœکKڑœکKک—Jکڑںœک1JکJڑ‌œ‌œ‌œ ™*JکJڑœ‌œک0Jڑœ‌œ‌œ‌œکSJکڑ‌œ‌œ‌œکڑ‌œ#‌œک+Jڑœ‌œک!Jڑœ‌œک#Jڑ‌œ‌œک,JکJک——Jڑ‌œ‌œX‌œ@ک·JڑœکJڑœک—JککJک—JکJکJکJکJکJکJڑ‌œک—J™—…—عہ