DIRECTORY Basics,TamarinBlocks, TamDefs; TamPc:  CEDAR PROGRAM IMPORTS TamDefs = BEGIN OPEN TamDefs;PcLogic: PUBLIC PROC [d1, r: Word, xBus: Word, topCxt, nextRegCxt: FourBitIndex, pcRaddrSel, pcWaddrSel: OneBitIndex, opLength: ThreeBitIndex, opLength0: OneBitIndex, clock: OneBitIndex] RETURNS [pcNext: Word, d2: Word] = {};iBufRegs: ARRAY [0..7] OF Word;lastIBufDataRegsClock, lastIBufDriveClock: NAT _ 0;iBufDataLatch: Word;ShiftAmountDecode: PROC [shiftlines: NAT] RETURNS [shiftamount: NAT] = {shiftamount _ SELECT shiftlines FROM 8=>0, 4=>8, 2=>16, 1=>24 ENDCASE=> 0;};DecodeToIndex: PROC [decoder: NAT] RETURNS [index: NAT] = {index _ SELECT decoder FROM 128=>0, 64=>1, 32=>2, 16=>3, 8=>4, 4=>5, 2=>6, 1=>7 ENDCASE=> 0;};IBufDataRegs: PUBLIC PROC [iBSres: Word, selIBufData, reset, load, clock: NAT] RETURNS [D1: Word _ ZerosWord] = {IF (clock = 1) AND (lastIBufDataRegsClock = 0) THEN {shiftdist: NAT _ SELECT reset FROM 0=>0, 8=>8, 12=>16, 14=>24, 15=>32, ENDCASE => ERROR;iBufDataLatch _ SingleWordShiftRight[SingleWordShiftLeft[iBSres, shiftdist], shiftdist];};lastIBufDataRegsClock _ clock;IF selIBufData = 1 THEN D1 _ iBufDataLatch;};IShifter: PUBLIC PROC [curIWd, nextIWd: Word, sel: NAT] RETURNS [iBSres: Word,  ibufN, opCode: NAT] = {shiftDist: NAT _ ShiftAmountDecode[sel];opCode _ ByteToCard[WordToBytes[DoubleWordShiftRight[curIWd, nextIWd, shiftDist]][3]];iBSres _ DoubleWordShiftRight[curIWd, nextIWd, shiftDist + 8];ibufN _  ByteToCard[WordToBytes[iBSres][3]];};IBufReg: PUBLIC PROC [ibl, nibl: Word, selCur, selNext, selWrite: NAT] RETURNS [curIWd, nextIWd: Word] = {IF (ibl # OnesWord) OR (nibl # OnesWord) THEN iBufRegs[DecodeToIndex[selWrite]] _ ibl;curIWd _ iBufRegs[DecodeToIndex[selCur]];nextIWd _ iBufRegs[DecodeToIndex[selNext]];};IBufDrive: PUBLIC PROC [xBus: Word, nWtIBuf, clock: NAT] RETURNS [ibl, nibl: Word _ OnesWord] = {IF (clock = 0) AND (nWtIBuf = 0) THEN {ibl _ xBus;nibl _  TamNot[xBus];};};END.  f  TamPc.mesaCopyright س 1987 by Xerox Corporation.  All rights reserved.Krivacic April 10, 1987 12:55:33 pm PSTLast Edited by: Krivacic April 13, 1987 4:34:43 pm PST-- Instruction Buffer Latches & State Info-- shiftlines: [8 4 2 1] bit select line for what byte (8 = msb)-- decoder: [128, 64, 32, 16, 8 4 2 1] bit select line for index (1 = msb)‌ت¨  ک ™
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