Basics, BitOps, Core, CoreClasses, CoreCreate, CoreFlat, CoreProperties, Logic, Ports, Rosemary, RosemaryUser, TamPorts, Rope, TamDefs, TerminalIO;
TamRegFile6TCell:
CEDAR
PROGRAM
IMPORTS CoreCreate, CoreFlat, CoreClasses, Logic, Ports, Rosemary, TamPorts, TerminalIO
= BEGIN OPEN TamDefs, TamPorts;
busBits: NAT ← 32;
-------------------- RegFile6TRamCell ---------------------
RegFile6TRamCellState: TYPE = REF RegFile6TRamCellStateRec;
RegFile6TRamCellStateRec: TYPE = RECORD [in, nIn, selWrite, out, vdd, gnd: NAT ← LAST[NAT], storedval: NAT];
regFile6TCellName: Rope.ROPE = Rosemary.Register[roseClassName: "RegFile6TRamCell", init: RegFile6TRamCellInit, evalSimple: RegFile6TRamCellEvalSimple];
Reg6TRamCell:
PUBLIC
PROC
RETURNS [ct: CoreCreate.CellType] = {
ct ← CoreClasses.CreateUnspecified[
name: regFile6TCellName,
public: CoreCreate.Wires["In", "nIn", "Out", "SelWrite", "Vdd", "Gnd"]];
[] ← Rosemary.BindCellType[cellType: ct, roseClassName: regFile6TCellName];
[] ← CoreFlat.CellTypeCutLabels[ct, Logic.logicCutSet];
TerminalIO.PutRope["Creating 6T RamCell"];
};
RegFile6TRamCellInit: Rosemary.InitProc = {
--PROC [cellType: Core.CellType, p: Ports.Port] RETURNS [stateAny: REF ANY ← NIL]--
state: RegFile6TRamCellState ← NEW[RegFile6TRamCellStateRec];
[] ← Ports.InitPorts[cellType, l, none, "Vdd", "Gnd"];
[] ← Ports.InitPorts[cellType, l, none, "In", "nIn", "SelWrite"];
[] ← Ports.InitPorts[cellType, l, drive, "Out",];
[state.vdd, state.gnd] ← Ports.PortIndexes[cellType.public, "Vdd", "Gnd"];
[state.in, state.nIn, state.selWrite, state.out] ← Ports.PortIndexes[cellType.public, "In", "nIn", "SelWrite", "Out"];
state.storedval ← 0;
[] ← Rosemary.SetFixedWire[cellType.public[state.vdd], H];
[] ← Rosemary.SetFixedWire[cellType.public[state.gnd], L];
stateAny ← state;
};
RegFile6TRamCellEvalSimple: Rosemary.EvalProc = {
PROC [p: Ports.Port, stateAny: REF ANY]--
state: RegFile6TRamCellState ← NARROW[stateAny];
xS: BOOL ← HasXs[p, state.in] OR HasXs[p, state.nIn] OR HasXs[p, state.selWrite];
IF
NOT xS
THEN
IF PortToNat[p, state.selWrite] = 1
THEN {
in: NAT ← PortToNat[p, state.in];
nIn: NAT ← PortToNat[p, state.nIn];
IF (in + nIn) = 1 THEN state.storedval ← in;
};
IF state.storedval = 1 THEN
{SetP[p, state.out, state.storedval]; p[state.out].d ← none; p[state.out].d ← drive;}
ELSE {SetP[p, state.out, state.storedval]; p[state.out].d ← drive;};
stateAny ← state;
};
END.