TamIBuf6TCell.mesa
Copyright Ó 1987 by Xerox Corporation. All rights reserved.
July 1, 1987 9:52:11 am PDT
Last Edited by: Krivacic April June 26, 1987 3:09:37 pm PDT
DIRECTORY

Basics, BitOps, Core, CoreClasses, CoreCreate, CoreFlat, CoreProperties, Logic, Ports, Rosemary, RosemaryUser, TamPorts, Rope, TamDefs, TerminalIO;
TamIBuf6TCell: CEDAR PROGRAM
IMPORTS CoreCreate, CoreFlat, CoreClasses, Logic, Ports, Rosemary, TamPorts, TerminalIO
= BEGIN OPEN TamDefs, TamPorts;
busBits: NAT ← 32;
-------------------- IBuf6TRamCell ---------------------
IBuf6TRamCellState: TYPE = REF IBuf6TRamCellStateRec;
IBuf6TRamCellStateRec: TYPE = RECORD [in, nIn, selWrite, out, vdd, gnd: NATLAST[NAT], storedval: NAT];
IBuf6TCellName: Rope.ROPE = Rosemary.Register[roseClassName: "IBuf6TRamCell", init: IBufFile6TRamCellInit, evalSimple: IBuf6TRamCellEvalSimple];
IBuf6TRamCell: PUBLIC PROC RETURNS [ct: CoreCreate.CellType] = {
ct ← CoreClasses.CreateUnspecified[
name: IBuf6TCellName,
public: CoreCreate.Wires["In", "nIn", "Out", "SelWrite", "Vdd", "Gnd"]];
[] ← Rosemary.BindCellType[cellType: ct, roseClassName: IBuf6TCellName];
[] ← CoreFlat.CellTypeCutLabels[ct, Logic.logicCutSet];
TerminalIO.PutRope["Creating IBuf 6T RamCell\n"];
};
IBufFile6TRamCellInit: Rosemary.InitProc = {
--PROC [cellType: Core.CellType, p: Ports.Port] RETURNS [stateAny: REF ANY ← NIL]--
state: IBuf6TRamCellState ← NEW[IBuf6TRamCellStateRec];
[] ← Ports.InitPorts[cellType, l, none, "Vdd", "Gnd"];
[] ← Ports.InitPorts[cellType, l, none, "In", "nIn", "SelWrite"];
[] ← Ports.InitPorts[cellType, l, drive, "Out",];
[state.vdd, state.gnd] ← Ports.PortIndexes[cellType.public, "Vdd", "Gnd"];
[state.in, state.nIn, state.selWrite, state.out] ← Ports.PortIndexes[cellType.public, "In", "nIn", "SelWrite", "Out"];
state.storedval ← 0;
[] ← Rosemary.SetFixedWire[cellType.public[state.vdd], H];
[] ← Rosemary.SetFixedWire[cellType.public[state.gnd], L];
stateAny ← state;
};
IBuf6TRamCellEvalSimple: Rosemary.EvalProc = {
PROC [p: Ports.Port, stateAny: REF ANY]--
state: IBuf6TRamCellState ← NARROW[stateAny];
xS: BOOL ← HasXs[p, state.in] OR HasXs[p, state.nIn] OR HasXs[p, state.selWrite];
IF NOT xS THEN
IF PortToNat[p, state.selWrite] = 1 THEN {
in: NAT ← PortToNat[p, state.in];
nIn: NAT ← PortToNat[p, state.nIn];
IF (in + nIn) = 1 THEN state.storedval ← in;
};
IF state.storedval = 1 THEN
{SetP[p, state.out, state.storedval]; p[state.out].d ← none; p[state.out].d ← drive;}
ELSE {SetP[p, state.out, state.storedval]; p[state.out].d ← drive;};
stateAny ← state;
};
END.