<> <<>> <<>> DIRECTORY Basics, BitOps, Core, CoreClasses, CoreCreate, CoreProperties, Ports, Rosemary, RosemaryUser, TamPorts, TamEu, Rope, TamDefs, TamPc; PcCells: CEDAR PROGRAM IMPORTS Ports, Rosemary, TamPorts, TamEu, TamPc, Basics = BEGIN OPEN TamDefs, TamPorts; BoolToInt: PROC [b: BOOL] RETURNS [NAT] = {RETURN[IF b THEN 1 ELSE 0]}; busBits: NAT _ 32; <<-------------------- PcLogic --------------------->> PcState: TYPE = REF PcStateRec; PcStateRec: TYPE = RECORD [d1, d2, r, xBus, topCxt, nextRegCxt, pcRaddrSel, pcWaddrSel, opLength, opLength0, clock, pcNext, vdd, gnd: NAT _ LAST[NAT]]; PcInit: Rosemary.InitProc = { <<>> <<--PROC [cellType: Core.CellType, p: Ports.Port] RETURNS [stateAny: REF ANY _ NIL]-->> state: PcState _ NEW[PcStateRec]; [] _ Ports.InitPorts[cellType, ls, none, "D1", "D2", "EUControl", "nEUControl"]; [] _ Ports.InitPorts[cellType, ls, drive, "R"]; <<[state.d1, state.d2, state.r, state.euControl, state.nEuControl, state.vdd, state.gnd] _ Ports.PortIndexes[cellType.public, "D1", "D2", "R", "EUControl", "nEUControl", "Vdd", "Gnd"];>> [] _ Rosemary.SetFixedWire[cellType.public[state.vdd], H]; [] _ Rosemary.SetFixedWire[cellType.public[state.gnd], L]; stateAny _ state; }; PcEvalSimple: Rosemary.EvalProc = { <<>> <<-- PROC [p: Ports.Port, stateAny: REF ANY]-->> state: PcState _ NARROW[stateAny]; <> <> <> <> <> <> <> <> <> <> <<>> <> }; <<-------------------- IBufLogic --------------------->> IBufState: TYPE = REF IBufStateRec; IBufStateRec: TYPE = RECORD [d1, d2, xBus, pcNext, ibWaddr, wtIbuf, stopIBWt, opLength, opLength0, selIBufData, clock, r, ibufN, opCode, vdd, gnd: NAT _ LAST[NAT], iBufArray: ARRAY [0..7] OF CARD, valid: ARRAY[0..7] OF BOOL, lastClock: BOOL ]; IBufInit: Rosemary.InitProc = { <<>> <<--PROC [cellType: Core.CellType, p: Ports.Port] RETURNS [stateAny: REF ANY _ NIL]-->> state: IBufState _ NEW[IBufStateRec]; [] _ Ports.InitPorts[cellType, l, none, "Vdd", "Gnd"]; [] _ Ports.InitPorts[cellType, ls, none, "D1", "D2", "XBus", "PCNext", "IbWaddr", "WtIbuf", "StopIbWt", "OpLength", "OpLength0", "SelIBufData", "Clock"]; [] _ Ports.InitPorts[cellType, ls, drive, "R", "IbufN", "OpCode"]; [state.vdd, state.gnd] _ Ports.PortIndexes[cellType.public, "Vdd", "Gnd"]; [state.d1, state.d2, state.xBus, state.pcNext, state.ibWaddr, state.wtIbuf, state.stopIBWt, state.opLength, state.opLength0, state.selIBufData, state.clock] _ Ports.PortIndexes[cellType.public, "D1", "D2", "XBus", "PCNext", "IbWaddr", "WtIbuf", "StopIbWt", "OpLength", "OpLength0", "SelIBufData", "Clock"]; [state.r, state.ibufN, state.opCode] _ Ports.PortIndexes[cellType.public, "R", "IbufN", "OpCode"]; state.valid _ [FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE]; state.iBufArray _ [0, 0, 0, 0, 0, 0, 0, 0]; state.lastClock _ FALSE; [] _ Rosemary.SetFixedWire[cellType.public[state.vdd], H]; [] _ Rosemary.SetFixedWire[cellType.public[state.gnd], L]; stateAny _ state; }; IBufEvalSimple: Rosemary.EvalProc = { <> overFlow, carry, gt: BOOL _ FALSE; state: IBufState _ NARROW[stateAny]; <> }; <<-------------------- InstDP --------------------->> InstDPState: TYPE = REF InstDPStateRec; InstDPStateRec: TYPE = RECORD [d1, r, load, nByteSel, selIBufData, shiftSel, selCur, selNext, selWrite, nWtIBuf, clock, ibufN, opCode, xBus, vdd, gnd: NAT _ LAST[NAT], iBufArray: ARRAY [0..7] OF CARD, valid: ARRAY[0..7] OF BOOL, lastClock: BOOL ]; InstDPInit: Rosemary.InitProc = { <<>> <<--PROC [cellType: Core.CellType, p: Ports.Port] RETURNS [stateAny: REF ANY _ NIL]-->> state: InstDPState _ NEW[InstDPStateRec]; [] _ Ports.InitPorts[cellType, l, none, "Vdd", "Gnd"]; [] _ Ports.InitPorts[cellType, ls, none, "R", "load", "nByteSel", "SelIBufData", "ShiftSel", "SelCur", "SelNext", "SelWrite", "nWtIBuf", "CK", "XBus"]; [] _ Ports.InitPorts[cellType, ls, drive, "D1", "IbufN", "OpCode"]; [state.vdd, state.gnd] _ Ports.PortIndexes[cellType.public, "Vdd", "Gnd"]; [state.r, state.load, state.nByteSel, state.selIBufData, state.shiftSel, state.selCur, state.selNext, state.selWrite, state.nWtIBuf, state.clock, state.xBus] _ Ports.PortIndexes[cellType.public, "R", "load", "nByteSel", "SelIBufData", "ShiftSel", "SelCur", "SelNext", "SelWrite", "nWtIBuf", "CK", "XBus"]; [state.d1, state.ibufN, state.opCode] _ Ports.PortIndexes[cellType.public, "D1", "IbufN", "OpCode"]; state.valid _ [FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE]; state.iBufArray _ [0, 0, 0, 0, 0, 0, 0, 0]; state.lastClock _ FALSE; [] _ Rosemary.SetFixedWire[cellType.public[state.vdd], H]; [] _ Rosemary.SetFixedWire[cellType.public[state.gnd], L]; stateAny _ state; }; InstDPEvalSimple: Rosemary.EvalProc = { <> ibl, nibl, curIWd, nextIWd, iBSres, D1: TamDefs.Word _ ZerosWord; ibufN, opCode, selIBufData: NAT _ 0; state: InstDPState _ NARROW[stateAny]; xS: BOOL _ HasXs[p, state.selCur] OR HasXs[p, state.selNext] OR HasXs[p, state.selWrite]; ClrP[p, state.ibufN]; ClrP[p, state.opCode]; IF NOT xS THEN { IF NOT (HasXs[p, state.xBus] OR HasXs[p, state.nWtIBuf] OR HasXs[p, state.clock]) THEN [ibl, nibl] _ TamPc.IBufDrive[ PortToTamWord[p, state.xBus], PortToNat[p, state.nWtIBuf], PortToNat[p, state.clock]]; IF NOT (HasXs[p, state.selCur] OR HasXs[p, state.selNext] OR HasXs[p, state.selWrite]) THEN [curIWd, nextIWd] _ TamPc.IBufReg[ibl, nibl, PortToNat[p, state.selCur], PortToNat[p, state.selNext], PortToNat[p, state.selWrite]]; IF NOT TamPorts.HasXs[p, state.shiftSel] THEN [iBSres, ibufN, opCode] _ TamPc.IShifter[curIWd, nextIWd, PortToNat[p, state.shiftSel]]; SetP[p, state.opCode, opCode]; SetP[p, state.ibufN, ibufN]; IF NOT (HasXs[p, state.selIBufData] OR HasXs[p, state.nByteSel] OR HasXs[p, state.load] OR HasXs[p, state.clock]) THEN D1 _ TamPc.IBufDataRegs[iBSres, selIBufData _ PortToNat[p, state.selIBufData], Basics.BITXOR[PortToNat[p, state.nByteSel], 0FH], PortToNat[p, state.load], PortToNat[p, state.clock]]; }; IF selIBufData = 1 THEN SetPWord[p, state.d1, D1] ELSE ClrP[p, state.d1]; }; <<-------------------- IBuf6TCell --------------------->> IBuf6TCellState: TYPE = REF IBuf6TCellStateRec; IBuf6TCellStateRec: TYPE = RECORD [in, nIn, selWrite, out, vdd, gnd: NAT _ LAST[NAT], storedval: NAT]; IBuf6TCellInit: Rosemary.InitProc = { <<>> <<--PROC [cellType: Core.CellType, p: Ports.Port] RETURNS [stateAny: REF ANY _ NIL]-->> state: IBuf6TCellState _ NEW[IBuf6TCellStateRec]; [] _ Ports.InitPorts[cellType, l, none, "Vdd", "Gnd"]; [] _ Ports.InitPorts[cellType, ls, none, "In", "nIn", "SelWrite"]; [] _ Ports.InitPorts[cellType, ls, drive, "Out",]; [state.vdd, state.gnd] _ Ports.PortIndexes[cellType.public, "Vdd", "Gnd"]; [state.in, state.nIn, state.selWrite, state.out] _ Ports.PortIndexes[cellType.public, "In", "nIn", "SelWrite", "Out"]; state.storedval _ 0; [] _ Rosemary.SetFixedWire[cellType.public[state.vdd], H]; [] _ Rosemary.SetFixedWire[cellType.public[state.gnd], L]; stateAny _ state; }; IBuf6TCellEvalSimple: Rosemary.EvalProc = { <> state: IBuf6TCellState _ NARROW[stateAny]; xS: BOOL _ HasXs[p, state.in] OR HasXs[p, state.nIn] OR HasXs[p, state.selWrite]; IF NOT xS THEN IF PortToNat[p, state.selWrite] = 1 THEN { in: NAT _ PortToNat[p, state.in]; nIn: NAT _ PortToNat[p, state.nIn]; IF (in + nIn) = 1 THEN state.storedval _ in; }; SetP[p, state.out, state.storedval]; p[state.out].d _ drive; stateAny _ state; }; iBuf6TCellName: Rope.ROPE = Rosemary.Register[roseClassName: "IBuf6TCell", init: IBuf6TCellInit, evalSimple: IBuf6TCellEvalSimple]; instDPName: Rope.ROPE = Rosemary.Register[roseClassName: "InstDP", init: InstDPInit, evalSimple: InstDPEvalSimple]; iBufLogicName: Rope.ROPE = Rosemary.Register[roseClassName: "IBufLogic", init: IBufInit, evalSimple: IBufEvalSimple]; PcName: Rope.ROPE = Rosemary.Register[roseClassName: "PcLogic", init: PcInit, evalSimple: PcEvalSimple]; END. <<>>