Basics, BitOps, Core, CoreClasses, CoreCreate, CoreProperties, Ports, Rosemary, RosemaryUser, TamPorts, TamEu, Rope, TamDefs, TamPc;
PcCells:
CEDAR
PROGRAM
IMPORTS Ports, Rosemary, TamPorts, TamEu, TamPc, Basics
= BEGIN OPEN TamDefs, TamPorts;
BoolToInt: PROC [b: BOOL] RETURNS [NAT] = {RETURN[IF b THEN 1 ELSE 0]};
busBits: NAT ← 32;
-------------------- PcLogic ---------------------
PcState: TYPE = REF PcStateRec;
PcStateRec: TYPE = RECORD [d1, d2, r, xBus, topCxt, nextRegCxt, pcRaddrSel, pcWaddrSel, opLength, opLength0, clock, pcNext, vdd, gnd: NAT ← LAST[NAT]];
PcInit: Rosemary.InitProc = {
--PROC [cellType: Core.CellType, p: Ports.Port] RETURNS [stateAny: REF ANY ← NIL]--
state: PcState ← NEW[PcStateRec];
[] ← Ports.InitPorts[cellType, ls, none, "D1", "D2", "EUControl", "nEUControl"];
[] ← Ports.InitPorts[cellType, ls, drive, "R"];
[state.d1, state.d2, state.r, state.euControl, state.nEuControl, state.vdd, state.gnd] ← Ports.PortIndexes[cellType.public, "D1", "D2", "R", "EUControl", "nEUControl", "Vdd", "Gnd"];
[] ← Rosemary.SetFixedWire[cellType.public[state.vdd], H];
[] ← Rosemary.SetFixedWire[cellType.public[state.gnd], L];
stateAny ← state;
};
PcEvalSimple: Rosemary.EvalProc = {
-- PROC [p: Ports.Port, stateAny: REF ANY]--
state: PcState ← NARROW[stateAny];
hasXs: BOOL ← TamPorts.HasXs[p, state.euControl] OR TamPorts.HasXs[p, state.d1] OR TamPorts.HasXs[p, state.d2];
IF (NOT hasXs) AND (LOOPHOLE[EUSelect[p, state.euControl], EuUnits] = LU) THEN
TamPorts.SetP[
p,
state.r,
TamDefs.WordToCard[
TamEu.LogicalUnit[
EUMask[p, state.euControl],
TamPorts.PortToTamWord[p, state.d1],
TamPorts.PortToTamWord[p, state.d2]]]]
ELSE TamPorts.ClrP[p, state.r];
};
-------------------- IBufLogic ---------------------
IBufState: TYPE = REF IBufStateRec;
IBufStateRec: TYPE = RECORD [d1, d2, xBus, pcNext, ibWaddr, wtIbuf, stopIBWt, opLength, opLength0, selIBufData, clock, r, ibufN, opCode, vdd, gnd: NAT ← LAST[NAT],
iBufArray: ARRAY [0..7] OF CARD,
valid: ARRAY[0..7] OF BOOL,
lastClock: BOOL
];
IBufInit: Rosemary.InitProc = {
--PROC [cellType: Core.CellType, p: Ports.Port] RETURNS [stateAny: REF ANY ← NIL]--
state: IBufState ← NEW[IBufStateRec];
[] ← Ports.InitPorts[cellType, l, none, "Vdd", "Gnd"];
[] ← Ports.InitPorts[cellType, ls, none, "D1", "D2", "XBus", "PCNext", "IbWaddr", "WtIbuf", "StopIbWt", "OpLength", "OpLength0", "SelIBufData", "Clock"];
[] ← Ports.InitPorts[cellType, ls, drive, "R", "IbufN", "OpCode"];
[state.vdd, state.gnd] ← Ports.PortIndexes[cellType.public, "Vdd", "Gnd"];
[state.d1, state.d2, state.xBus, state.pcNext, state.ibWaddr, state.wtIbuf, state.stopIBWt, state.opLength, state.opLength0, state.selIBufData, state.clock] ← Ports.PortIndexes[cellType.public, "D1", "D2", "XBus", "PCNext", "IbWaddr", "WtIbuf", "StopIbWt", "OpLength", "OpLength0", "SelIBufData", "Clock"];
[state.r, state.ibufN, state.opCode] ← Ports.PortIndexes[cellType.public, "R", "IbufN", "OpCode"];
state.valid ← [FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE];
state.iBufArray ← [0, 0, 0, 0, 0, 0, 0, 0];
state.lastClock ← FALSE;
[] ← Rosemary.SetFixedWire[cellType.public[state.vdd], H];
[] ← Rosemary.SetFixedWire[cellType.public[state.gnd], L];
stateAny ← state;
};
IBufEvalSimple: Rosemary.EvalProc = {
PROC [p: Ports.Port, stateAny: REF ANY]--
overFlow, carry, gt: BOOL ← FALSE;
state: IBufState ← NARROW[stateAny];
hasXs: BOOL ← TamPorts.HasXs[p, state.opCode] OR TamPorts.HasXs[p, state.pcNext] OR TamPorts.HasXs[p, state.ibWaddr] OR TamPorts.HasXs[p, state.wtIbuf] OR TamPorts.HasXs[p, state.opLength] OR TamPorts.HasXs[p, state.selIBufData] OR TamPorts.HasXs[p, state.d1] OR TamPorts.HasXs[p, state.d2];
};
-------------------- InstDP ---------------------
InstDPState: TYPE = REF InstDPStateRec;
InstDPStateRec: TYPE = RECORD [d1, r, load, nByteSel, selIBufData, shiftSel, selCur, selNext, selWrite, nWtIBuf, clock, ibufN, opCode, xBus, vdd, gnd: NAT ← LAST[NAT],
iBufArray: ARRAY [0..7] OF CARD,
valid: ARRAY[0..7] OF BOOL,
lastClock: BOOL
];
InstDPInit: Rosemary.InitProc = {
--PROC [cellType: Core.CellType, p: Ports.Port] RETURNS [stateAny: REF ANY ← NIL]--
state: InstDPState ← NEW[InstDPStateRec];
[] ← Ports.InitPorts[cellType, l, none, "Vdd", "Gnd"];
[] ← Ports.InitPorts[cellType, ls, none, "R", "load", "nByteSel", "SelIBufData", "ShiftSel", "SelCur", "SelNext", "SelWrite", "nWtIBuf", "CK", "XBus"];
[] ← Ports.InitPorts[cellType, ls, drive, "D1", "IbufN", "OpCode"];
[state.vdd, state.gnd] ← Ports.PortIndexes[cellType.public, "Vdd", "Gnd"];
[state.r, state.load, state.nByteSel, state.selIBufData, state.shiftSel, state.selCur, state.selNext, state.selWrite, state.nWtIBuf, state.clock, state.xBus] ← Ports.PortIndexes[cellType.public, "R", "load", "nByteSel", "SelIBufData", "ShiftSel", "SelCur", "SelNext", "SelWrite", "nWtIBuf", "CK", "XBus"];
[state.d1, state.ibufN, state.opCode] ← Ports.PortIndexes[cellType.public, "D1", "IbufN", "OpCode"];
state.valid ← [FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE];
state.iBufArray ← [0, 0, 0, 0, 0, 0, 0, 0];
state.lastClock ← FALSE;
[] ← Rosemary.SetFixedWire[cellType.public[state.vdd], H];
[] ← Rosemary.SetFixedWire[cellType.public[state.gnd], L];
stateAny ← state;
};
InstDPEvalSimple: Rosemary.EvalProc = {
PROC [p: Ports.Port, stateAny: REF ANY]--
ibl, nibl, curIWd, nextIWd, iBSres, D1: TamDefs.Word ← ZerosWord;
ibufN, opCode, selIBufData: NAT ← 0;
state: InstDPState ← NARROW[stateAny];
xS: BOOL ← HasXs[p, state.selCur] OR HasXs[p, state.selNext] OR HasXs[p, state.selWrite];
ClrP[p, state.ibufN];
ClrP[p, state.opCode];
IF
NOT xS
THEN {
IF
NOT (HasXs[p, state.xBus]
OR HasXs[p, state.nWtIBuf]
OR HasXs[p, state.clock]
) THEN
[ibl, nibl] ←
TamPc.IBufDrive[
PortToTamWord[p, state.xBus],
PortToNat[p, state.nWtIBuf],
PortToNat[p, state.clock]];
IF
NOT (HasXs[p, state.selCur]
OR HasXs[p, state.selNext]
OR HasXs[p, state.selWrite]
) THEN
[curIWd, nextIWd] ←
TamPc.IBufReg[ibl, nibl,
PortToNat[p, state.selCur],
PortToNat[p, state.selNext],
PortToNat[p, state.selWrite]];
IF
NOT TamPorts.HasXs[p, state.shiftSel]
THEN
[iBSres, ibufN, opCode] ←
TamPc.IShifter[curIWd, nextIWd,
PortToNat[p, state.shiftSel]];
SetP[p, state.opCode, opCode];
SetP[p, state.ibufN, ibufN];
IF
NOT (HasXs[p, state.selIBufData]
OR HasXs[p, state.nByteSel]
OR HasXs[p, state.load]
OR HasXs[p, state.clock]
) THEN
D1 ←
TamPc.IBufDataRegs[iBSres, selIBufData ← PortToNat[p, state.selIBufData],
Basics.BITXOR[PortToNat[p, state.nByteSel], 0FH],
PortToNat[p, state.load],
PortToNat[p, state.clock]];
};
IF selIBufData = 1 THEN SetPWord[p, state.d1, D1] ELSE ClrP[p, state.d1];
};
-------------------- IBuf6TCell ---------------------
IBuf6TCellState: TYPE = REF IBuf6TCellStateRec;
IBuf6TCellStateRec: TYPE = RECORD [in, nIn, selWrite, out, vdd, gnd: NAT ← LAST[NAT], storedval: NAT];
IBuf6TCellInit: Rosemary.InitProc = {
--PROC [cellType: Core.CellType, p: Ports.Port] RETURNS [stateAny: REF ANY ← NIL]--
state: IBuf6TCellState ← NEW[IBuf6TCellStateRec];
[] ← Ports.InitPorts[cellType, l, none, "Vdd", "Gnd"];
[] ← Ports.InitPorts[cellType, ls, none, "In", "nIn", "SelWrite"];
[] ← Ports.InitPorts[cellType, ls, drive, "Out",];
[state.vdd, state.gnd] ← Ports.PortIndexes[cellType.public, "Vdd", "Gnd"];
[state.in, state.nIn, state.selWrite, state.out] ← Ports.PortIndexes[cellType.public, "In", "nIn", "SelWrite", "Out"];
state.storedval ← 0;
[] ← Rosemary.SetFixedWire[cellType.public[state.vdd], H];
[] ← Rosemary.SetFixedWire[cellType.public[state.gnd], L];
stateAny ← state;
};
IBuf6TCellEvalSimple: Rosemary.EvalProc = {
PROC [p: Ports.Port, stateAny: REF ANY]--
state: IBuf6TCellState ← NARROW[stateAny];
xS: BOOL ← HasXs[p, state.in] OR HasXs[p, state.nIn] OR HasXs[p, state.selWrite];
IF
NOT xS
THEN
IF PortToNat[p, state.selWrite] = 1
THEN {
in: NAT ← PortToNat[p, state.in];
nIn: NAT ← PortToNat[p, state.nIn];
IF (in + nIn) = 1 THEN state.storedval ← in;
};
SetP[p, state.out, state.storedval];
p[state.out].d ← drive;
stateAny ← state;
};
iBuf6TCellName: Rope.ROPE = Rosemary.Register[roseClassName: "IBuf6TCell", init: IBuf6TCellInit, evalSimple: IBuf6TCellEvalSimple];
instDPName: Rope.ROPE = Rosemary.Register[roseClassName: "InstDP", init: InstDPInit, evalSimple: InstDPEvalSimple];
iBufLogicName: Rope.ROPE = Rosemary.Register[roseClassName: "IBufLogic", init: IBufInit, evalSimple: IBufEvalSimple];
PcName: Rope.ROPE = Rosemary.Register[roseClassName: "PcLogic", init: PcInit, evalSimple: PcEvalSimple];
END.