<> <<>> <<>> DIRECTORY EuLu, BitOps, Core, CoreClasses, CoreCreate, CoreProperties, Ports, Rosemary, RosemaryUser, TamarinPorts, TamarinOpsUtils, TamarinBlocks, Rope; EuLuImpl: CEDAR PROGRAM IMPORTS CoreClasses, CoreCreate, Ports, Rosemary, TamarinPorts, TamarinBlocks, TamarinOpsUtils EXPORTS EuLu = BEGIN d1, d2, r, luEuop, selLu, Vdd, Gnd: NAT _ LAST[NAT]; luCt: Core.CellType; busBits: NAT _ 32; euopBits: NAT _ 4; Create: PUBLIC PROC RETURNS [ct: Core.CellType] = { luCt _ CoreClasses.CreateUnspecified[ public: CoreCreate.WireList[ LIST[ CoreCreate.Seq["D1", busBits], CoreCreate.Seq["D2", busBits], CoreCreate.Seq["R", busBits], CoreCreate.Seq["LUEuop", euopBits], "SelLU","Vdd", "Gnd"], "EuLu", NIL], name: luName ]; ct _ luCt; [] _ Rosemary.BindCellType[cellType: ct, roseClassName: luName]; InitPortIndicies[ct]; [] _ Ports.InitPorts[ct, ls, none, "D1"]; [] _ Ports.InitPorts[ct, ls, none, "D2"]; [] _ Ports.InitPorts[ct, ls, none, "R"]; [] _ Ports.InitPorts[ct, ls, none, "LUEuop"]; [] _ Ports.InitPorts[ct, l, none, "SelLU"]; }; LuInit: Rosemary.InitProc = { <<>> <<--PROC [cellType: Core.CellType, p: Ports.Port] RETURNS [stateAny: REF ANY _ NIL]-->> RETURN[NIL]; }; InitPortIndicies: PROC [ct: Core.CellType] = { [d1, d2, r, luEuop, selLu, Vdd, Gnd] _ Ports.PortIndexes[ct.public, "D1", "D2", "R", "LUEuop", "SelLU", "Vdd", "Gnd"]; }; LuEvalSimple: Rosemary.EvalProc = { <> IF TamarinPorts.PortToBool[p, selLu] THEN TamarinPorts.SetP[ p, r, TamarinOpsUtils.WordToCard[ TamarinBlocks.LogicalUnit[ TamarinPorts.PortToCard[p, luEuop], TamarinPorts.PortToTamWord[p, d1], TamarinPorts.PortToTamWord[p, d2] ] ] ]; }; luName: Rope.ROPE = Rosemary.Register[roseClassName: "EuLu", init: LuInit, evalSimple: LuEvalSimple]; END. <<>>