EuLu, BitOps, Core, CoreClasses, CoreCreate, CoreProperties, Ports, Rosemary, RosemaryUser, TamarinPorts, TamarinOpsUtils, TamarinBlocks, Rope;
EuLuImpl:
CEDAR
PROGRAM
IMPORTS CoreClasses, CoreCreate, Ports, Rosemary, TamarinPorts, TamarinBlocks, TamarinOpsUtils
EXPORTS EuLu
= BEGIN
d1, d2, r, luEuop, selLu, Vdd, Gnd: NAT ← LAST[NAT];
luCt: Core.CellType;
busBits: NAT ← 32;
euopBits: NAT ← 4;
Create:
PUBLIC
PROC
RETURNS [ct: Core.CellType] = {
luCt ← CoreClasses.CreateUnspecified[
public: CoreCreate.WireList[
LIST[
CoreCreate.Seq["D1", busBits],
CoreCreate.Seq["D2", busBits],
CoreCreate.Seq["R", busBits],
CoreCreate.Seq["LUEuop", euopBits],
"SelLU","Vdd", "Gnd"],
"EuLu", NIL],
name: luName
];
ct ← luCt;
[] ← Rosemary.BindCellType[cellType: ct, roseClassName: luName];
InitPortIndicies[ct];
[] ← Ports.InitPorts[ct, ls, none, "D1"];
[] ← Ports.InitPorts[ct, ls, none, "D2"];
[] ← Ports.InitPorts[ct, ls, none, "R"];
[] ← Ports.InitPorts[ct, ls, none, "LUEuop"];
[] ← Ports.InitPorts[ct, l, none, "SelLU"];
};
LuInit: Rosemary.InitProc = {
--PROC [cellType: Core.CellType, p: Ports.Port] RETURNS [stateAny: REF ANY ← NIL]--
RETURN[NIL];
};
InitPortIndicies:
PROC [ct: Core.CellType] = {
[d1, d2, r, luEuop, selLu, Vdd, Gnd] ← Ports.PortIndexes[ct.public, "D1", "D2", "R", "LUEuop", "SelLU", "Vdd", "Gnd"];
};
LuEvalSimple: Rosemary.EvalProc = {
PROC [p: Ports.Port, stateAny: REF ANY]--
IF TamarinPorts.PortToBool[p, selLu]
THEN
TamarinPorts.SetP[
p,
r,
TamarinOpsUtils.WordToCard[
TamarinBlocks.LogicalUnit[
TamarinPorts.PortToCard[p, luEuop],
TamarinPorts.PortToTamWord[p, d1],
TamarinPorts.PortToTamWord[p, d2]
]
]
];
};
luName: Rope.ROPE = Rosemary.Register[roseClassName: "EuLu", init: LuInit, evalSimple: LuEvalSimple];
END.